SN74LVCC3245A OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS SCAS585F – NOVEMBER 1996 – REVISED AUGUST 1998 D D D D EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages DB, DW, OR PW PACKAGE (TOP VIEW) VCCA DIR A1 A2 A3 A4 A5 A6 A7 A8 GND GND description This 8-bit (octal) noninverting bus transceiver contains two separate supply rails. The B port is designed to track VCCB, which accepts voltages from 3 V to 5.5 V, and the A port is designed to track VCCA, which operates at 2.3 V to 3.6 V. This allows for translation from a 3.3-V to a 5-V system environment and vice versa, or from a 2.5-V to a 3.3-V system environment and vice versa. 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCCB NC OE B1 B2 B3 B4 B5 B6 B7 B8 GND NC – No internal connection The SN74LVCC3245A is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are effectively isolated. The SN74LVCC3245A is characterized for operation from –40°C to 85°C. FUNCTION TABLE INPUTS OPERATION OE DIR L L B data to A bus L H A data to B bus H X Isolation Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74LVCC3245A OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS SCAS585F – NOVEMBER 1996 – REVISED AUGUST 1998 logic diagram (positive logic) DIR 2 22 OE A1 3 21 B1 To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCCA and VCCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V Input voltage range, VI: All A port (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCCA + 0.5 V All B port (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCCB + 0.5 V Except I/O ports (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCCA + 0.5 V Output voltage range, VO (see Note 1): All A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCCA + 0.5 V All B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCCB + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCCA, VCCB, or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. This value is limited to 6 V maximum. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74LVCC3245A OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS SCAS585F – NOVEMBER 1996 – REVISED AUGUST 1998 recommended operating conditions (see Note 4) VCCA VCCA VCCB Supply voltage 2.3 V VIHA VIHB VILA VCCB Supply voltage High level input voltage High-level High level input voltage High-level Low level input voltage Low-level VOB ≤ 0.1 0 1 V, V VOA ≤ 0.1 0 1 V, V 0 1 V, V VOB ≤ 0.1 VOA ≤ 0.1 0 1 V, V VOB ≥ VCCB – 0 0.1 1V VOA ≥ VCCA – 0 0.1 1V 1V VOB ≥ VCCB – 0 0.1 VOA ≥ VCCA – 0 0.1 1V MIN NOM MAX 2.3 3.3 3.6 V 3 5 5.5 V 3V 1.7 2.7 V 3V 2 3V 3.6 V 2 3.6 V 5.5 V 2 2.3 V 3V 2 2.7 V 3V 2 3V 3.6 V 2 3.6 V 5.5 V 3.85 2.3 V 3V 0.7 2.7 V 3V 0.8 3V 3.6 V 0.8 3.6 V 5.5 V 0.8 2.3 V 3V 0.8 2.7 V 3V 0.8 3V 3.6 V 0.8 3.6 V 5.5 V VILB Low level input voltage Low-level VIA VIB Input voltage 0 Input voltage 0 VOA VOB Output voltage 0 Output voltage 0 IOHA High-level output current IOHB IOLA High-level output current Low-level output current IOLB Low-level output current ∆t/∆v Input transition rise or fall rate UNIT V V V V 1.65 VCCA VCCB V VCCA VCCB V 2.3 V 3V –8 2.7 V 3V –12 3.3 V 3V –24 2.3 V 3.3 V –12 2.7 V 3.3 V –12 3.3 V 3V –24 2.3 V 3V 8 2.7 V 3V 12 3.3 V 3V 24 2.3 V 3.3 V 12 2.7 V 3.3 V 12 3.3 V 3V V V mA mA mA mA 24 0 10 ns/V TA Operating free-air temperature –40 85 °C NOTE 4: All unused inputs of the device must be held at the associated VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74LVCC3245A OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS SCAS585F – NOVEMBER 1996 – REVISED AUGUST 1998 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 µA IOH = –8 mA IOH = –12 12 mA VOHA IOH = –24 24 mA IOH = –12 12 mA IOH = –24 24 mA VOLA 3 2.3 V 3V 2 2.7 V 3V 2.2 2.5 3V 3V 2.4 2.8 3V 3V 2.2 2.6 2.7 V 4.5 V 2 2.3 3 3V 3V 2.9 2.3 V 3V 2.4 2.7 V 3V 2.4 2.8 3V 3V 2.2 2.6 2.7 V 4.5 V 3.2 4.2 MAX V 3V 3V 2.3 V 3V IOL = 12 mA 2.7 V 3V 0.1 0.5 3V 3V 0.2 0.5 2.7 V 4.5 V 0.2 0.5 3V 3V 2.3 V 3V IOL = 100 µA IOL = 12 mA IOL = 24 mA 3V 0.1 0.6 0.4 3V 0.2 0.5 4.5 V 0.2 0.5 3.6 V ±0.1 ±1 5.5 V ±0.1 ±1 Control inputs VI = VCCA or GND IOZ† A or B ports VO = VCCA/B or GND, A port = VCCA or GND, VI = VIL or VIH IO = 0 3.6 V 3.6 V ±0.5 ±5 3.6 V Open 5 50 B port = VCCB or GND GND, IO = 0 36V 3.6 3.6 V 5 50 5.5 V 5 50 3.6 V 5 50 5.5 V 8 80 ICCB B to A µA µA µA µA A port = VCCA or GND GND, A port VI = VCCA – 0.6 V, Other inputs at VCCA or GND, OE at GND and DIR at VCCA 3.6 V 3.6 V 0.35 0.5 OE VI = VCCA – 0.6 V, Other inputs at VCCA or GND, DIR at VCCA 3.6 V 3.6 V 0.35 0.5 DIR VI = VCCA – 0.6 V, Other inputs at VCCA or GND, OE at GND 3.6 V 3.6 V 0.35 0.5 ∆ICCB‡ B port VI = VCCB – 2.1 V, Other inputs at VCCB or GND, OE at GND and DIR at GND 3.6 V 5.5 V 1 1.5 Ci Control inputs Open 4 pF A or B ports VI = VCCA or GND VO = VCCA/B or GND Open Cio 3.3 V 5V 18.5 pF A to B Outputs enabled 3.3 V 5V 38 B to A Outputs enabled 3.3 V 5V 36.5 Cpd d 36V 3.6 V A to B ∆ICCA‡ IO = 0 V 0.1 II ICCA 36V 3.6 UNIT V IOL = 100 µA IOL = 8 mA IOL = 24 mA VOLB TYP 2.9 VCCB 3V IOH = –100 µA VOHB MIN VCCA 3V mA mA pF † For I/O ports, the parameter IOZ includes the input leakage current. ‡ This is the increase in supply current for each input that is at one of the specified voltage levels rather than 0 V or the associated VCC. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74LVCC3245A OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS SCAS585F – NOVEMBER 1996 – REVISED AUGUST 1998 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 4) FROM (INPUT) TO (OUTPUT) tPHL tPLH A B tPHL tPLH B A tPZL tPZH OE A tPZL tPZH OE B tPLZ tPHZ OE A tPLZ tPHZ OE B PARAMETER VCCA = 2.5 V ± 0.2 V, VCCB = 3.3 V ± 0.3 V VCCA = 2.7 V TO 3.6 V, VCCB = 5 V ± 0.5 V MIN MAX MIN 1 9.4 1 9.1 1 1 VCCA = 2.7 V TO 3.6 V, VCCB = 3.3 V ± 0.3 V MAX MIN MAX 1 6 1 7.1 1 5.3 1 7.2 11.2 1 5.8 1 6.4 9.9 1 7 1 7.6 1 14.5 1 9.2 1 9.7 1 12.9 1 9.5 1 9.5 1 13 1 8.1 1 9.2 1 12.8 1 8.4 1 9.9 1 7.1 1 5.5 1 6.6 1 6.9 1 7.8 1 6.9 1 8.8 1 7.3 1 7.5 1 8.9 1 7 1 7.9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ns ns ns ns ns ns 5 SN74LVCC3245A OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS SCAS585F – NOVEMBER 1996 – REVISED AUGUST 1998 PARAMETER MEASUREMENT INFORMATION FOR A PORT VCCA = 2.5 V ± 0.2 V AND VCCB = 3.3 V ± 0.3 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 30 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74LVCC3245A OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS SCAS585F – NOVEMBER 1996 – REVISED AUGUST 1998 PARAMETER MEASUREMENT INFORMATION FOR B PORT VCCA = 2.5 V ± 0.2 V AND VCCB = 3.3 V ± 0.3 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN74LVCC3245A OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS SCAS585F – NOVEMBER 1996 – REVISED AUGUST 1998 PARAMETER MEASUREMENT INFORMATION FOR B PORT VCCA = 3.6 V AND VCCB = 5.5 V 2 × VCC 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC Open LOAD CIRCUIT tw VCC B-Port Input 50% VCC 50% VCC 0V VOLTAGE WAVEFORMS PULSE DURATION 1.5 V 1.5 V 0V tPHL tPLH B-Port Output VOH 50% VCC 1.5 V 1.5 V 0V tPZL VCC Input 2.7 V Output Control 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NONINVERTING OUTPUTS tPLZ Output Waveform 1 S1 at 2 × VCC (see Note B) Output Waveform 2 S1 at Open (see Note B) 50% VCC tPZH 50% VCC VCC VOL + 0.3 V VOL tPHZ VOH – 0.3 V VOH [0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 3. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74LVCC3245A OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS SCAS585F – NOVEMBER 1996 – REVISED AUGUST 1998 PARAMETER MEASUREMENT INFORMATION FOR A AND B PORT VCCA AND VCCB = 3.6 V 7V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open LOAD CIRCUIT tw 2.7 V 1.5 V Input 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION 1.5 V 1.5 V 0V tPHL tPLH VOH Output 1.5 V 1.5 V 0V tPZL 2.7 V Input 2.7 V Output Control 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NONINVERTING OUTPUTS tPLZ Output Waveform 1 S1 at 7 V (see Note B) Output Waveform 2 S1 at Open (see Note B) 1.5 V tPZH 3.5 V VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH [0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 4. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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