TDA9210 150 MHz PIXEL VIDEO CONTROLLER FOR MONITORS PRELIMINARY DATA FEATURE ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 150 MHZ PIXEL RATE 2.7 ns RISE AND FALL TIME I2C BUS CONTROLLED GREY SCALE TRACKING VERSUS BRIGHTNESS OSD MIXING NEGATIVE FEED-BACK FOR DC COUPLING APPLICATION BEAM CURRENT ATTENUATION (ABL) PEDESTRAL CLAMPING ON OUTPUT STAGE POSSIBILITY OF LIGHT OR DARK GREY OSD BACKGROUND OSD INDEPENDENT CONTRAST CONTROL ADJUSTABLE BANDWIDTH INPUT BLACK LEVEL CLAMPING WITH BUILT-IN CLAMPING PULSE STAND-BY MODE 5 V TO 8 V POWER SUPPLY SYNC CLIPPING FUNCTION (SOG) DESCRIPTION The TDA9210 is an I2C Bus controlled RGB preamplifier designed for Monitor applications, able to mix the RGB signals coming from any OSD device. The usual Contrast, Brightness, Drive and Cut-Off Controls are provided. In addition, it includes the following features: – OSD contrast, – Bandwidth adjustment, – Grey background, – Internal back porch clamping pulse generator. DIP20 (Plastic Package) ORDER CODE: TDA9210 The RGB incoming signals are amplified and shaped to drive any commonly used video amplifiers without intermediate follower stages. Even though encapsulated in a 24-pin package only, this IC allows any kind of CRT Cathode coupling : – AC coupling with DC restore, – DC coupling with Feed-back from Cathodes, – DC coupling with Cut-Off controls of the Video amplifier (ST Amplifiers TDA9533/9530). As for any ST Video pre-amplifier, the TDA9210 is able to drive a real load without any external interface. One of the main advantages of ST devices is their ability to sink and source currents while most of the devices from our competitors have problems to sink large currents. These driving capabilities combined with an original output stage structure suppress any static current on the output pins and therefore reduce dramatically the power dissipation of the device. Extensive integration combined with high performance and advanced features make the TDA9210 one of the best choice for any CRT Monitor in the 14” to 17” range. Perfectly matched with the ST Video Amplifiers TDA9535/36, these 2 products offer a complete solution for high performance and cost-optimized Video Board Application. Version 3.1 March 2000 1/19 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1 TDA9210 1 - PIN CONNECTIONS IN1 ABL IN2 1 2 3 GNDL 4 IN3 5 GNDA OSD1 OSD2 6 7 8 9 12 OUT3 SDA SCL OSD3 10 11 FBLK VCCA 20 19 18 17 16 15 14 13 BLK HSYNC or BPCP OUT1 VCCP OUT2 GNDP 2 - PIN DESCRIPTION Pin Number 1 2 Symbol IN1 ABL 3 4 IN2 GNDL Green Video Input Logic Ground 5 6 IN3 GNDA Blue Video Input Analog Ground 7 8 9 VCCA OSD1 OSD2 Analog VCC (5V) Red OSD Input Green OSD Input 10 11 12 OSD3 FBLK SCL Blue OSD Input Fast Blanking SCL 2/19 13 SDA 14 15 16 OUT3 GNDP OUT2 17 18 19 VCCP OUT1 HSYNC/BPCP 20 BLK Description Red Video Input ABL Input SDA Blue Video Output Power Ground Green Video Output Power VCC (5 V to 8 V) Red Video Output HSYNC/BPCP Blanking Input TDA9210 3 - BLOCK DIAGRAM TDA9210 BLK FBLK 20 11 VCCP 17 Output Clamp Pulse (OCL) Drive Contrast VREF 18 OUT1 Output Stage IN1 1 Clamp IN2 3 Green Channel IN3 5 Blue Channel 14 OUT3 Contrast/8bit ABL 2 Brightness Drive 8bits 3x8bits BPCP GNDL 16 OUT2 15 GNDP Latches I2C Bus Decoder 4 Cut-off 8bits GNDA 6 D/A IC Output DC Level 4bits OSD Cont. 4bits VCCA 7 VREF 19 HSYNC or BPCP 13 12 SDA SCL 8 OSD1 9 OSD2 10 OSD3 See Figure 8 for complete BPCP and OCL generation diagram 4 - FUNCTIONAL DESCRIPTION 4.1 - RGB Input The three RGB inputs have to be supplied through coupling capacitors (100 nF). The maximum input peak-to-peak video amplitude is 1 V. The input stage includes a clamping function. The clamp uses the input serial capacitor as a ”memory capacitor”. To avoid a discharge of the serial capacitor during the line (due to leakage current), the input voltage is referenced to the ground. The clamp is gated by an internally generated ”Back Porch Clamping Pulse” (BPCP). Register 8 allows to choose the way to generate this BPCP (see Figure 1). When bit 0 is set to 0, the BPCP is synchronized on the trailing or leading edge of HSYNC (Pin 19) (bit 1 = 0: trailing edge, bit 1 = 1: leading edge). 3/19 TDA9210 Additionally, the IC automatically works with either positive or negative HSYNC pulses. – When bit 0 is set to 1, BPCP is synchronized on the leading edge of the blanking pulse BLK (Pin 20). One can use a positive or negative blanking pulse by programming bit 0 in Register 9 (See I 2C Table 3). – BPCP width can be adjusted with bit 2 and 3 (see Register 8, I2C table 2). – If the application already provides the Back Porch Clamping Pulse, bit 4 must be set to 1 (providing a direct connection between Pin 19 and internal BPCP). put) the synchro clipping function must be activated (bit 7 set to 1 in register 9) in order to keep the right green output levels and avoid unbalanced colours. 4.2 - Synchro Clipping Function The contrast adjustment is made by controlling simultaneously the gain of the three internal amplifiers through the I2C bus interface. Register 1 allows the adjustment in a range of 48 dB. This function is available on channel 2 (Green Channel). When using the Sync On Green (SOG) (Synchro pulse included in the green channel in- 4.3 - Blanking Input The Blanking pin (FBLK) is TTL compatible. The Blanking pulse can be: – positive or negative – line or Composite-type (but not Frame-type). 4.4 - Contrast Adjustment (8 bits) Figure 1. R8b0=0 and R8b1=0 HSYNC/BPCP (Pin19) Internal BPCP R8b0=0 and R8b1=1 HSYNC/BPCP (Pin19) Internal BPCP R8b0=1 BLK (Pin20) Internal BPCP R8b4 =1 HSYNC/BPCP (Pin19) Internal BPCP 4.5 - ABL Control The TDA9210 includes an ABL (automatic beam limitation) input to attenuate the RGB Video signals depending on the beam intensity. 4/19 The operating range is 2 V (from 3 V to 1 V). A typical 15 dB maximum attenuation is applied to the output signal whatever the contrast adjustment is. (See Figure 2 ). When the ABL feature is not used, the ABL input (Pin 2) must be connected to a 5 V supply voltage. TDA9210 Figure 2. Attenuation (dB) 0 -2 -4 -6 -8 -10 -12 -14 -16 0 VABL (V) 1 2 3 4 5 4.6 - Brightness Adjustment (8 bits) Brightness adjustment is controlled by the I2C Bus via Register 2. It consists of adding the same DC voltage to the three RGB signals, after contrast adjustment. When the blanking pulse equals 0, the DC voltage is set to a value which can be adjusted between 0 and 2V with 8mV steps (see Figure 3). The DC output level is forced to the ”Infra Black” level (VDC) when the blanking pulse is equal to 1. 4.7 - Drive Adjustment (3 x 8 bits) In order to adjust the white balance, the TDA9210 offers the possibility of adjusting separately the overall gain of each channel thanks to the I2C bus (Registers 3, 4 and 5). The very large drive adjustment range (48 dB) allows different standards or custom color temperatures. It can also be used to adjust the output voltages at the optimum amplitude to drive the CRT drivers, keeping the whole contrast control for the enduser only. The drive adjustment is located after the Contrast, Brightness and OSD switch blocks, so it does not affect the white balance setting when the BRT is adjusted. It also operates on the OSD portion of the signal. 4.8 - OSD Inputs The TDA9210 allows to mix the OSD signals into the RGB main picture. The four pins dedicated to this function are the following: – Three TTL RGB inputs (Pins 8, 9, 10) connected to the three outputs of the corresponding OSD processor. – One TTL fast blanking input (Pin 11) also connected to the FBLK output of the OSD processor. When a high level is present on the FBLK, the IC acts as follows: – The three main picture RGB input signals (IN1, IN2, IN3) are internally switched to the internal input clamp reference voltage. – The three output signals are set to the voltage corresponding to the three OSD input logic states (0 or 1). (See Figure 3). If the OSD input is at low level, the output and brightness voltages (VBRT) are equal. If the OSD input is at high level, the output voltage is VOSD, where V OSD = VBRT + OSD and OSD is an I2C bus-controlled voltage. OSD varies between 0 V to 4.9 V by 320 mV steps via Register 7 (4 bits). The same variation is applied simultaneously to the three channels providing the OSD contrast. The grey color can be obtained on output signals when: – OSD1 = 1, OSD2 = 0 and OSD3 = 1, – A special bit (bit 5 or 6) in Register 9 is set to 1. If R9b5 is set to 1, light grey is obtained on output. If R9b6 is set to 1, dark grey is obtained on output. In the case where R9b5 and R9b6 are set to 0, the normal operation is provided on output signals. 4.9 - Output Stage The overall waveforms of the output signal are shown in Figure 3 and Figure 4. The three output stages, which are large bandwidth output amplifiers, are able to deliver up to 4.4 VPP for 0.7 V PP on input. When a high level is applied on the BLK input (Pin 20), the three outputs are forced to ”Infra Black” level (VDC) thanks to a sample and hold circuit (described below). The black level (which is the output voltage outside the blanking pulse with minimum brightness and no Video input signals) is 400 mV higher than VDC. The brightness level (VBRT) is then obtained by programming register 2 (see I2C table 1). The sample and hold circuit is used to control the ”Infra Black” level in the range of 0.5 V to 2.5 V via Register 6 (in case of AC coupling) or Registers 10, 11, 12 (in case of DC coupling) . This sampling occurs during an internal pulse (OCL) generated inside the blanking pulse window. Refer to “CRT cathode coupling” part for further details. 5/19 TDA9210 Functioning with 5 V Power VCC To simplify the application, it is possible to supply the power VCC with 5 V (instead of 8 V nominal) at the expense of output swing voltage. Functioning without Blanking Pulse If no blanking pulse is applied to the TDA9210, the internal BPCP can be connected to the sample and hold circuit (Register 8, bit 7 = 1 and BLK pin grounded) so that the output DC level is still controlled by I2C. To ensure the device correct behavior in the worst possible conditions, the Brightness Register must be set to 0. Figure 3. Waveforms VOUT, BRT, CONT, OSD HSYNC BPCP BLK Video IN FBLK OSD IN (4) CONT (5) V OSD (3) VBRT (2) V BLACK VDC (1) VOUT1 , VOUT2 , VOUT3 V 6/19 OSD CONT BRT 0.4V fixed Notes : 1. VDC = 0.5 to 2.5V 2. VBLACK = V DC + 0.4V 3. VBRT = V BLACK + BRT (with BRT = 0 to 2V) 4. VCONT = V BRT + CONT = k x Video IN (CONT = 4.4VPP max. for VIN = 0.7V PP) 5. VOSD = V BRT + OSD (OSD max. = 4.9VPP , OSD min = 0VPP) TDA9210 Figure 4. Waveforms (Drive adjustment) HSYNC BPCP BLK Video IN BFLK OSD IN VOUT1, VOUT2, VOUT3 VCONT V OSD VBRT VBLACK VDC Two examples of drive adjustment (1) Note : 1.Drive adjustment modifies the following voltages : VCONT, VBRT and V OSD. Drive adjustment doesn’t modify the following voltages : VDC and VBLACK. 4.10 - Bandwidth Adjustment A new feature: Bandwidth adjustment, has been implemented on the TDA9210. This function has several advantages: – Depending on the external capacitive load and on the peak-to-peak output voltage, the bandwidth can be adjusted to avoid any slew-rate phenomenon. – The preamp bandwidth can be adjusted in order to reduce electromagnetic radiation, since it is possible to slow down the signal rise/fall time at the CRT driver input without too much affecting the rise/fall time at the CRT driver output. – It is possible to optimize the ratio of the frequency response versus the CRT driver power consumption for any kind of chassis, as the preamp bandwidth adjustment also allows the adjustment of the rise/fall time on the cathode (through the CRT driver). – In still picture mode, when a high Video swing voltage is of greater interest than rise/fall time, bandwidth adjustment is used to avoid any slewrate phenomenon at the CRT driver output and to meet electromagnetic radiation requirements. 4.11 - CRT Cathode Coupling (Figure 5) The TDA9210 is designed to be used in DC coupling mode, enabling to build a powerful video system on a small PCB Board and giving a substantial cost saving compared with any other solution available on the market. The preamplifier outputs control directly the cut-off levels. The output DC level (VDC) is adjusted independently for each channel from 0.5 V to 2.5 V via registers 10, 11 and 12. In DC coupling mode, bit 2 must be set to 1 and bit3 to 0 in Register 9. 7/19 TDA9210 Figure 5. DC Coupling TDA 9210 Pins 14-16-18 CRT Driver CRT OUTPUT 1,2,3 DC LEVEL 0.5V to 2.5V (8bits) In order to write data into the TDA9210, after the “start” message, the MCU must send the following data (see Figure 6): – the I2C address slave byte with a low level for the R/W bit, – the byte to the internal register address where the MCU wants to write data, – the data. All bytes are sent with MSB bit first. The transfer of written data is ended with a “stop” message. When transmitting several data, the register addresses and data can be written with no need to repeat the start and slave addresses. 4.12 - Stand-by Mode The TDA9210 has a stand-by mode. As soon as the VCC power (Pin 17) gets lower than 3V (typ.), the device is set in stand-by mode whatever the voltage on analog VCCA (Pin 7) is. The analog blocks are internally switched-off while the logic parts (I2C bus, power-on reset) are still supplied. In stand-by mode, the power consumption is below 20 mW. 4.13 - Serial Interface The 2-wire serial interface is an I2C interface. The slave address of TDA9210 is DC hex. A6 A5 A4 A3 A2 A1 A0 W 1 1 0 1 1 1 0 0 4.14 - Power-on Reset A power-on reset function is implemented on the TDA9210 so that the I2C registers have a determined status after power-on. The Power-on reset threshold for a rising supply on VCCA (Pin 7) is 3.8 V (typ.) and 3.2V when the VCC decreases. The host MCU can write into the TDA9210 registers. Read mode is not available. Figure 6. I2C Write Operation SCL W SDA Start 8/19 I2C Slave Address A7 ACK A6 A5 A4 A3 A2 Register Address A1 D7 A0 ACK D6 D5 D4 D3 Data Byte D2 D1 D0 ACK Stop TDA9210 5 - ABSOLUTE MAXIMUM RATINGS Symbol VCCA Max. VCCP Max. Parameter Supply Voltage on Analog VCC Supply Voltage on Power VCC Vin Max. Voltage at any Input Pins (except Video inputs) and Input/Output Pins VI Max. Voltage at Video Inputs Tstg Storage Temperature Toper Operating Junction Temperature Pin Value 7 20 5.5 8.8 Units V V - 5.5 V 1, 3, 5 1.4 V - - °C - +150 °C 6 - THERMAL DATA Symbol Value Units R th(j-a) Max. Junction-ambient Thermal Resistance Parameter 69 °C/W Tj Typ. Junction Temperature at Tamb = 25°C 80 °C 7 - DC ELECTRICAL CHARACTERISTICS T amb = 25°C, VCCA = 5V, VCCP = 8V, unless otherwise specified. Symbol Parameter Min. Typ. Max. Units Pin 7 4.5 5 5.5 V Power Supply Voltage Pin 17 4.5 8 8.8 Analog Supply Current VCCA = 5V Power Supply Current VCCP = 8V VCCA Analog Supply Voltage VCCP ICCA ICCP VI Test Conditions 70 55 Video Input Voltage Amplitude 0.7 Vo Output Voltage Range 0.5 VI L VI H Low Level Input Voltage High Level Input Voltage OSD, FBLK, BLK, HSYNC IIN Input Current OSD, FBLK, BLK RHS Input Resistor HSYNC mA 1 V V CCP -0.5V V 0.8 2.4 -1 1 40 V mA V V µA kΩ 9/19 TDA9210 8 - AC ELECTRICAL CHARACTERISTICS Tamb = 25°C, VCCA = 5V, VCCP= 8V, V i = 0.7 VPP, CLOAD = 5pF RS = 100Ω, serial between output pin and CLOAD, unless otherwise specified. Symbol Parameter Test Condit ions Min. Typ. Max. Units VIDEO INPUTS (PINS 1, 3, 5) VI Video Input Voltage Amplitude Max. Contrast and Drive 0.7 1 V VIDEO OUTPUT SIGNAL (PINS 14, 16, 18) - GENERAL GAM Maximum Gain Max Contrast and Drive (CRT = DRV = 254 dec) 16 dB VOM Maximum Video Output Voltage (Note 1) Max Contrast and Drive (CRT = DRV = 254 dec) 4.4 V Nominal Video Output Voltage Contrast and Drive at POR (CRT = DRV = 180 dec) 2.2 V Contrast Attenuation Range From max. Contrast (CRT=254 dec) 48 dB 48 dB ± 0.1 dB VON CAR to min. Contrast (CRT = 1 dec) DAR Drive Attenuation Range From Max. Drive (DRV = 254 dec) to min Drive (DRV = 1 dec) GM Gain Matching Contrast and Drive at POR tR, tF Rise Time, Fall Time (Note 2) BW Large Signal Bandwidth BW Bandwidth Adjustment Range CT Crosstalk between Video Outputs VOUT = 2 VPP (BW = 15 dec) VOUT = 2 VPP (BW = 0 dec) VOUT = 2 V PP 2.7 4.3 ns ns 130 MHz VOUT = 2 V PP Minimum bandwidth (BW = 0 dec) Maximum bandwidth (BW =15 dec) 80 130 MHz MHz 60 35 dB dB VOUT = 2 V PP @ f = 10 MHz @ f = 50 MHz VIDEO OUTPUT SIGNAL — BRIGHTNESS BRTmax Maximum Brightness Level Max. Brightness (BRT = 255 dec) and Max. Drive (DRV = 254 dec) 2 V BRTmin Minimum Brightness Level Min. Brightness (BRT = 0 dec) and Max. Drive (DRV = 254 dec) 0 V VIP Insertion Pulse 0.4 V BRTM Brightness Matching Brightness and Drive at POR ± 10 mV Max. Drive (DRV = 254 dec) Max. OSD (OSD = 15 dec) Min. OSD (OSD = 0 dec) 4.9 0 V V 2.5 0.4 V V 10 mV 0.5 % VIDEO OUTPUT SIGNAL — OSD OSDmax OSDmin Maximum OSD Output Level Minimum OSD Output Level VIDEO OUTPUT SIGNAL — DC LEVEL (DC COUPLING MODE) DCLmax DCLmin Maximum Output DC Level Minimum Output DC Level DCLstep Output DC Level Step DCLTD Output DC Level Drift Max. Cut-off (Cut-off = 255 dec) Min. Cut-off (Cut-off = 40 dec) Tj variation=100°C Note 1 : Assuming that VOM remains within the range of Vo (between 0.5V and VCCP - 0.5V) Note 2 : tR, tF are calculated values, assuming an ideal input rise/fall time of 0ns (tR = tROUT2 + tRIN2 , tF = tFOUT2 + tFIN2 10/19 TDA9210 AC ELECTRICAL CHARACTERISTICS Tamb = 25°C, VCCA = 5V, VCCP= 8V, Vi = 0.7 VPP, C LOAD = 5 pF, unless otherwise specified Symbol Parameter Test Condit ions Min. Typ. Max. Units ABL (PIN 2) VABL ≥ 3.2 V GABLmin GABLmax ABL Mini Attenuation ABL Maxi Attenuation VABL ABL Threshold Voltage For output attenuation 3 V IABLhigh IABLlow High ABL Input Current Low ABL Input Current VABL = 3.2V VABL = 1V 0 -2 µA µA Typ. Max. Units 0 15 VABL = 1 V dB dB 9 - I2C ELECTRICAL CHARACTERISTICS T amb = 25°C, VCCA = 5V, unless otherwise specified Symbol Parameter Test Conditi ons VIL Low Level Input Voltage VIH High Level Input Voltage Min. On Pins SDA, SCL 1.5 3 0.4 V < VIN < 4.5 V IIN Input Current (Pins SDA, SCL) fSCL(Max.) SCL Maximum Clock Frequency VOL Low Level Output Voltage V V -10 +10 µA 200 0.25 kHz 0.6 V SDA Pin when ACK Sink Current = 6mA 10 - I 2C INTERFACE TIMING REQUIREMENTS (see Figure 11) Symbol Parameter Min. Typ. Max. Units tBUF Time the bus must be free between two accesses 1300 ns tHDS Hold Time for Start Condition 600 ns tSUP Set-up Time for Stop Condition 600 ns tLOW The Low Period of Clock 1300 ns tHIGH The High Period of Clock 600 ns tHDAT Hold Time Data 300 ns tSUDAT Set-up Time Data 250 tR, tF Rise and Fall Time of both SDA and SCL 20 ns 300 ns Figure 7. I2C Timing Diagram t t BUF HDAT SDA t t HDS SUDAT t SUP SCL t HIGH t LOW 11/19 TDA9210 11 - I 2C REGISTER DESCRIPTION Register Sub-addressed - I2C Table 1 Sub-address Max. Value POR Value Register Names Hex Dec 01 01 Contrast (CRT) 02 02 Brightness (BRT) 8-bit DAC B4 180 FF 255 03 03 Drive 1 (DRV) 8-bit DAC B4 180 FE 254 04 04 Drive 2 (DRV) 8-bit DAC B4 180 FE 254 05 05 Drive 3 (DRV) 8-bit DAC B4 180 FE 254 06 06 Not Used - - - - 07 07 OSD Contrast (OSD) 4-bit DAC 09 09 0F 15 08 08 BPCP & OCL Refer to the I2C table 2 04 04 09 09 Miscellaneous Refer to the I2C table 3 1C 28 0A 10 Cut Off Out 1 DC Level (Cut-off) 8-bit DAC B4 180 FF 255 8-bit DAC Hex Dec Hex Dec B4 180 FE 254 0B 11 Cut Off Out 2 DC Level (Cut-off) 8-bit DAC B4 180 FF 255 0C 12 Cut Off Out 3 DC Level (Cut-off) 8-bit DAC B4 180 FF 255 0D 13 Bandwidth Adjustment (BW) 4-bit DAC 07 07 0F 15 For Contrast & Drive adjustment, code 00 (dec) and 255 (dec) are not allowed. For Output DC Level, code 00(dec), 01(dec), 02(dec) are not allowed (Register 06). For Cut Off Output DC Level, output voltage is linear between code 10 and code 235 (Registers 0A, 0B, 0C). BPCP & OCL Register (R8) - I2C Table 2 (see also Figure 8) b7 b6 b5 b4 b3 b2 b1 b0 Function 0 0 Internal BPCP triggered by HSYNC 0 1 Internal BPCP triggered by BLK 0 0 Internal BPCP synchronized by the trailing edge 0 1 Internal BPCP synchronized by the leading edge 0 0 0 Internal BPCP Width = 0.33 µs 0 0 1 Internal BPCP Width = 0.66 µs 0 1 0 Internal BPCP Width = 1 µs 0 1 1 Internal BPCP Width = 1.33 µs 1 x x x Internal BPCP = BPCP input (Pin 23) 0 Normal Operation 1 Reserved (Force BPCP to 1 in test) 0 Normal Operation 1 Reserved (Force OCL to 1 in test) 0 Internal OCL pulse triggered by BLK (pin 24) 1 Internal OCL pulse = Internal BPCP 12/19 POR Value x x x TDA9210 Miscellaneous Register (R9) - I2C Table 3 b7 b6 b5 b4 x b3 0 b2 b1 b0 Function 0 Positive Blanking Polarity 1 Negative Blanking Polarity 0 Soft Blanking = OFF 1 Soft Blanking = ON 1 POR Value x x DC Coupling Mode (Note 3) 0 0 Light Grey on OSD Outputs = OFF 0 1 Light Grey on OSD Outputs = ON 0 0 Dark Grey on OSD Outputs = OFF 1 0 Dark Grey on OSD Outputs = ON 0 SOG Clipping = OFF 1 SOG Clipping = ON x x x Note 3 : After Power ON, the DC coupling mode must be programmed in Register 9 by setting bit2=1 and bit3=0. Bandwidth Adjustment (R13) - I2C Table 4 b7 b6 b5 b4 b3 b2 b1 b0 Function 1 1 1 1 130 MHz 0 1 1 1 100 MHz 0 0 0 0 80 MHz POR Value x 0 0 Normal Operation 0 1 BW DAC output connected to BLK input (for test) x 1 0 BW DAC complementary output connected to BLK input (for test) Figure 8. BPCP and OCL Generation Source Selection R8b0 HS/BPCP (External) 23 Automatic Polarity HS edge Selection R8b1 24 BPCP Source Selection R8b4 BPCP (Internal) Edge Selection BLK (External) Width Selection R8b2b3 Pulse Generation OCL (Internal) Polarity Pulse Selection Generation BLK Polarity Selection R9b0 OCL Source Selection R8b7 13/19 TDA9210 12 - INTERNAL SCHEMATICS Figure 9. Figure 12. VCC5 VCCA 7 30k (8V) LOGIC PART HIGH IMPEDANCE IN (Pins 1-3-5) GNDA 6 GNDA Figure 10. Figure 13. VCCA V CCA OSD-FBLK-HS-BLK Pins 8-9-10 11-19-20 1k ABL 2 GNDA GNDL GNDA Figure 11. Figure 14. VCCA HSYNC 19 GNDL 4 GNDA 14/19 2 GNDA GNDL TDA9210 Figure 15. 30kΩ SCL 12 4pF GNDA (8V) GNDL 30kΩ SCA 13 4pF GNDL GNDA Figure 16. VCCP GNDP 15 GNDA Figure 17. VCCP 17 OUT Pins 14-16-18 (20V) GNDA GNDP 15/19 TDA9210 Figure 18. TDA9210 - TDA9535/9536 Demonstration Board: Silk Screen and Trace (scale 1:1) 16/19 1 2 3 4 1 2 3 4 5 6 Supply J17 12 11 10 9 8 7 6 5 4 3 2 1 1 2 3 4 5 Power J16 Video J1 110V A 5V 8V 12V BLU RED R10 75R R3 75R R5 75R 47uF C15 47uF C16 47uF C17 VsOut R18 100R GRN Hs Out A R20 100R 5V D5 1N4148 D6 Hs Out Vs Out G1 Heater 1N4148 D8 1N4148 C3 100nF 100nF 15R 5 4 3 15 16 FBLK 11 SCL 12 SCA 13 OUT3 14 GNDP OUT2 VCCP 17 OUT1 18 HS 19 BLK 20 TDA9210 OSD3 OSD2 OSD1 VCCA GNDA IN3 GNDL IN2 ABL IN1 U1 100pF C12 C13 100pF R21 2K7 R19 2K7 5V C5(1)100nF 5V 1 2 3 4 R17 R13 R9 I2C J10 R11 2R7 100pF C1(1) C B C 8V 15R/33R 15R/33R 15R/33R 2: The purpose of all components followed by (2) is to ensure a good protectionagainst overvoltage(arcing protection) 1: All capacitorsfollowed by (1) are decoupling capacitors which must be connected as close as possible to the device 10 9 8 7 C22(1) 100nF 6 R12 C9(1) 100nF R8 15R 2 1 100R R2 15R 2R7 R4 Notes: R16 2R7 5V C6 1N4148 C4 100nF D4 5V 5V 1N4148 D3 1N4148 D1 5V B R1 24R R24 24R R33 24R R29 47pF C25 47pF C24 47pF C23 8 4 D C21 100nF/ 250V 10R R28 G1 D2(2) 110V 6 G2 R H2 4.7nF/1kV C20 150R 5 G 10 H1 7 G2 150R 10nF/ 2KV C19 J8 10nF/ 400V 9 C14 Heater R23 FDH400 D9(2) 110V 8 150R FDH400 R15 150R D7(2) 110V R7 E F1(2) F2(2) February16,2000 Date: Wednesday, E Sheet 1 of CRT3 with TDA9210 + TDA9535/36 R27 G1 11 0.33uH S_R L3 Size DocumentNumber CustomVersion1.4 Title 1 GND J5 12 GND B R22 120R 110V 0.33uH S_R L2 R31 0.33uH L1 4.7uF/ 150V R32 C18 R26(2) 39R R14 47uF 120R 120R C8 100nF/ 250V C10(1) 100nF R6 R30 FDH400 transientresponse optimisation S_R 12V C7(1) GND_CRT J7 OUT1 1 GND1 2 VDD OUT2 5 GND2 6 VCC TDA9535/36 IN1 IN2 IN3 110V 3 7 9 11 GND3 10 OUT3 U2 D 1 F4(2) Rev 1 2 3 4 TDA9210 Figure 19. TDA9210 - TDA9535/9536 Demonstration Board Schematic 17/19 TDA9210 13 - PACKAGE MECHANICAL DATA 20 Pins — Plastic Dip Dimensions Millimeters Min. a1 0.254 B 1.39 Typ. 1.65 0.45 b1 0.25 D Min. Typ. 0.055 Max. 0.065 0.018 0.010 25.4 1.000 8.5 0.335 e 2.54 0.100 e3 22.86 0.900 F 7.1 0.280 I 3.93 0.155 L Z 18/19 Max. 0.010 b E Inches 3.3 0.130 1.34 0.053 TDA9210 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this public ation are subject to change witho ut notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics. 2000 STMicroelectronics - All Rights Reserved Purchase of I2C Components of STMicroelectronics, conveys a license under the Philip s I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philip s. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www .st.com 19/19 3