2N7007 N-Channel Enhancement-Mode Vertical DMOS FET Ordering Information BVDSS / BVDGS RDS(ON) (max) ID(ON) (min) 240V 45Ω 150mA Order Number / Package TO-92 2N7007 Features Advanced DMOS Technology ■ Free from secondary breakdown These enhancement-mode (normally-off) transistors utilize a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, these devices are free from thermal runaway and thermally-induced secondary breakdown. ■ Low power drive requirement ■ Ease of paralleling ■ Low CISS and fast switching speeds ■ Excellent thermal stability ■ Integral Source-Drain diode Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. ■ High input impedance and high gain ■ Complementary N- and P-channel devices Applications ■ Motor controls Package Options ■ Converters ■ Amplifiers ■ Switches ■ Power supply circuits ■ Drivers (relays, hammers, solenoids, lamps, memories, displays, bipolar transistors, etc.) Absolute Maximum Ratings Drain-to-Source Voltage BVDSS SGD Drain-to-Gate Voltage BVDGS TO-92 Gate-to-Source Voltage Operating and Storage Temperature Soldering Temperature* ±30V -55°C to +150°C 300°C * Distance of 1.6 mm from case for 10 seconds. Note 1: See Package Outline section for dimensions. 7-13 2N7007 Thermal Characteristics Package ID (continuous)* ID (pulsed) Power Dissipation @ TC = 25°C θjc °C/W θja °C/W IDR* IDRM 65mA 260mA 1W 125 170 65mA 260mA TO-92 * ID (continuous) is limited by max rated Tj. Electrical Characteristics (@ 25°C unless otherwise specified) Symbol Parameter Min BVDSS Drain-to-Source Breakdown Voltage 240 VGS(th) Gate Threshold Voltage 1 IGSS IDSS Max Unit Conditions V ID = 100µA, VGS = 0V 2.5 V VGS = VDS, ID = 250µA Gate Body Leakage 10 nA VGS = ±20V, VDS = 0V Zero Gate Voltage Drain Current 100 nA VGS = 0V, VDS = 120V 1 µA VGS = 0V, VDS = 120V TA = 125°C ON-State Drain Current 50 mA 150 Static Drain-to-Source ON-State Resistance RDS(ON) 45 Ω 45 GFS Forward Transconductance 30 m CISS Input Capacitance 30 COSS Common Source Output Capacitance 15 CRSS Reverse Transfer Capacitance 10 t(ON) Turn-ON Time 30 t(OFF) Turn-OFF Time 20 VSD Diode Forward Voltage Drop 1.2 Ω ID(ON) Typ VGS = 4.5V, VDS = 20V VGS = 10V, VDS = 20V VGS = 4.5V, ID = 20mA VGS = 10V, ID = 50mA VDS = 10V, ID = 50mA pF VGS = 0V, VDS = 25V f = 1 MHz ns VDD = 60V, ID = 50 mA, RGEN = 25Ω V ISD = 65mA, VGS = 0V Notes: 1. All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.) 2. All A.C. parameters sample tested. Switching Waveforms and Test Circuit VDD RL 10V 90% PULSE GENERATOR INPUT 0V 10% t(ON) td(ON) Rgen t(OFF) tr td(OFF) OUTPUT tF D.U.T. VDD 10% INPUT 10% OUTPUT 0V 90% 90% 7-14