HV300/HV310 HV300 HV310 Kit Demo able Avail Hotswap, Inrush Current Limiter Controllers (Negative Supply Rail) General Description Features ❏ HV300, PWRGD=Active HIGH ❏ HV310, PWRGD=Active LOW ❏ -10V to -90V Input Voltage Range ❏ Few External Components ❏ 0.33mA Typical Standby Supply Current ❏ Programmable Over/Under Voltage Limits with Hysteresis ❏ Programmable Current Limit ❏ Active control during all phases of start-up ❏ Programmable timing ❏ 8 Lead SOIC The Supertex HV300 (and HV310), Hotswap Controller, Negative Supply control power supply connection during insertion of cards or modules into live backplanes. They may be used in traditional ‘negative 48V’ powered systems or for higher voltage busses up to negative 90V. Operation during the initial power up prevents turn-on glitches, and after complete charging of load capacitors (typically found in filters at the input of DC-DC converters) the HV300 (and HV310) issues a power good signal. This signal is typically used to enable the DC-DC converter. The only difference between the HV300 and the HV310 is the polarity of the PWRGD signal line to accommodate different DC-DC converter models. Once PWRGD signal has been established the device sleeps in a low power state, important for large systems with many individual hotswap cards or modules. Applications An external power MOSFET is required as the pass element, plus a ramp capacitor, and resistors to establish current limiting and over and under voltage lockouts. There is no need for additional external snubber components. ❏ Central Office Switching ❏ Servers ❏ POTS Line Cards ❏ ISDN Line Cards ❏ xDSL Line Cards ❏ PBX Systems ❏ Powered Ethernet for VoIP ❏ Distributed Power Systems ❏ Negative Power Supply Control ❏ Antenna and Fixed Wireless Systems Features are programmable over voltage and under voltage detection of the input voltage which locks out the load connection if the bus (input) voltage is out of range. An internal voltage regulator creates a stable reference, and maintains accurate gate drive voltage. The unique control loop scheme provides full current control and limiting during start up. Theory of Operation Initially the external N-channel MOSFET is held off by the gate signal, preventing an input glitch. After a delay (while internal circuits are activated) the inrush current to the load is limited by the gate control output. The current may ramp up and limit at a maximum value programmed by an external resistor. Initial time delay, to allow for contact bounce, and charging operation is determined by the single external ramp capacitor connected to the RAMP pin. When the load capacitor is fully charged, the controller emerges from current limit mode, an additional time delay occurs before the external N-channel MOSFET pass transistor is switched to full conduction, and the PWRGD output signal is activated. The controller will then transition to a low power standby mode. Ordering Information VEE Package Options Min Max Power Good Signal 8 Pin SOIC -90V -10V Active HIGH HV300LG -90V -10V Active LOW HV310LG The HV300LG PWRGD is active high (open drain), while the HV310LG PWRGD is active low (VEE). 08/26/02 Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website. 1 HV300/HV310 Electrical Characteristics (V IN Symbol Supply =-10V to -90V, -40°C ≤ TA ≤ +85°C unless otherwise noted) Parameters Min Typ Max Unit Conditions 550 330 -10 650 400 V µA µA VEE = -48V, Mode = Limiting VEE = -48V, Mode = Standby (Referenced to VDD pin) VEE IEE IEE Supply Voltage Supply Current Standby Mode Supply Current OV and UV Control VUVH VUVL VUVHY IUV VOVH VOVL VOVHY IOV (Referenced to VEE pin) UV High Threshold UV Low Threshold UV Hysteresis UV Input Current OV High Threshold OV Low Threshold OV Hysteresis OV Input Current Current Limit VSENSE -90 1.26 1.16 100 1.0 V V mV nA V V mV nA 1.0 1.26 1.16 100 Current Limit Threshold Voltage VOV = VEE + 0.5V 40 50 60 mV VUV = VEE + 1.9V, VOV = VEE + 0.5V 10 11 V VUV = VEE + 1.9V, VOV = VEE + 0.5V VUV = VEE + 1.9V, VOV = VEE + 0.5V, (Referenced to VEE pin) VGATE Maximum Gate Drive Voltage 9.0 IGATEUP Gate Drive Pull-Up Current 500 µA IGATEDOWN Gate Drive Pull-Down Current 40 mA Timing Control – VUV = VEE, VOV = VEE + 0.5V Test Conditions: C =100µF, CRAMP=10nF, VUV = VEE+1.9V, VOV= VEE+0.5V, External MOSFET is IRF530* Ramp Pin Output Current Time from UV to Gate Turn On Time from Gate Turn On to VSENSE Limit Duration of Current Limit Mode Time from Current Limit to PWRGD Voltage on Ramp Pin in Current Limit Mode Power Good Output VPWRGD VPWRGD VUV = VEE + 1.9V Low to High Transition High to Low Transition (Referenced to VEE pin) Gate Drive Output IRAMP tPOR tRISE tLIMIT tPWRGD VRAMP Low to High Transition High to Low Transition 10 5.0 3.6 µA ms µs ms ms V 0.5 0.8 V V 500 500 ns ns 2.0 400 5.0 VSENSE = 0V (Note 1) (Note 2) (Referenced to VEE pin) Power Good Pin Breakdown Voltage Power Good Pin Output Low Voltage 90 IPWRGD = 1mA Dynamic Characterstics tGATEHLOV tGATEHLUV OV Delay UV Delay Note 1: This timing depends on the threshold voltage of the external N-Channel MOSFET. The higher its threshold is, the longer this timing. Note 2: This voltage depends on the characteristics of the external N-Channel MOSFET. *IRF530 is a registered trademark of International Rectifier. 2 VGS(th) = 3V for an IRF530. HV300/HV310 Timing Diagrams I LIM = contact bounce GND t START = 1.2V VOUT VIN VOUT VSENSE RSENSE VUVL VIN -48V VGATE tTH = VGS ( th ) CRAMP I RAMP CRAMP I RAMP tSTART t POR = t START + tTH VRAMP VRAMP VGATE VGS(lim) VGATE VGS(th) t RISE ≈ VEE tTH tPOR IIN CRAMP I RAMP R g fs − SENSE RFB 0.9 I LIM ILIM 90% t LIM ≈ VIN tRISE ( tPWRGD CLOAD 1 − t RISE I LIM 2 t PWRGD = VINT − VGS (lim) − 1.2V tLIM ) CIRAMP RAMP active PWRGD VINT is the internally regulated supply voltage and can range from 9V to 11V. inactive Initialization VGS(th) is the gate threshold voltage of the external pass transistor and may be obtained from its datasheet. Full On Limiting VGS(lim) is the pass transistor gate-source voltage required to obtain the limit curent. It is dependent on the pass transistor’s characteristics and may be obtained from the transfer characteristics curves on the transistor datasheet. gfs is the transconductance of the pass transistor and may be obtained from its datasheet. RFB is the internal feedback resistor and is 5kΩ nominal. Absolute Maximum Ratings VEE reference to VDD pin +0.3V to -100V VPWRGD referenced to VEE Voltage -0.3V to +100V Operating Ambient Temperature Range -40°C to +85°C Operating Junction Temperature Range -40°C to +125°C Storage Temperature Range -65°C to +150°C UV & OV ref to VEE -0.3V to +12V 3 HV300/HV310 Functional Block Diagram VDD Internal Supply Regulator Band Gap Reference UVLO and POR Vref HV300:PWRG VINT HV310: PWRGD UV Vref LOGIC VINT VREF OV – VINT –1.2V 10µA + Transconductor Buffer 5kΩ VEE SENSE Pinout RAMP GATE PWRGD Logic Model PWRGD 1 8 VDD OV 2 7 RAMP UV 3 6 GATE VEE 4 5 SENSE HV300 Condition PWRGD NOT READY 0 VEE READY 1 HI Z NOT READY 1 HI Z READY 0 VEE HV310 Pin Description PWRGD – The Power Good Output Pin is held inactive on initial power application and will go active when the external MOSFET is fully turned on. This pin may be used as an enable control when connected directly to a PWM power module. RAMP – This pin provides a current output so that a timing ramp voltage is generated when a capacitor is connected. The initial portion of the ramp provides a time delay, which in conjunction with the Under Voltage detection circuit eliminates circuit card insertion contact bounce. The RAMP pin also controls the delay between the current limit mode disengaging and the PWRGD signal activating; as well as the current rise profile after the initial turn on delay. OV – This Over Voltage sense pin, when raised above its high threshold will immediately cause the GATE pin to be pulled low. The GATE pin will remain low until the voltage on this pin falls below the low threshold limit, initiating a new start-up cycle. GATE – This is the Gate Driver Output for the external NChannel MOSFET. UV – This Under Voltage sense pin, when below its low threshold limit will ensure that the GATE pin is low. The GATE pin will remain low until the voltage on this pin rises above the high threshold, initializing a new start-up cycle. SENSE – The current sense resistor connected from this pin to VEE pin programs the current limit. Constant current output mode is established when the voltage drop across this resistor reaches 50mV. VEE – This pin is the negative voltage power supply input to the circuit. VDD – This pin is the positive voltage power supply input to the circuit. 4 HV300/HV310 Assuming the above conditions are satisfied and while continuing to hold the PWRGD output inactive and the external MOSFET GATE voltage low, the current source feeding the RAMP pin is turned on. The external capacitor connected to it begins to charge, thus starting an initial time delay determined by the value of the capacitor. If an interruption of the input power occurs during this time (i.e. caused by contact bounce) or the OV or UV limits are exceeded, an immediate reset occurs and the external capacitor connected to the RAMP pin is discharged. Functional Description Insertion Into Hot Backplanes Telecom, Data Network and some Computer applications require the ability to insert and remove circuit cards from systems without powering down the entire system. All circuit cards have some filter capacitance on the power rails, which is especially true in circuit cards or network terminal equipment utilizing distributed power systems. The insertion can result in high inrush currents that can cause damage to connector and circuit cards and may result in unacceptable disturbances on the system backplane power rails. When the voltage on the RAMP pin reaches an internally set voltage limit, the gate drive circuitry begins to turn on the external MOSFET; allowing the current to softly rise over a period of a few hundred micro-seconds to the current limit set point. While the circuit is limiting current, the voltage on the RAMP pin will be fixed. The HV300/HV310 was designed to allow the insertion of these circuit cards or connection of terminal equipment by eliminating these inrush currents and powering up these circuits in a controlled manner after full connector insertion has been achieved. The HV300/HV310 is intended to provide this function on a negative supply rail in the range of -10 to -90 Volts. Depending on the value of the load capacitance and the programmed current limit, charging may continue for some time. The magnitude of the current limit is programmed by comparing a voltage developed by a sense resistor connected between the VEE and SENSE pins to 50mV (Typical). Once the load capacitor has been charged, the current will drop which will cause the ramp voltage to continue rising; providing yet another programmed delay. Waveforms When the ramp voltage is within 1.2V of the internally regulated voltage, the controller will force the GATE full on and will activate the PWRGD pin and the circuit will transition to a low power standby mode. The PWRGD pin is often used as an enable for downstream DC/DC converter loads. Drain 50V/div VIN 50V/div At any time during the start up cycle or thereafter, crossing the UV and OV limits (including hysteresis) will cause an immediate reset of all internal circuitry. Thereafter the start up process will begin again. Gate 5.00V/div Iinrush 500mA/div 5.00ms/div Operation On initial power application an internal regulator seeks to provide 10 Volts for the internal IC circuitry. Until the proper internal voltage is achieved all circuits are held reset, the open drain PWRGD signal is inactive to inhibit the start of any load circuitry and the gate to source voltage of the external N-channel MOSFET is held low. Once the internal under voltage lock out (UVLO) has been satisfied, the circuit checks the input supply voltage under voltage (UV) and over voltage (OV) sense circuits to ensure that the input voltage is within acceptable programmed limits. These limits are determined by the selected values of resistors R1, R2 and R3, which form a voltage divider. 5 HV300/HV310 Typical Application Circuit GND Long Pin 8 Jumper GND Short Pin R1 487kΩ R2 6.81kΩ VDD 3 2 PWRGD 1 ENABLE UV +5V HV300LG or HV310LG OV Cload R3 9.76kΩ RAMP VEE SENSE GATE 7 4 5 6 Long Pin R4 50mΩ Q1 IRF530 Application Information UVoff = 1.16 = 35 * (R2 + R3) / 500K R2 = (1.16 * 500K) / 35 – 9.76kΩ = 6.81kΩ. Under Voltage and Over Voltage Detection The closest 1% value is 6.81kΩ. The UV and OV pins are connected to comparators with nominal 1.21V thresholds and 100mV of hysteresis (1.21V ± 50mV). They are used to detect under voltage and over voltage conditions at the input to the circuit. Whenever the OV pin rises above its threshold or the UV pin falls below its threshold the GATE voltage is immediately pulled low, the PWRGD signal is deactivated and the external capacitor connected to the RAMP pin is discharged. Then R1 = 500K – (R2 +R3) = 483kΩ The closest 1% value is 487kΩ. The under voltage and over voltage trip points can be programmed by means of the three resistor divider formed by R1, R2 and R3. Since the input currents on the UV and OV pins are negligible the resistor values may be calculated as follows: Undervoltage/Overvoltage Operation GND UVOFF UVON VIN UVoff = VUVH = 1.16 = |VEEUV| * (R2+R3) / (R1+R2+R3) OVON OVOFF OVoff = VOVL = 1.26 = |VEEOV| * R3 / (R1+R2+R3) Where points. |VEEUV| COM NOTES: 1. Undervoltage Lockout (UV) set to 35V 2. Overvoltage Lockout (OV) set to 65V 3. Remove Jumper if Short Pin is used C1 10nF -48V DC/DC PWM CONVERTER and |VEEOV| are Under & Over Voltage Set Pass Transistor If we select a divider current of 100µA at a nominal operating input voltage of 50 Volts then (R1+R2+R3) = 50V / 100µA = 500kΩ ON OFF Current Limit From the second equation for an Over voltage set point of 65 Volts the value of R3 may be calculated. The current limit magnitude above which the current will not be allowed to rise during startup is programmed using a sense resistor connected from the SENSE pin to VEE pin. For example to program a current limit of 1A, one would choose a resistor as follows: OVoff = 1.26 = 65 * R3 / 500kΩ R3 = (1.26 * 500K) / 65 = 9.69 kΩ The closest 1% value is 9.76kΩ. Rsense = 50mV / Isense From the first equation for an Under Voltage set point of 35 Volts the value R2 can be calculated. Rsense = 50mV / 1A Rsense = 50mΩ 08/26/02rev.10b ©2002 Supertex Inc. All rights reserved. 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