HV3418 64-Channel Serial To Parallel Converter With High Voltage Push-Pull Outputs Ordering Information Package Options Device Recommended Operating VPP Max 80-Lead Quad Cerpak Gullwing 80-Lead Quad Plastic Gullwing Die HV3418 180V HV3418DG HV3418PG HV3418X Features General Description ❏ HVCMOS® technology The HV34 is a low voltage serial to high voltage parallel converter with push-pull outputs. This device has been designed for use as a printer driver for inkjet applications. It can also be used in any application requiring multiple output high voltage, low current sourcing and sinking capabilities. ❏ Output voltages up to 180V ❏ Low power level shifting ❏ Shift register speed: 6MHz @ VDD = 5V 12MHz @ VDD = 12V The device consists of a 64-bit shift register, 64 latches, and control logic to perform the polarity select and blanking of the outputs. A DIR pin controls the direction of data shift through the device. With DIR grounded, DIOA is Data-In and DIOB is Data-Out; data is shifted from HVOUT64 to HVOUT1. When DIR is at logic high, DIOB is Data-In and DIOA is Data-Out: data is then shifted from HVOUT1 to HVOUT64. Data is shifted through the shift register on the low to high transition of the clock. Data output buffers are provided for cascading devices. Operation of the shift register is not affected by the LE (latch enable), BL (blanking), or the POL (polarity) inputs. Transfer of data from the shift register to the latch occurs when the LE (latch enable) is high. The data in the latch is stored during LE transition from high to low. ❏ Latched data outputs ❏ Output polarity and blanking ❏ CMOS compatible inputs ❏ Forward and reverse shifting options Absolute Maximum Ratings1 Supply voltage, VDD -0.5V to +15V Supply voltage, VPP VDD to +200V Logic input levels -0.5V to VDD +0.5V Ground current2 1.5A High voltage supply current2 1.3A Continuous total power dissipation3 Ceramic Plastic Operating temperature range Storage temperature range 1900mW 1200mW Ceramic -55°C to +125°C Plastic -40°C to +85°C -65°C to +150°C Notes: 1. All voltages are referenced to GND. 2. Connection to all power and ground pads is required. Duty cycle is limited by the total power dissipated in the package. 3. For operation above 25°C ambient derate linearly to maximum operating temperature at 20mW/°C for plastic and at 31.7mW/°C for ceramic. 12/13/01 Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to 1 workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website. HV3418 Electrical Characteristics (over recommended operating conditions unless noted) DC Characteristics Symbol IDD Parameter Min Typ VDD Supply Current Max Units 25 mA Conditions fCLK = 12MHz, fDATA = 12MHz LE = LOW IDDQ Quiescent VDD Supply Current 200 µA All VIN = 0V or VDD IPP High Voltage Supply Current 0.50 mA VPP = 180V All outputs high 0.50 mA VPP = 180V All outputs low IIH High-Level Logic Input Current 10 µA VIH = VDD IIL Low-Level Logic Input Current -10 µA VIL = 0V VOH High-Level Output 155 V VPP = 180V, IHVOUT = -5mA VDD -1V V IDOUT = -100µA HVOUT Data Out VOL VOC Low-Level Output HVOUT 25 V VPP = 180V, IHVOUT = +5mA Data Out 1.0 V IDOUT = +100µA VPP +1.5 V IOL = +5mA -1.5 V IOL = -5mA HVOUT Clamp Voltage AC Characteristics1,2 (For VDD = 12V: values in parentheses are for VDD = 5V; VPP = 180V, TA = 25°C) Symbol Parameter fCLK Clock Frequency tW Clock Width High and Low tSU Min High Typ Max Units 12(6) MHz 40(83) ns Data Setup Time Before Clock Rises 25(35) ns tH Data Hold Time After Clock Rises 10(30) ns tWLE Width of Latch Enable Pulse 62(80) ns tDLE LE Delay Time Rising Edge of Clock 25(35) ns tSLE LE Setup Time Before Rising Edge of Clock 30(40) ns tON, tOFF Time from Latch Enable to HVOUT tDHL Conditions 1(1.5) µs CL = 20pF Delay Time Clock to Data High to Low 50(110) ns CL = 20pF tDLH Delay Time Clock to Data Low to High 75(160) ns CL = 20pF tr, tf All Logic Inputs 5 ns Notes: 1. Shift register speed can be as low as DC as long as Data Set-up and Hold Time meet the spec. 2. AC Characteristics are guaranteed only under VDD = 12V and VDD = 5V. Recommended Operating Conditions Symbol VDD Parameter Logic supply voltage VPP High voltage supply VIH High-level input voltage VIL Low-level input voltage TA Operating free-air temperature Notes: Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. Power-down sequence should be the reverse of the above. Min Typ Max VDD = 5V 4.5 5.0 5.5 V VDD =12V 10.8 12.0 13.2 V 60 180 V VDD -0.9 VDD V 0 0.9 V Plastic -40 +85 Ceramic -55 +125 4. Apply VPP. 5. The VPP should not drop below VDD or float during operation. 2 Units °C HV3418 Input and Output Equivalent Circuits VDD VDD VPP Data Out Input HVOUT GND GND GND Logic Data Output Logic Inputs High Voltage Outputs Switching Waveforms VIH Data Input 50% Data Valid 50% VIL tH tSU VIH Clock 50% 50% 50% tWL 50% VIL tWH VOH 50% VOL tDLH D IO/D OI VOH 50% VOL tDHL Latch Enable VIH 50% 50% VOL tDLE tWLE tSLE 90% 10% HV OUT w/ S/R LOW VOH VOL tOFF HV OUT w/ S/R HIGH 10% tON 3 90% VOH VOL HV3418 Functional Block Diagram POL BL Latch Enable VPP DIOA HVOUT1 Clock HVOUT2 64 bit Static Shift Register DIR • • • 60 Additional Outputs • • • HVOUT63 64 Latches HVOUT64 DIOB Function Table Inputs Function Data CLK LE Outputs BL POL DIR Shift Reg HV Outputs Data Out 1 2…64 1 2…64 * All on X X X L L X * *…* H H…H * All off X X X L H X * *…* L L…L * Invert mode X X L H L X * *…* * *…* * H or L ↑ L H H X H or L *…* * *…* * Load/Store Data in Latches X X ↓ H H X * *…* * *…* * X X ↓ H L X * *…* * *…* * Transparent Latch mode L ↑ H H H X L *…* L *…* * H ↑ H H H X H *…* H *…* * DIOA ↑ X X X L Qn→ Qn-1 — DIOB DIOB ↑ X X X H Qn→ Qn+1 — DIOA Load S/R I/O Relation Notes: H = high level, L = low level, X = irrelevant, ↑ = low-to-high transition, ↓ = high-to-low transition. * = dependent on previous stage’s state before the last CLK or last LE high. 4 HV3418 Pin Configurations HV34 Pin Function 1 HVOUT 41/24 2 HVOUT 42/23 3 HVOUT 43/22 4 HVOUT 44/21 5 HVOUT 45/20 6 HVOUT 46/19 7 HVOUT 47/18 8 HVOUT 48/17 9 HVOUT 49/16 10 HVOUT 50/15 11 HVOUT 51/14 12 HVOUT 52/13 13 HVOUT 53/12 14 HVOUT 54/11 15 HVOUT 55/10 16 HVOUT 56/9 17 HVOUT 57/8 18 HVOUT 58/7 19 HVOUT 59/6 20 HVOUT 60/5 21 HVOUT 61/4 22 HVOUT 62/3 23 HVOUT 63/2 24 HVOUT 64/1 25 VPP 26 DIOA 27 N/C 28 N/C 29 BL 30 POL 31 VDD 32 DIR 33 LGND 34 OGND 35 N/C 36 N/C 37 CLK 38 LE 39 DIOB 40 VPP Package Outline 41 64 Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Function HVOUT 1/64 HVOUT 2/63 HVOUT 3/62 HVOUT 4/61 HVOUT 5/60 HVOUT 6/59 HVOUT 7/58 HVOUT 8/57 HVOUT 9/56 HVOUT 10/55 HVOUT 11/54 HVOUT 12/53 HVOUT 13/52 HVOUT 14/51 HVOUT 15/50 HVOUT 16/49 HVOUT 17/48 HVOUT 18/47 HVOUT 19/46 HVOUT 20/45 HVOUT 21/44 HVOUT 22/43 HVOUT 23/42 HVOUT 24/41 HVOUT 25/40 HVOUT 26/39 HVOUT 27/38 HVOUT 28/37 HVOUT 29/36 HVOUT 30/35 HVOUT 31/34 HVOUT 32/33 HVOUT 33/32 HVOUT 34/31 HVOUT 35/30 HVOUT 36/29 HVOUT 37/28 HVOUT 38/27 HVOUT 39/26 HVOUT 40/25 40 65 Index 25 80 24 1 top view 80-pin Gullwing Package Note: Pin designation for DIR = H/L Example: for DIR = H, Pin 1 is HVOUT41 for DIR = L, Pin 1 is HVOUT24 12/13/010 ©2001 Supertex Inc. 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