HV6810 10-Channel Serial-Input Latched Display Driver Ordering Information Package Options Device 18-Pin Plastic DIP 20-Pin Small Outline Package 20-Pin Plastic Chip Carrier Die HV6810 HV6810P HV6810WG HV6810PJ HV6810X *For Hi-Rel process flow, refer to page 5-3 of the Databook. Features General Description ■ High output voltage 80V The HV6810 is a monolithic integrated circuit designed to drive a dot matrix or segmented vacuum fluorescent display (VFD). These devices feature a serial data output to cascade additional devices for large displays. ■ High speed 5MHz @ 5VDD ■ Low power IBB ≤ 0.1mA (All high) ■ Active pull down 100µA min A 10-bit data word is serially loaded into the shift register on the positive-going transition of the clock. Parallel data is transferred to the output buffers through a 10-bit D-type latch while the latch enable input is high and is latched when the latch enable is low. When the blanking input is high, all outputs are low. ■ Output source current 100mA at 60V VPP ■ Each device drives 10 lines ■ High-speed serially-shifted data input Outputs are structures formed by double-diffused MOS (DMOS) transistors with output voltage ratings of 80 volts and 25 milliampere source-current capability. All inputs are compatible with CMOS levels. ■ 5V CMOS-compatible inputs ■ Latches on all driver outputs ■ Pin-compatible improved replacement for UCN5810A and TL4810A, TL4810B Absolute Maximum Ratings1 Logic supply voltage, VDD2 7.5V Driver supply voltage, VBB2 90V Output voltage2 Input voltage2 Continuous total power dissipation at 25°C free-air temperature 3 Operating Temperature Range 90V -0.3V to VDD + 0.3V 18-Pin P-DIP3 900mW 20-Pin SOIC4 1000mW 20-Pin PLCC4 1000mW -40° to +85*C Notes: 1. Over operating free-air temperature. 2. All voltages are referenced to VSS. 3. For operation above 25°C ambient derate linearly to 85°C at 15mW/°C. 4. For operation above 25°C ambient derate linearly to 85°C at 16.7mW/°C. 12-142 HV6810 Electrical Characteristics DC Characteristics (VDD = 5V ±10%, VBB = 60V, VSS = 0, TA = 25°C unless otherwise noted) Symbol Parameter High-level output voltage VOH Q outputs Min Typ 57.5 58 V IOH = 25mA 4 4.5 V VDD = 4.5V, IOH = -100µA Serial output Low-level output voltage VOL Units Conditions Q outputs 0.15 1 V IOH = 100µA, Blanking input at VDD Serial output 0.05 0.1 V VDD = 4.5V, IOL = 100µA µA TA = Max, VOL = 0.7V -15 µA VO = 0, Blanking input TA = Max at VDD 1 µA VI = VDD 10 50 µA All inputs at 0V, one Q output high 10 50 µA All inputs at 0V, all Q outputs low 0.05 0.1 mA All outputs low, all Q outputs open 0.05 0.1 mA All outputs high, all Q outputs open IOL Low-level Q output current (pull-down current) IO(OFF) Off-state output current IH High-level input current IDD Supply current from VDD (standby) 60 80 -1 Supply current from VBB IBB Max * All typical values are at TA = 25°C, except for IO. AC Characteristics (Timing requirements over recommended operating conditions) Symbol Parameter Min Typ Max Units tW(CKH) Pulse duration, clock high 100 ns tW(LEH) Pulse duration, latch enable high 100 ns tSU(D) Setup time, data before clock 50 ns tH(D) Hold time, data after clock 50 ns tCKH-LEH Delay time, clock to latch enable high 50 ns tpd* Propagation delay time, latch enable to output Conditions µs 0.3 * Switching characteristics, VBB = 60V, TA = 25°C. Recommended Operating Conditions Symbol Parameter Min Nom Max Units VDD Supply voltage 4.5 5.5 V VBB Supply voltage 20 80 V VSS Supply voltage VIH High-level input voltage (for VDD = 5V) 3.5 5.3 V VIL Low-level input voltage -0.3 0.8 V IOH Continuous high-level Q output current -25 fCLK Clock frequency TA Operating free-air temperature 0 Plastic Note: Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 4. Apply VPP. Power-down sequence should be the reverse of the above. 12-143 -40 V mA 5 MHz +85 °C HV6810 Input and Output Equivalent Circuits VDD VBB Output Input VSS VSS Logic Data Output Input Equivalent Circuit Timing Diagram Clock Data In SR Contents VALID IRRELEVANT INVALID VALID Latch Enable Latch Contents PREVIOUSLY STORED DATA NEW DATA VALID Blanking Q Outputs VALID 12-144 HV6810 Functional Block Diagram Logic Diagram (positive logic) Blanking Latch Enable Shift Register Data Input Clock • • • Latches 1D C1 R1 C2 2D LC1 Q1 1D C1 R2 C2 2D LC2 Q2 • • • • • • 6 Stages (Q3 thru Q8) not shown • • • 1D C1 R9 C2 2D LC9 Q9 1D C1 R10 C2 2D LC10 Q10 Serial Out Function Table Serial Data Input Clock Input Shift Register Contents I1 I2 I3 … IN-1 IN Serial Data Output Strobe Input Latch Contents I1 I2 I3 … IN-1 Output Contents Blanking Input IN I1 I2 I3 … IN-1 IN H H R1 R2 … RN-2 RN-1 RN-1 L L R1 R2 … RN-2 RN-1 RN-1 X R1 R2 R3 … RN-1 RN RN X X X …X X L R1 R2 R3 … RN-1 RN PN H P1 P2 P3 … PN-1 PN L P1 P2 P3 … PN-1 PN X X X …X H L L L …L X P1 P2 P3 … PN-1 PN X L L = Low logic level H = High logic level X = Irrelevant P = Present state R = Previous state Switching Waveforms t w(CKH) V IH 50% Clock 50% Clock Input V IL t su(D) 50% V IH Valid V IL t CKH–LEH t h(D) Latch Enable V IH Valid Data 50% 50% Output V IL Input Timing t w(LEH) 50% 50% t pd 90% Valid Output Switching Times 12-145 V IH V IL HV6810 Pin Configurations HV6810 18-Pin DIP Pin Function 1 Q8 2 Q7 3 Q6 4 Clock 5 VSS 6 VDD 7 LE (strobe) 8 Q5 9 Q4 Pin 10 11 12 13 14 15 16 17 18 Package Outlines Function Q3 Q2 Q1 Blanking Data in VBB Serial data out Q10 Q9 1 18 2 17 3 16 4 15 5 14 6 13 7 12 8 11 9 10 top view 18-pin DIP HV6810 20-Pin SOW Pin Function 1 Q8 2 Q7 3 Q6 4 Clock 5 VSS 6 N/C 7 VDD 8 LE (strobe) 9 Q5 10 Q4 Pin 11 12 13 14 15 16 17 18 19 20 Function Q3 Q2 Q1 Blanking Data in VBB Serial data out N/C Q10 Q9 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 top view SOW-20 HV6810 20-Pin Plastic PLCC Pin Function 1 Q8 2 Q7 3 Q6 4 Clock 5 N/C 6 VSS 7 VDD 8 LE(Strobe) 9 Q5 10 Q4 18 Pin 11 12 13 14 15 16 17 18 19 20 Function Q3 Q2 Q1 Blanking Data In N/C VBB Serial data out Q10 Q9 17 16 15 19 13 20 12 1 • 11 2 10 3 9 4 5 6 7 top view 20-pin PLCC 12-146 14 8