SUPERTEX HV9605

HV9605
HV9605
Preliminary
High Voltage Current Mode PWM
Controller for ISDN Equipment
Ordering Information
+VIN
Min
Max
Feedback
Accuracy
15V
250V
< ± 1%
Max
Duty Cycle
49%
14 Pin
Plastic DIP
HV9605P
Package Options
14 Pin
Narrow Body SOIC
HV9605NG
Features
Die
HV9605X
General Description
BiCMOS/DMOS technology
The Supertex HV9605 is a BiCMOS/DMOS single-output,
current mode, pulse width modulator IC designed to meet
the requirements of ETR-060 for ISDN applications. In a 14
pin package, it provides all the necessary functions to implement a single-switch PWM with a minimum of external parts.
Current mode control
49% duty cycle operation
Programmable START/STOP capability
Utilizing Supertex’s proprietary BiCMOS/DMOS technology,
it requires less than one tenth of the operating power of
conventional bipolar PWM ICs. Dynamic range for regulation
is also increased to approximately 8 times that of similar
bipolar parts. It operates directly from any DC input voltage
between 15 and 250 VDC. The START and STOP input
voltage thresholds can be programmed within the operating
input voltage range by means of a resistor divider, provided
+VIN(START) > +V IN(STOP). The output stage is push-pull CMOS,
eliminating the need for external clamping diodes. The clock
frequency is set with a single external resistor.
15V to 250V input range internal start-up regulator
6.0µA standby supply current for +VIN <20V
0.9mA operating supply current
5.0V V DD supply operation
30KHz to 300KHz internal oscillator
15KHz to 150KHz converter output frequency
1.0MHz low offset error amplifier
1.20V 2% band gap reference
Output driver optimized for under 10W applications
Low driver output impedance with VDD = 0V
Fast (90nsec) over current shutdown
All pins are ESD protected
Applications
Absolute Maximum Ratings*
ISDN network terminations
+VIN, Input Voltage
ISDN terminals
Supply Voltage, V DD
ISDN terminal adapters
Operating Temperature Range
-0.5V to +250V
-0.5V to +10V
-40°C to +85°C
Feature phones
Storage Temperature Range
SLIC circuits
PBX systems
Power Dissipation @ 25°C, SOIC
Modems
Power Dissipation @ 25°C, Plastic DIP
Distributed power systems
*All voltages referenced to GND
-65°C to +150°C
750mW
1000mW
DC/DC converters
11/30/98
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For complete liability information11/30/98
covering
this and other Supertex products, refer to the Supertex 1998 Databook.
1
HV9605
Electrical Characteristics
Symbol
Parameters
Min
Typ
Max
Unit
250
V
Conditions
Pre-Regulator/Start-Up
+VIN
Regulator input voltage
15
+IIN
Input leakage current
6.0
µA
+VIN=20V, Start=0V, Stop=0V
+IIN
Input leakage current
50
µA
+VIN = 250V, VDD = 4.7V
+ISTART
Pre-regulator start-up current
5.0
mA
+VIN = 15V,
Start & Stop 10MΩ to + VIN
VDD
Regulator output voltage
4.4
4.5
4.6
V
UVLO
Under voltage lockout threshold
4.1
4.2
4.4
V
HYST
Under voltage hysteresis
0.1
0.3
0.4
V
VDD
Operating range
4.7
8.0
V
IDD
Supply current
0.9
1.3
mA
7.30
7.88
V
VDD rising
Supply
OUT open,
fOUT = 20KHz to 150KHz,
VDD = 5V
Start/Stop Control
VSTART
Start threshold
6.72
ISTART
Start input current
0.05
µA
+VIN = 18V
ISTOP
Stop input current
0.05
µA
+VIN = 18V
VCLAMP
Zener clamp voltage on STOP Pin
20
V
MOSFET Driver Output
VOUT(HIGH)
Output high voltage
VOUT(LOW)
Output low voltage
tR
tF
4.85
4.90
V
IOUT = 10mA, VDD = 5.00V
IOUT = -10mA
0.05
0.15
V
Rise time
30
50
nsec
CL = 250pf
Fall time
20
50
nsec
CL = 250pf
KHz
RT = 91KΩ
Oscillator
150
fOUT
Output converter frequency
TC
Temperature coefficient
∆f/f
Voltage stability
45
50
55
KHz
RT = 390KΩ
31.5
35
38.5
KHz
RT = 560KΩ
18
20
22
KHz
RT = 1.0MΩ
100
300
PPM/°C
1
3
%
fOUT = 50KHz
fOUT = 50KHz, 4.5V< VDD<5.5V
11/30/98
2
HV9605
Electrical Characteristics
Symbol
(continued)
Parameters
Min
DMAX
Maximum duty cycle
49.0
DMIN
Minimum duty cycle
Typ
Max
Unit
Conditions
49.9
%
fOUT = 20KHz
0
%
80
125
nsec
1.200
1.224
V
PWM
Minimum pulse width before pulse drop out
Reference
VREF
Reference output voltage
VREF
Load regulation
1.0
5.0
mV
0 < IREF < 0.3mA
VREF
Line regulation
2.0
5.0
mV
3.0V < VDD < 5.5V
VREF
Reference output voltage
1.200
1.241
V
-40°C < TA < 85°C
IREF(SHORT)
1.176
1.159
TA = 25°C
mV
TA = 125°C, 1000hrs
1.0
mA
VREF = SGND
VCS (limit)
V
0.7
0.8
V
90
120
nsec
1.200
1.212
V
REF shorted to NI, FB
shorted to Comp, TA = 25°C
VFB = 3.0V, VNI = 2.5V
Long term stability
3.0
Short circuit current
0.5
Current Sensing
VCS
Usable control current sense range
VCS (LIMIT)
Current limit threshold
tDELAY
Current limit delay to output
0.6
VCS = 1.5V
Error Amplifier
VFB
Feedback voltage
1.188
IFB or INI
Input bias current
25
200
nA
VOS
Input offset voltage
5.0
25
mV
VCM
Common mode input range
0
VDD-1
V
AVOL
Open loop voltage gain
65
90
dB
BW
Unity gain bandwidth
1.0
1.5
MHz
ISOURCE
Output current sourcing
ISINK
Output current sinking
2
PSRR
Power supply rejection
-2
-1
mA
VFB < VNI
4
mA
VFB > VNI
50
72
dB
4.5V < VDD < 5.5V, f=1KHz
mA
VSTATUS = 2.0V
Status Output
ISINK
Output current sinking
5.0
10
ISOURCE
Output current sourcing
5.0
10
VSTATUS(HIGH) High output voltage
VSTATUS(LOW)
tR
µA
VDD
V
No load
1.0
2.0
V
Sinking 5mA
0.02
0.04
V
Sinking 100µA
VDD-0.2
Low output voltage
Rise time
15
1.0
5.0
msec
4.7nF From Status to GND
11/30/98
3
HV9605
Pin Description
COMP - The low impedance output of the error amplifier.
SGND - Common connection for all low level signal and digital
circuits. While SGND and PGND must be electrically connected
together, having separate common pins enhances the ability of
the designer to prevent coupling of noise into critical circuits.
FB
- The high impedance inverting input of the error amplifier.
NI
- The high impedance non-inverting input of the error
amplifier.
PGND - This pin provides common return for the high transient
current of the output driver circuits. While PGND and SGND must
be electrically connected, having a separate connection prevents
common noise created by the high transient currents of the output
driver from being injected into critical circuits.
REF
- This pin provides a 2% accuracy 1.20V low output
impedance buffered reference which is current limited to 0.5mAmps
and should be bypassed, REF to SGND, with a 0.1µF ceramic
capacitor.
+VIN
- This is the start-up linear pre-regulator input which can
accept DC input voltages in the range of 15V to 250V. With
START and STOP set to more than 20V, the leakage current on
this pin is less than 6.0µA at +VIN = 20V.
RT
- The resistor connected from this pin to SGND sets the
frequency of the internal oscillator by setting the charging current
for the internal timing capacitor. The oscillator frequency is twice
the PWM output frequency.
START - The resistive divider from +VIN sets the start voltage.
STATUS - This output is held low until the +VIN voltage reaches
the programmed START voltage. It remains low until the bootstrap supply to VDD forces the voltage above the internal regulator
set point. It is further held low while the control amplifier output on
the COMP pin is forced to its high limit by a low output from the
converter. Once all these conditions are satisfied, this output will
rise to VDD with a time constant set by the external capacitor
indicating that normal operation has been reached. This output
may be used to control the reset of a microprocessor.
STOP - The resistive divider from +VIN sets the stop voltage.
- This is the supply pin for the PWM circuits. When the
VDD
input voltage to the +VIN pin exceeds the start voltage the input
regulator seeks to regulate the voltage on the capacitor connected to this pin to a nominal 4.5V.
OUT
- This high current push-pull CMOS output is intended
to drive the gate of a power MOSFET. In order to protect the
power MOSFET in high electrical noise environment, this output
appears as low impedance to PGND when VDD is at zero volts.
CS
- This is the current sense input to the PWM comparators. Under normal operation the over current limit is triggered
when the voltage on this pin is at 0.70V and the loop control
operating peak current may be set to any level below this, typically
in the range of 0.2 to 0.5V.
Pin Configuration
+VIN
1
14
COMP
STOP
2
13
FB
START
3
12
NI
REF
4
11
STATUS
VDD
5
10
RT
PGND
6
9
SGND
CS
7
8
OUT
14 Pin SOIC/DIP Package
11/30/98
4
HV9605
Functional Block Diagram
VDD
+VIN
STOP
Start-Up
Regulator
H=SWITCH CLOSED
L= SWITCH OPEN
Enable
START
+
–
UVLO
+
VREF
–
C
C
VSTART
Bootstrap Good
PWM Good
STATUS
MOSFET Driver
VDD
Clock
Oscillator
CLK Q
D
OUT
Q
CLR
S Q
+
A
-
–
C
R
+
CS
PGND
SGND
VDD
Bandgap
Reference
Generator
RT
REF
NI
FB
COMP
Typical Application Circuit
HV9605
+
48V INPUT
-
+
VDD
+VIN
+
+
STATUS
STOP
TN2124K1
or
TN2524N8
OUT
START
+
40V
+ ISOLATED
OUTPUT
RESET
CS
+5.0V
REFERENCED
TO INPUT (-)
TERMINAL
PGND
RT
REF
NI
FB
SGND
COMP
11/30/98
5
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 • FAX: (408) 745-4895
www.supertex.com
11/30/98