CSP-6 TPS62690, TPS62691 SLVS965 – MARCH 2011 www.ti.com 500-mA / 600-mA, 4-MHz HIGH-EFFICIENCY STEP-DOWN CONVERTER IN CHIP SCALE PACKAGING Check for Samples: TPS62690, TPS62691 FEATURES 1 • • • • • 95% Efficiency at 4MHz Operation 19μA Quiescent Current 4MHz Regulated Frequency Operation High Duty-Cycle Operation ±2% Total DC Voltage Accuracy Best in Class Load and Line Transient Excellent AC Load Regulation Low Ripple Light-Load PFM Mode ≥40dB VIN PSRR (1kHz to 10kHz) Internal Soft Start, 250-μs Start-Up Time Integrated Active Power-Down Sequencing (Optional) Current Overload and Thermal Shutdown Protection Three Surface-Mount External Components Required (One 2012 MLCC Inductor, Two 0402 Ceramic Capacitors) Complete Sub 1-mm Component Profile Solution Total Solution Size <12 mm2 Available in a 6-Pin NanoFree™ (CSP) 100 150 VI = 3.6 V, 95 VO = 2.85 V 135 90 120 Efficiency PFM/PWM Operation Efficiency - % 85 105 80 90 75 75 Power Loss PFM/PWM Operation 70 60 65 45 60 30 Power Loss - mW • • • • • • • • • • • 2 APPLICATIONS • • • • LDO Replacement Cell Phones, Smart-Phones Portable Audio, Portable Media DC/DC Micro Modules DESCRIPTION The TPS6269x device is a high-frequency synchronous step-down dc-dc converter optimized for battery-powered portable applications. Intended for low-power applications, the TPS6269x supports up to 600-mA load current, and allows the use of low cost chip inductor and capacitors. The device is ideal for mobile phones and similar portable applications powered by a single-cell Li-Ion battery. Different fixed voltage output versions are available from 2.2V to 2.9V. The TPS6269x operates at a regulated 4-MHz switching frequency and enters the power-save mode operation at light load currents to maintain high efficiency over the entire load current range. The PFM mode extends the battery life by reducing the quiescent current to 19μA (typ) during light load operation. For noise-sensitive applications, the device can be forced into fixed frequency PWM mode by pulling the MODE pin high. This feature, combined with high PSRR and AC load regulation performance, make this device suitable to replace a linear regulator to obtain better power conversion efficiency. VIN 3.15 V .. 4.8 V CI TPS62690 VIN SW EN FB 4.7 mF 50 0.1 VOUT 2.85 V @ 500mA 1.0 mH CO 4.7 mF GND 55 L MODE 15 1 10 100 IO - Load Current - mA 0 1000 Figure 2. Smallest Solution Size Application Figure 1. Efficiency vs. Load Current 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. © 2011, Texas Instruments Incorporated TPS62690, TPS62691 SLVS965 – MARCH 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) TA -40°C to 85°C (1) (2) (3) (4) PACKAGE MARKING CHIP CODE PART NUMBER OUTPUT VOLTAGE (2) DEVICE SPECIFIC FEATURE ORDERING (3) TPS62690 2.85V 500mA peak output current TPS62690YFF PB TPS62691 (4) 2.2V 600mA peak output current TPS62691YFF SU For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Internal tap points are available to facilitate output voltages in 25mV increments. The YFF package is available in tape and reel. Add a R suffix (e.g. TPS62690YFFR) to order quantities of 3000 parts. Add a T suffix (e.g. TPS62690YFFT) to order quantities of 250 parts. Product preview. Contact TI factory for more information. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) Input Voltage MIN MAX UNIT Voltage at VIN (2) (3), SW (3) –0.3 6 V Voltage at FB (3) –0.3 3.6 V –0.3 VI + 0.3 V TPS62690 500 mA TPS62691 600 mA Voltage at EN, MODE (3) Peak output current, IO Power dissipation Operating temperature range, TA Internally limited (4) –40 85 °C 150 °C 150 °C Human body model 2 kV Charge device model 1 kV 200 V Operating junction temperature, TJ –65 Storage temperature range, Tstg ESD (5) Machine model (1) (2) (3) (4) (5) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Operation above 4.8V input voltage is not recommended over an extended period of time. All voltage values are with respect to network ground terminal. In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA(max)) is dependent on the maximum operating junction temperature (TJ(max)), the maximum power dissipation of the device in the application (PD(max)), and the junction-to-ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA(max)= TJ(max)–(θJA X PD(max)). To achieve optimum performance, it is recommended to operate the device with a maximum junction temperature of 105°C. The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. The machine model is a 200-pF capacitor discharged directly into each pin. THERMAL INFORMATION THERMAL METRIC (1) TPS62690 YFF (6 PINS) θJA Junction-to-ambient thermal resistance θJCtop Junction-to-case (top) thermal resistance 65 θJB Junction-to-board thermal resistance 105 ψJT Junction-to-top characterization parameter 23 ψJB Junction-to-board characterization parameter 95 θJCbot Junction-to-case (bottom) thermal resistance - (1) 2 UNITS 121 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS62690 TPS62691 TPS62690, TPS62691 SLVS965 – MARCH 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS VIN MIN NOM MAX 2.3 4.8 (1) TPS62690 0 500 mA TPS62691 0 600 mA 1.8 µH 10 µF Input voltage range UNIT V IO Output current range L Inductance CO Output capacitance TA Ambient temperature –40 +85 °C TJ Operating junction temperature –40 +125 °C (1) 0.5 1 5 Operation above 4.8V input voltage is not recommended over an extended period of time. ELECTRICAL CHARACTERISTICS Minimum and maximum values are at VIN = 2.3V to 5.5V, VOUT = 2.85V, EN = 1.8V, AUTO mode and TA = –40°C to 85°C; Circuit of Parameter Measurement Information section (unless otherwise noted). Typical values are at VIN = 3.6V, VOUT = 2.85V, EN = 1.8V, AUTO mode and TA = 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX 50 UNIT SUPPLY CURRENT μA IQ Operating quiescent current TPS6269x IO = 0mA. Device not switching 19 TPS62690 IO = 0mA, PWM mode 4.2 I(SD) Shutdown current TPS6269x EN = GND 0.2 5 μA UVLO Undervoltage lockout threshold TPS6269x 2.05 2.1 V mA ENABLE, MODE VIH High-level input voltage VIL Low-level input voltage Ilkg Input leakage current 1 V TPS6269x 0.4 V Input connected to GND or VIN 0.01 1.5 μA VIN = V(GS) = 3.6V. PWM mode 160 280 (1) mΩ VIN = V(GS) = 2.9V. PWM mode 190 350 (1) mΩ 1 μA POWER SWITCH rDS(on) P-channel MOSFET on resistance TPS6269x Ilkg P-channel leakage current, PMOS TPS6269x rDS(on) N-channel MOSFET on resistance TPS6269x Ilkg N-channel leakage current, NMOS TPS6269x rDIS Discharge resistor for power-down sequence P-MOS current limit Input current limit under short-circuit conditions TPS62690 V(DS) = 5.5V, -40°C ≤ TJ ≤ 85°C VIN = V(GS) = 3.6V. PWM mode 110 mΩ VIN = V(GS) = 2.9V. PWM mode 140 mΩ V(DS) = 5.5V, -40°C ≤ TJ ≤ 85°C 2.3V ≤ VIN ≤ 4.8V. Open loop TPS62691 2.3V ≤ VIN ≤ 4.8V. Open loop TPS62690 VO shorted to ground Thermal shutdown Thermal shutdown hysteresis (1) 900 VIN = 3.6V. Closed loop TPS6269x 2 μA 100 150 Ω 1100 1250 mA 830 1050 1250 mA 1400 mA 15 mA 140 °C 10 °C Verified by characterization. Not tested in production. Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS62690 TPS62691 3 TPS62690, TPS62691 SLVS965 – MARCH 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Minimum and maximum values are at VIN = 2.3V to 5.5V, VOUT = 2.85V, EN = 1.8V, AUTO mode and TA = –40°C to 85°C; Circuit of Parameter Measurement Information section (unless otherwise noted). Typical values are at VIN = 3.6V, VOUT = 2.85V, EN = 1.8V, AUTO mode and TA = 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 3.6 4 4.4 MHz 3.15V ≤ VIN ≤ 4.8V, 0mA ≤ IO ≤ 500 mA PFM/PWM operation 0.98×VNOM VNOM 1.03×VNOM V 3.15V ≤ VIN ≤ 5.5V, 0mA ≤ IO ≤ 500 mA PFM/PWM operation 0.98×VNOM VNOM 1.04×VNOM V 3.15V ≤ VIN ≤ 5.5V, 0mA ≤ IO ≤ 500 mA PWM operation 0.98×VNOM VNOM 1.02×VNOM V OSCILLATOR fSW Oscillator frequency TPS6269x IO = 0mA, PWM mode. TA = 25°C OUTPUT Regulated DC output voltage VOUT TPS62690 Line regulation VIN = VO + 0.5V (min 3.15V) to 5.5V IO = 200 mA Load regulation IO = 0mA to 500 mA Regulated DC output voltage VOUT TPS62691 ΔVO 4 %/mA VNOM 1.03×VNOM V 2.5V ≤ VIN ≤ 4.8V, 0mA ≤ IO ≤ 600 mA PFM/PWM operation 0.97×VNOM VNOM 1.03×VNOM V 2.5V ≤ VIN ≤ 5.5V, 0mA ≤ IO ≤ 600 mA PFM/PWM operation 0.97×VNOM VNOM 1.04×VNOM V 2.5V ≤ VIN ≤ 5.5V, 0mA ≤ IO ≤ 600 mA PWM operation 0.97×VNOM VNOM 1.02×VNOM V Load regulation IO = 0mA to 600 mA Start-up time –0.0002 0.98×VNOM VIN = VO + 0.5V (min 2.5V) to 5.5V IO = 200 mA Power-save mode ripple voltage %/V 2.65V ≤ VIN ≤ 4.8V, 0mA ≤ IO ≤ 600 mA PFM/PWM operation Line regulation Feedback input resistance 0.18 TPS6269x 0.12 –0.0003 %/V %/mA 480 kΩ IO = 1mA CO = 4.7μF X5R 6.3V 0402 65 mVPP IO = 1mA CO = 10μF X5R 6.3V 0603 25 mVPP TPS62691 IO = 1mA CO = 10μF X5R 6.3V 0603 22 mVPP TPS62690 IO = 0mA, Time from active EN to VO 250 μs TPS62691 IO = 0mA, Time from active EN to VO 205 μs TPS62690 Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS62690 TPS62691 TPS62690, TPS62691 SLVS965 – MARCH 2011 www.ti.com PIN ASSIGNMENTS TPS6269X TPS6269x CSP-6 (TOP VIEW) TPS6269x CSP-6 (BOTTOM VIEW) MODE A1 A2 VIN VIN A2 A1 MODE SW B1 B2 EN EN B2 B1 SW FB C1 C2 GND GND C2 C1 FB PIN FUNCTIONS PIN I/O DESCRIPTION NAME NO. FB C1 I Output feedback sense input. Connect FB to the converter’s output. VIN A2 I Power supply input. SW B1 I/O EN B2 I This is the switch pin of the converter and is connected to the drain of the internal Power MOSFETs. This is the enable pin of the device. Connecting this pin to ground forces the device into shutdown mode. Pulling this pin to VI enables the device. This pin must not be left floating and must be terminated. This is the mode selection pin of the device. This pin must not be left floating and must be terminated. MODE A1 I MODE = LOW: The device is operating in regulated frequency pulse width modulation mode (PWM) at high-load currents and in pulse frequency modulation mode (PFM) at light load currents. MODE = HIGH: Low-noise mode enabled, regulated frequency PWM operation forced. GND C2 – Ground pin. Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS62690 TPS62691 5 TPS62690, TPS62691 SLVS965 – MARCH 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAM MODE VIN Undervoltage Lockout Bias Supply Bandgap EN VIN Soft-Start Negative Inductor Current Detect V REF = 0.8 V Power Save Mode Switching Logic Thermal Shutdown Current Limit Detect Frequency Control R1 FB Gate Driver R2 SW Anti Shoot-Through VREF + GND PARAMETER MEASUREMENT INFORMATION TPS6269x VIN CI L VIN SW EN FB VOUT CO GND MODE List of components: • L = MURATA LQM21PN1R0NGC • CI = MURATA GRM155R60J475M (4.7μF, 6.3V, 0402, X5R) • CO = MURATA GRM188R60J106ME84 (10μF, 6.3V, 0603, X5R) 6 Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS62690 TPS62691 TPS62690, TPS62691 SLVS965 – MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS Table of Graphs FIGURE η vs Load current Efficiency Peak-to-peak output ripple voltage 3, 4, 5 vs Input voltage 6 vs Load current 7, 8 Combined line/load transient response VO IQ fs rDS(on) 9, 10 Load transient response 11, 12, 13, 14 AC load transient response 15, 16, 17, 18 DC output voltage vs Load current 19, 20 PFM/PWM boundaries vs Input voltage 21 Quiescent current vs Input voltage 22 PWM switching frequency vs Input voltage 23 PFM switching frequency vs Load current 24 P-channel MOSFET rDS(on) vs Input voltage 25 N-channel MOSFET rDS(on) vs Input voltage 26 PWM operation 27 Power-save mode operation 28 Start-up PSRR 29, 30 Power supply rejection ratio vs. Frequency 31 Spurious output noise (PFM mode) vs. Frequency 32 Spurious output noise (PWM mode) vs. Frequency 33 Output spectral noise density vs. Frequency 34 EFFICIENCY vs LOAD CURRENT EFFICIENCY vs LOAD CURRENT 100 100 90 90 80 70 VI = 3.2 V PFM/PWM Operation VI = 4.2 V PFM/PWM Operation Efficiency - % Efficiency - % VI = 3 V Forced PWM 80 VI = 3 V PFM/PWM Operation 70 60 VO = 2.85 V 50 VI = 3.6 V PFM/PWM Operation 40 30 VI = 3.2 V Forced PWM 60 50 VI = 3.6 V Forced PWM 40 VI = 4.2 V Forced PWM 30 20 20 VI = 3.6 V Forced PWM Operation 10 10 VO = 2.85 V 0 0.1 1 10 100 IO - Load Current - mA 1000 0 1 Figure 3. 10 100 IO - Load Current - mA 1000 Figure 4. Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS62690 TPS62691 7 TPS62690, TPS62691 SLVS965 – MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) EFFICIENCY vs LOAD CURRENT EFFICIENCY vs INPUT VOLTAGE 100 100 90 98 80 VI = 2.7 V PFM/PWM Operation Efficiency - % Efficiency - % VI = 3.6 V PFM/PWM Operation 40 30 VI = 4.2 V PFM/PWM Operation IO = 1 mA 84 VO = 2.2 V 0 0.1 1 10 100 IO - Load Current - mA 82 2.9 1000 3.1 3.3 4.5 4.7 Figure 6. PEAK-TO-PEAK OUTPUT RIPPLE VOLTAGE vs LOAD CURRENT PEAK-TO-PEAK OUTPUT RIPPLE VOLTAGE vs LOAD CURRENT 110 40 CO = 10 mF 35 VI = 3.3 V 30 25 VI = 4.5 V 20 15 VI = 3.6 V 5 PFM/PWM Operation 50 100 150 200 250 300 350 400 450 500 IO - Load Current - mA VO - Peak-to-Peak Output Ripple Voltage - mV VO = 2.85 V, VO = 2.85 V, 100 CO = 4.7 mF 90 VI = 3.2 V 80 70 VI = 4.5 V 60 50 40 30 20 VI = 3.6 V 10 PFM/PWM Operation 0 0 50 Figure 7. 8 3.5 3.7 3.9 4.1 4.3 VI - Input Voltage - V Figure 5. 45 VO - Peak-to-Peak Output Ripple Voltage - mV IO = 10 mA 90 86 10 0 0 92 88 20 10 IO = 300 mA 94 VI = 3.2 V PFM/PWM Operation 50 IO = 100 mA 96 70 60 VO = 2.85 V, PFM/PWM Operation 100 150 200 250 IO - Load Current - mA 300 350 Figure 8. Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS62690 TPS62691 TPS62690, TPS62691 SLVS965 – MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) COMBINED LINE/LOAD TRANSIENT RESPONSE COMBINED LINE/LOAD TRANSIENT RESPONSE VO = 2.85 V VO = 2.85 V 10 to 400 mA Load Step 3.3V to 3.9V mA Line Step 10 to 400 mA Load Step 3.15V to 3.75V mA Line Step MODE = Low MODE = Low Figure 9. Figure 10. LOAD TRANSIENT RESPONSE IN PFM/PWM OPERATION LOAD TRANSIENT RESPONSE IN PFM/PWM OPERATION 10 to 400 mA Load Step VI = 3.6 V, VO = 2.85 V 5 to 200 mA Load Step VI = 3.6 V, VO = 2.85 V MODE = Low Figure 11. MODE = Low Figure 12. Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS62690 TPS62691 9 TPS62690, TPS62691 SLVS965 – MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) LOAD TRANSIENT RESPONSE IN PFM/PWM OPERATION 10 to 400 mA Load Step LOAD TRANSIENT RESPONSE IN PFM/PWM OPERATION 10 to 400 mA Load Step VI = 3.15 V, VO = 2.85 V VI = 4.8 V, VO = 2.85 V MODE = Low MODE = Low Figure 13. Figure 14. AC LOAD TRANSIENT RESPONSE AC LOAD TRANSIENT RESPONSE VI = 3.05 V, VO = 2.85 V VI = 3.15 V, VO = 2.85 V 5 to 600 mA Load Sweep 5 to 500 mA Load Sweep MODE = Low Figure 15. 10 MODE = Low Figure 16. Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS62690 TPS62691 TPS62690, TPS62691 SLVS965 – MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) AC LOAD TRANSIENT RESPONSE AC LOAD TRANSIENT RESPONSE VI = 3.6 V, VO = 2.85 V VI = 4.2 V, VO = 2.85 V 5 to 500 mA Load Sweep 5 to 500 mA Load Sweep MODE = Low MODE = Low Figure 17. Figure 18. DC OUTPUT VOLTAGE vs LOAD CURRENT DC OUTPUT VOLTAGE vs LOAD CURRENT 2.907 2.907 VO = 2.85 V, PFM/PWM Operation VO = 2.85 V, PFM/PWM Operation VI = 3.2 V 2.879 VI = 4.5 V VO - Output Voltage - V VO - Output Voltage - V 2.879 2.850 VI = 3.6 V 2.822 2.793 2.765 0.1 10 100 IO - Load Current - mA VI = 3.2 V, TA = 25°C 2.850 VI = 3.1 V, TA = 85°C 2.822 2.793 VI = 2.9 V 1 VI = 2.9 V, TA = 25°C VI = 3.0 V, TA = 85°C 1000 2.765 0.1 Figure 19. 1 10 100 IO - Load Current - mA 1000 Figure 20. Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS62690 TPS62691 11 TPS62690, TPS62691 SLVS965 – MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) QUIESCENT CURRENT vs INPUT VOLTAGE PFM/PWM BOUNDARIES 240 220 VO = 2.85 V Always PWM 200 160 IQ - Quiescent Current - mA IO - Load Current - mA 180 PFM to PWM Mode Change 140 The switching mode changes at these borders 120 100 80 60 40 Always PFM PWM to PFM Mode Change 20 0 3.1 3.2 3.4 3.6 3.8 4.0 4.2 4.4 VI - Input Voltage - V 4.6 4.8 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 2.7 TA = -40°C 3 3.3 3.6 3.9 4.2 VI - Input Voltage - V PWM SWITCHING FREQUENCY vs INPUT VOLTAGE PFM SWITCHING FREQUENCY vs INPUT VOLTAGE 4.8 4.5 4 fS - Switching Frequency - MHz 3.8 3.6 IO = 500 mA 3.4 3.2 IO = 400 mA 3 IO = 300 mA 2.8 IO = 150 mA 2.6 IO = 50 mA 2.4 2.2 2 VO = 2.85 V MODE = High 1.8 3.1 3.3 3.5 3.7 3.9 4.1 VI - Input Voltage - V 4.3 VO = 2.85 V MODE = Low 3.5 VI = 4.5 V VI = 3.6 V 3 2.5 VI = 3.2 V 2 1.5 1 0.5 4.5 0 0 20 40 60 80 100 120 140 160 180 200 220 240 IO - Load Current - mA Figure 23. 12 4.5 Figure 22. 4 fs - Switching Frequency - MHz TA = 25°C Figure 21. 4.2 1.6 2.9 TA = 85°C Figure 24. Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS62690 TPS62691 TPS62690, TPS62691 SLVS965 – MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) P-CHANNEL rDS(ON) vs INPUT VOLTAGE N-CHANNEL rDS(ON) vs INPUT VOLTAGE rDS(on) - Static Drain-Source On-Resistance - mW rDS(on) - Static Drain-Source On-Resistance - mW 275 250 TA = 85°C 225 TA = 25°C 200 TA = -40°C 175 150 125 100 75 2.7 3 3.3 3.6 3.9 4.2 VI - Input Voltage - V 4.5 4.8 250 225 200 TA = 85°C 175 TA = 25°C 150 TA = -40°C 125 100 75 50 25 0 2.7 3 3.3 3.6 3.9 4.2 VI - Input Voltage - V 4.5 Figure 25. Figure 26. PWM OPERATION POWER-SAVE MODE OPERATION VI = 3.6 V, VO = 2.85 V, IO = 150 mA 4.8 VI = 3.6 V, VO = 2.85V, IO = 60 mA MODE = Low Figure 27. MODE = Low Figure 28. Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS62690 TPS62691 13 TPS62690, TPS62691 SLVS965 – MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) START-UP START-UP VI = 3.6 V, VO = 2.85 V, IO = 0 mA VI = 3.6 V, VO = 2.85 V, RL = 39 W MODE = Low Figure 29. Figure 30. POWER SUPPLY REJECTION RATIO vs FREQUENCY SPURIOUS OUTPUT NOISE (PFM MODE) vs FREQUENCY 85 IO = 20 mA 80 PWM Operation 75 70 IO = 250 mA 65 PWM Operation 60 IO = 20 mA 55 PFM Operation 50 45 I = 400 mA O 40 PWM Operation 35 30 25 20 15 VI = 3.6 V 10 VO = 2.85 V 5 0 0.01 0.1 1 10 100 1000 f - Frequency - kHz 10 m 9m Spurious Output Noise (PFM Mode) - V PSRR - Power Supply Rejection Ratio - dB MODE = Low VO = 2.85 V RL = 150 Ω 8m 7m VI = 3.2 V 6m 5m 4m 3m VI = 3.6 V VI = 4.2 V 2m 1m 100 n 0 Figure 31. 14 Span = 500 kHz f - Frequency - MHz 5 Figure 32. Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS62690 TPS62691 TPS62690, TPS62691 SLVS965 – MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) SPURIOUS OUTPUT NOISE (PWM MODE) vs FREQUENCY OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 100 1m Output Spectral Noise Density - µV/Ö Hz Spurious Output Noise (PWM Mode) - V 900 µ VO = 2.85 V RL = 12 Ω 800 µ 700 µ VI = 4.2 V 600 µ 500 µ VI = 3.2 V 400 µ 300 µ 200 µ VI = 3.6 V 100 µ 100 n 0 Span = 2 MHz f - Frequency - MHz 20 VIN = 3.6 V, VOUT = 2.85 V 10 IOUT = 2 mA PFM Operation 1 IOUT = 20 mA PFM Operation 0.1 0.01 0.1 Figure 33. IOUT = 250 mA PWM Operation 1 10 100 f - Frequency - kHz 1000 Figure 34. Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS62690 TPS62691 15 TPS62690, TPS62691 SLVS965 – MARCH 2011 www.ti.com DETAILED DESCRIPTION OPERATION The TPS6269x is a synchronous step-down converter typically operates at a regulated 4-MHz frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents, the TPS6269x converter operates in power-save mode with pulse frequency modulation (PFM). The converter uses a unique frequency locked ring oscillating modulator to achieve best-in-class load and line response and allows the use of tiny inductors and small ceramic input and output capacitors. At the beginning of each switching cycle, the P-channel MOSFET switch is turned on and the inductor current ramps up rising the output voltage until the main comparator trips, then the control logic turns off the switch. One key advantage of the non-linear architecture is that there is no traditional feed-back loop. The loop response to change in VO is essentially instantaneous, which explains the transient response. The absence of a traditional, high-gain compensated linear loop means that the TPS6269x is inherently stable over a range of L and CO. Although this type of operation normally results in a switching frequency that varies with input voltage and load current, an internal frequency lock loop (FLL) holds the switching frequency constant over a large range of operating conditions. Combined with best in class load and line transient response characteristics, the low quiescent current of the device (ca. 19μA) allows to maintain high efficiency at light load, while preserving fast transient response for applications requiring tight output regulation. SWITCHING FREQUENCY The magnitude of the internal ramp, which is generated from the duty cycle, reduces for duty cycles either set of 50%. Thus, there is less overdrive on the main comparator inputs which tends to slow the conversion down. The intrinsic maximum operating frequency of the converter is about 5MHz to 7MHz, which is controlled to circa. 4MHz by a frequency locked loop. When high or low duty cycles are encountered, the loop runs out of range and the conversion frequency falls below 4MHz. The tendency is for the converter to operate more towards a "constant inductor peak current" rather than a "constant frequency". In addition to this behavior which is observed at high duty cycles, it is also noted at low duty cycles. When the converter is required to operate towards the 4MHz nominal at extreme duty cycles, the application can be assisted by decreasing the ratio of inductance (L) to the output capacitor's equivalent serial inductance (ESL). This increases the ESL step seen at the main comparator's feed-back input thus decreasing its propagation delay, hence increasing the switching frequency. POWER-SAVE MODE If the load current decreases, the converter will enter Power Save Mode operation automatically. During power-save mode the converter operates in discontinuous current (DCM) single-pulse PFM mode, which produces low output ripple compared with other PFM architectures. When in power-save mode, the converter resumes its operation when the output voltage trips below the nominal voltage. It ramps up the output voltage with a minimum of one pulse and goes into power-save mode when the inductor current has returned to a zero steady state. The PFM on-time varies inversely proportional to the input voltage and proportional to the output voltage giving the regulated switching frequency when in steady-state. PFM mode is left and PWM operation is entered as the output current can no longer be supported in PFM mode. As a consequence, the DC output voltage is typically positioned ca. 0.5% above the nominal output voltage and the transition between PFM and PWM is seamless. 16 Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS62690 TPS62691 TPS62690, TPS62691 SLVS965 – MARCH 2011 www.ti.com PFM Mode at Light Load PFM Ripple Nominal DC Output Voltage PWM Mode at Heavy Load Figure 35. Operation in PFM Mode and Transfer to PWM Mode MODE SELECTION The MODE pin allows to select the operating mode of the device. Connecting this pin to GND enables the automatic PWM and power-save mode operation. The converter operates in regulated frequency PWM mode at moderate to heavy loads and in the PFM mode during light loads, which maintains high efficiency over a wide load current range. Pulling the MODE pin high forces the converter to operate in the PWM mode even at light load currents. The advantage is that the converter modulates its switching frequency according to a spread spectrum PWM modulation technique allowing simple filtering of the switching harmonics in noise-sensitive applications. In this mode, the efficiency is lower compared to the power-save mode during light loads. For additional flexibility, it is possible to switch from power-save mode to PWM mode during operation. This allows efficient power management by adjusting the operation of the converter to the specific system requirements. LOW DROPOUT, 100% DUTY CYCLE OPERATION The device starts to enter 100% duty cycle mode once input and output voltage come close together. In order to maintain the output voltage, the P-channel MOSFET is turned on 100% for one or more cycles. With further decreasing VIN the high-side switch is constantly turned on, thereby providing a low input-to-output voltage difference. This is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage to maintain regulation depends on the load current and output voltage, and can be calculated as: VINmin = VOUT max + IOUT max ´ RDS(on)max + RL ( ) (1) With: IOUTmax = Maximum output current, plus inductor ripple current. RDS(on)max = Maximum P-channel MOSFET RDS(on). RL = Inductor DC resistance. VOUTmax = Nominal output voltage, plus maximum output voltage tolerance. Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS62690 TPS62691 17 TPS62690, TPS62691 SLVS965 – MARCH 2011 www.ti.com ENABLE The TPS6269x device starts operation when EN is set high and starts up with the soft start as previously described. For proper operation, the EN pin must be terminated and must not be left floating. Pulling the EN pin low forces the device into shutdown, with a shutdown quiescent current of typically 0.2μA. In this mode, the P and N-channel MOSFETs are turned off, the internal resistor feedback divider is disconnected, and the entire internal-control circuitry is switched off. The TPS6269x device can actively discharge the output capacitor when it turns off. The integrated discharge resistor has a typical resistance of 100 Ω. The required time to discharge the output capacitor at the output node depends on load current and the output capacitance value. SOFT START The TPS6269x has an internal soft-start circuit that limits the inrush current during start-up. This limits input voltage drops when a battery or a high-impedance power source is connected to the input of the converter. The soft-start system progressively increases the on-time from a minimum pulse-width of 35ns as a function of the output voltage. This mode of operation continues for c.a. 150μs after enable. Should the output voltage not have reached its target value by this time, such as a heavy load, the soft-start transitions to a second mode of operation. The converter then operates in a current limit mode, specifically the P-MOS current limit is set to half the nominal limit, and the N-channel MOSFET remains on until the inductor current has reset. After a further 150 μs, the device ramps up to the full current limit operation if the output voltage has risen above 0.5V (approximately). Therefore, the start-up time mainly depends on the output capacitor and load current. UNDERVOLTAGE LOCKOUT The undervoltage lockout circuit prevents the device from misoperation at low input voltages. It prevents the converter from turning on the switch or rectifier MOSFET under undefined conditions. The TPS6269x device have a UVLO threshold set to 2.05V (typical). Fully functional operation is permitted down to 2.1V input voltage. SHORT-CIRCUIT PROTECTION The TPS6269x integrates a P-channel MOSFET current limit to protect the device against heavy load or short circuits. When the current in the P-channel MOSFET reaches its current limit, the P-channel MOSFET is turned off and the N-channel MOSFET is turned on. The regulator continues to limit the current on a cycle-by-cycle basis. As soon as the output voltage falls below ca. 0.4V, the converter current limit is reduced to half of the nominal value. Because the short-circuit protection is enabled during start-up, the device does not deliver more than half of its nominal current limit until the output voltage exceeds approximately 0.5V. This needs to be considered when a load acting as a current sink is connected to the output of the converter. THERMAL SHUTDOWN As soon as the junction temperature, TJ, exceeds typically 140°C, the device goes into thermal shutdown. In this mode, the P- and N-channel MOSFETs are turned off. The device continues its operation when the junction temperature again falls below typically 130°C. 18 Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS62690 TPS62691 TPS62690, TPS62691 SLVS965 – MARCH 2011 www.ti.com APPLICATION INFORMATION INDUCTOR SELECTION The TPS6269x series of step-down converters have been optimized to operate with an effective inductance value in the range of 0.5μH to 1.8μH and with output capacitors in the range of 4.7μF to 10μF. The internal compensation is optimized to operate with an output filter of L = 1μH and CO = 4.7μF. Larger or smaller inductor values can be used to optimize the performance of the device for specific operation conditions. For more details, see the CHECKING LOOP STABILITY section. The inductor value affects its peak-to-peak ripple current, the PWM-to-PFM transition point, the output voltage ripple and the efficiency. The selected inductor has to be rated for its dc resistance and saturation current. The inductor ripple current (ΔIL) decreases with higher inductance and increases with higher VI or VO. V V *V DI I O DI + O DI +I ) L L L(MAX) O(MAX) 2 V L ƒ sw I with: fSW = switching frequency (4 MHz typical) L = inductor value ΔIL = peak-to-peak inductor ripple current IL(MAX) = maximum inductor current (2) In high-frequency converter applications, the efficiency is essentially affected by the inductor AC resistance (i.e. quality factor) and to a smaller extent by the inductor DCR value. To achieve high efficiency operation, care should be taken in selecting inductors featuring a quality factor above 25 at the switching frequency. Increasing the inductor value produces lower RMS currents, but degrades transient response. For a given physical inductor size, increased inductance usually results in an inductor with lower saturation current. The total losses of the coil consist of both the losses in the DC resistance (DC)) and the following frequency-dependent components: • The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies) • Additional losses in the conductor from the skin effect (current displacement at high frequencies) • Magnetic field losses of the neighboring windings (proximity effect) • Radiation losses The following inductor series from different suppliers have been used with the TPS6269x converters. Table 1. List of Inductors MANUFACTURER MURATA SERIES DIMENSIONS (in mm) LQM21PN1R0NGC 2.0 x 1.2 x 1.0 max. height LQM21PN1R5MC0 2.0 x 1.2 x 0.55 max. height FDK MIPS2012D1R0-X2 2.0 x 1.2 x 1.0 max. height TAIYO YUDEN NM2012N1R0M 2.0 x 1.2 x 1.0 max. height TOKO MDT2012-CH1R0A 2.0 x 1.2 x 1.0 max. height Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS62690 TPS62691 19 TPS62690, TPS62691 SLVS965 – MARCH 2011 www.ti.com OUTPUT CAPACITOR SELECTION The advanced fast-response voltage mode control scheme of the TPS6269x allows the use of tiny ceramic capacitors. Ceramic capacitors with low ESR values have the lowest output voltage ripple and are recommended. For best performance, the device should be operated with a minimum effective output capacitance of 1μF. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric capacitors, aside from their wide variation in capacitance over temperature, become resistive at high frequencies. At nominal load current, the device operates in PWM mode and the overall output voltage ripple is the sum of the voltage step caused by the output capacitor ESL and the ripple current flowing through the output capacitor impedance. At light loads, the output capacitor limits the output ripple voltage and provides holdup during large load transitions. A 4.7μF or 10μF ceramic capacitor typically provides sufficient bulk capacitance to stabilize the output during large load transitions. The typical output voltage ripple is ca. 0.5% to 1.5% of the nominal output voltage VO. The output voltage ripple during PFM mode operation can be kept small. The PFM pulse is time controlled, which allows to modify the charge transferred to the output capacitor by the value of the inductor. The resulting PFM output voltage ripple and PFM frequency depend in first order on the size of the output capacitor and the inductor value. The PFM frequency decreases with smaller inductor values and increases with larger once. Increasing the output capacitor value and the effective inductance will minimize the output ripple voltage. INPUT CAPACITOR SELECTION Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required to prevent large voltage transients that can cause misbehavior of the device or interferences with other circuits in the system. For most applications, a 2.2 or 4.7-μF capacitor is sufficient. If the application exhibits a noisy or erratic switching frequency, the remedy should be found by experimenting with the value of the input capacitor. Take care when using only ceramic input capacitors. When a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even damage the part. Additional "bulk" capacitance (electrolytic or tantalum) should in this circumstance be placed between CI and the power source lead to reduce ringing than can occur between the inductance of the power source leads and CI. CHECKING LOOP STABILITY The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals: • Switching node, SW • Inductor current, IL • Output ripple voltage, VO(AC) These are the basic signals that need to be measured when evaluating a switching converter. When the switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the regulation loop may be unstable. This is often a result of board layout and/or L-C combination. As a next step in the evaluation of the regulation loop, the load transient response is tested. The time between the application of the load transient and the turn on of the P-channel MOSFET, the output capacitor must supply all of the current required by the load. VO immediately shifts by an amount equal to ΔI(LOAD) x ESR, where ESR is the effective series resistance of CO. ΔI(LOAD) begins to charge or discharge CO generating a feedback error signal used by the regulator to return VO to its steady-state value. The results are most easily interpreted when the device operates in PWM mode. During this recovery time, VO can be monitored for settling time, overshoot or ringing that helps judge the converter’s stability. Without any ringing, the loop has usually more than 45° of phase margin. Because the damping factor of the circuitry is directly related to several resistive parameters (e.g., MOSFET rDS(on)) that are temperature dependant, the loop stability analysis has to be done over the input voltage range, load current range, and temperature range. 20 Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS62690 TPS62691 TPS62690, TPS62691 SLVS965 – MARCH 2011 www.ti.com LAYOUT CONSIDERATIONS As for all switching power supplies, the layout is an important step in the design. High-speed operation of the TPS6269x devices demand careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If the layout is not carefully done, the regulator could show poor line and/or load regulation, stability and switching frequency issues as well as EMI problems. It is critical to provide a low inductance, impedance ground path. Therefore, use wide and short traces for the main current paths. The input capacitor should be placed as close as possible to the IC pins as well as the inductor and output capacitor. In order to get an optimum ESL step, the output voltage feedback point (FB) should be taken in the output capacitor path, approximately 1mm away for it. The feed-back line should be routed away from noisy components and traces (e.g. SW line). MODE CI L VIN ENABLE CO GND VOUT Figure 36. Suggested Layout (Top) THERMAL INFORMATION Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependant issues such as thermal coupling, airflow, added heat sinks, and convection surfaces, and the presence of other heat-generating components, affect the power-dissipation limits of a given component. Three basic approaches for enhancing thermal performance are listed below: • Improving the power dissipation capability of the PCB design • Improving the thermal coupling of the component to the PCB • Introducing airflow into the system The maximum recommended junction temperature (TJ) of the TPS6269x devices is 105°C. The thermal resistance of the 6-pin CSP package (YFF-6) is RθJA = 125°C/W. Regulator operation is specified to a maximum steady-state ambient temperature TA of 85°C. Therefore, the maximum power dissipation is about 160 mW. PD(MAX) = TJ(MAX) - TA RqJA = 105°C - 85°C = 160mW 125°C/W (3) Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS62690 TPS62691 21 TPS62690, TPS62691 SLVS965 – MARCH 2011 www.ti.com PACKAGE SUMMARY CHIP SCALE PACKAGE (BOTTOM VIEW) D A2 A1 B2 B1 CHIP SCALE PACKAGE (TOP VIEW) YMDS CC A1 C1 C2 Code: E • YM — Year Month date Code • D — Day of laser mark • S — Assembly site code • CC— Chip code CHIP SCALE PACKAGE DIMENSIONS The TPS6269x device is available in an 6-bump chip scale package (YFF, NanoFree™). The package dimensions are given as: 22 D E Max = 1.33 mm Max = 0.929 mm Min = 1.27 mm Min = 0.923 mm Submit Documentation Feedback © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS62690 TPS62691 PACKAGE OPTION ADDENDUM www.ti.com 4-Apr-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TPS62690YFFR ACTIVE DSBGA YFF 6 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM TPS62690YFFT ACTIVE DSBGA YFF 6 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TPS62690YFFR DSBGA YFF 6 3000 180.0 8.4 TPS62690YFFT DSBGA YFF 6 250 180.0 8.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1.07 1.42 0.74 4.0 8.0 Q1 1.07 1.42 0.74 4.0 8.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS62690YFFR DSBGA YFF 6 3000 190.5 212.7 31.8 TPS62690YFFT DSBGA YFF 6 250 190.5 212.7 31.8 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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