1
TC820
3-3/4 DIGIT A/D CONVERTER WITH FREQUENCY
COUNTER AND LOGIC PROBE
2
FEATURES
GENERAL DESCRIPTION
■ Multiple Analog Measurement System
— Digit A/D Converter
— Frequency Counter
— Logic Probe
■ Low Noise A/D Converter:
— Differential Inputs, (1pA Bias Current)
— On-Chip 50PPM/°C Voltage Reference
■ Frequency Counter:
— 4Mhz Maximum Input Frequency
— Auto-ranging Over Four Decade Range
■ Logic Probe:
— Two LCD Annunciators
— Buzzer Driver
■ 3-3/4 Digit Display with Overrange Indicator
■ LCD Display Driver with Built-in Contrast Control
■ Data Hold Input for Comparison Measurements
■ Low Battery Detect with LCD Annunciator
■ Underrange and Overrange Outputs
■ On-Chip Buzzer Driver with Control Input
■ 44-Pin Plastic Flat Pack or PLCC or 40-Pin Plastic
DIP Packages
The TC820 is a 3-3/4 digit, multi-measurement system
especially suited for use in portable instruments. It integrates a dual slope A/D converter, auto-ranging frequency
counter and logic probe into a single 44-pin surface mount
or 40-pin through hole package. The TC820 operates from
a single 9V input voltage (battery) and features a built-in
battery low flag. Function and decimal point selection are
accomplished with simple logic inputs designed for direct
connection to an external microcontroller or rotary switch.
Ease of use, low power operation and high functional
integration make the TC820 desirable in a variety of analog
measurement applications.
3
4
ORDERING INFORMATION
Temperature
Range
Part No.
Resolution
Package
TC820CKW
3-3/4 Digits
TC820CLW
3-3/4 Digits
TC820CPL
3-3/4 Digits
44-Pin Plastic
0°C to +70°C
Quad Flat Package
44-Pin Plastic
0°C to +70°C
Leadless Chip
Carrier
40-Pin Plastic DIP 0°C to +70°C
5
FUNCTIONAL BLOCK DIAGRAM
TRIPLEX LCD
LOGIC HIGH
OVERRANGE
PKHOLD
LOW BATT
LOGIC LOW
6
ANNUNCIATOR DRIVE
EOC
UNDERRANGE
OVERRANGE
ANALOG
INPUT
FULL-SCALE
SELECT
FREQUENCY
INPUT
LOGIC
PROBE
INPUT
LOW DRIFT VOLTAGE
DIFFERENTIAL
REFERENCE
CLOCK
OSCILLATOR
3-3/4 DIGIT
A/D CONVERTER
TRIPLE LCD
DRIVERS
DECIMAL
POINT
DRIVERS
PEAK HOLD
COMPARATOR
DECIMAL
POINT
SELECT
7
ANALOG GND
AUTORANGING
FREQUENCY
COUNTER
LOGIC
PROBE
LOW
BATTERY
DETECT
BUZZER
DRIVER
BUZZER
CONTROL
TC820
FUNCTION
SELECT
TO LCD
AND BUZZER
VOLTS
FREQUENCY
LOGIC
FUNCTION
SELECT
DIGITAL GROUND
+
PEAK
HOLD
8
9V
TC820-10 10/17/96
TELCOM SEMICONDUCTOR, INC.
3-149
3-3/4 DIGIT A/D CONVERTER WITH
FREQUENCY AND LOGIC PROBE
TC820
GENERAL DESCRIPTION
The TC820 is a 3-3/4 digit measurement system combining an integrating analog-to-digital converter, frequency
counter, and logic level tester in a single package. The
TC820 supersedes the TC7106 in new designs by improving performance and reducing system cost. The TC820
adds features that are difficult, expensive, or impossible to
provide with older A/D converters (see the competitive
evaluation). The high level of integration permits TC820based instruments to deliver higher performance and more
features, while actually reducing parts count. Fabricated in
low-power CMOS, the TC820 directly drives a 3-3/4 digit
(3999 maximum) LCD.
With a maximum range of 3999 counts, the TC820
provides 10 times greater resolution in the 200mV to 400mV
range than traditional 3-1/2 digit meters. An auto-zero cycle
guarantees a zero reading with a 0V input. CMOS processing reduces analog input bias current to only 1pA. Rollover
error (the difference in readings for equal magnitude but
opposite polarity input signals) is less than ±1 count. Differential reference inputs permit ratiometric measurements for
ohms or bridge transducer applications.
The TC820's frequency counter option simplifies design
of an instrument well-suited to both analog and digital
troubleshooting: voltage, current, and resistance measurements, plus precise frequency measurements to 4MHz
(higher frequencies can be measured with an external
prescaler), and a simple logic probe. The frequency counter
will automatically adjust its range to match the input frequency, over a four-decade range.
Two logic level measurement inputs permit a TC820based meter to function as a logic probe. When combined
with external level shifters, the TC820 will display logic levels
on the LCD and also turn on a piezoelectric buzzer when the
measured logic level is low.
Other TC820 features simplify instrument design and
reduce parts count. On-chip decimal point drivers are included, as is a low battery detection annunciator. A piezoelectric buzzer can be controlled with an external switch or
by the logic probe inputs. Two oscillator options are provided: A crystal can be used if high accuracy frequency
measurements are desired, or a simple RC option can be
used for low-end instruments.
3-150
A "peak reading hold" input allows the TC820 to retain
the highest A/D or frequency reading. This feature is useful
in measuring motor starting current, maximum temperature, and similar applications.
A family of instruments can be created with the TC820.
No additional design effort is required to create instruments
with 3-3/4 digit resolution.
The TC820 operates from a single 9V battery, with
typical power of 10 mW. Packages include a 40-pin plastic
DIP, 44-pin plastic flat package, and 44-pin PLCC.
COMPETITIVE EVALUATION
Features Comparison
3-3/4 Digit Resolution
Auto-Ranging Frequency Counter
Logic Probe
Decimal Point Drive
Peak Reading Hold
(Frequency or Voltage)
Display Hold
Simple 10:1 Range Change
Buzzer Drive
Low Battery Detection
With Annunciator
Overrange Detection
With Annunciator
Low Drift Reference
Underrange/Overrange
Logic Output
Input Overload Display
LCD Annunciator Driver
LCD Drive Type
LCD Pin Connections
LCD Elements
TC820
7106
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
Yes
Yes
Yes
Yes
No
No
No
No
Yes
No
Yes
Yes
No
No
"OL"
Yes
Triplexed
15
36
"1"
No
Direct
24
23
TELCOM SEMICONDUCTOR, INC.
3-3/4 DIGIT A/D CONVERTER WITH
FREQUENCY AND LOGIC PROBE
1
TC820
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (VDD to GND) .....................................15V
Analog Input Voltage (Either Input) (Note 1) .... VDD to VSS
Reference Input Voltage (Either Input) ............. VDD to VSS
Digital Inputs ............................................... VDD to DGND
VDISP ............................................. VDD to (DGND – 0.3V)
Package Power Dissipation (TA ≤ 70°C) (Note 2)
40-Pin Plastic DIP ............................................. 1.23W
44-Pin PLCC .....................................................1.23W
44-Pin Plastic Flat Package .............................. 1.00W
Operating Temperature Range
"C" Devices ............................................ 0°C to +70°C
"E" Devices ....................................... – 40°C to +85°C
Storage Temperature Range ................ – 65°C to +150°C
Lead Temperature (Soldering, 10 sec) ................... 300°C
*Static-sensitive devices. Unused devices should be stored in conductive
material to protect against static discharge and static fields. Stresses above
those listed under Absolute Maximum Ratings may cause permanent
damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
NOTES: 1. Input voltages may exceed the supply voltages provided that
input current is limited to ±100µA. Current above this value
may result in invalid display readings but will not destroy the
device if limited to ±1mA.
2. Dissipation ratings assume device is mounted with all leads
soldered to printed circuit board.
ELECTRICAL CHARACTERISTICS: VS = 9V, TA = 25°C, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Zero Input Reading
VIN = 0V
Full Scale = 400 mV
VIN = ±390mV
Full-Scale = 400mV
Full-Scale = 400mV
– 000
±000
+000
–1
±0.2
+1
Digital
Reading
Counts
–1
±0.2
+1
Count
VIN = VREF, TC820
VCM = ±1V, VIN = 0V
Full-Scale = 400mV
(VFS = 200 mV)
Input High, Input Low
1999
—
1999/2000
50
2000
—
Digital
µV/V
VSS + 1.5
—
VDD– 1
V
—
15
—
µV
—
—
—
1
20
100
10
—
—
pA
3.15
3.3
3.45
V
—
—
35
50
50
—
ppm/°C
—
0.2
1
—
µV/°C
—
—
1
5
5
—
ppm/°C
—
4.25
1
4.7
1.5
5.3
mA
V
RE
Roll-Over Error
NL
Nonlinearity (Maximum
Deviation From Best
Straight Line Fit)
Ratiometric Reading
Common-Mode Rejection
Ratio
CMRR
VCMR
eN
IIN
Common-Mode Voltage
Range
Noise (P-P Value Not
Exceeded 95% of Time)
Input Leakage Current
VCOM
Analog Common Voltage
VCTC
Common Voltage
Temperature Coefficient
TCZS
TCFS
IS
Zero Reading Drift
Scale Factor
Temperature Coefficient
Supply Current
Peak-to-Peak Backplane
Drive Voltage
VIN = 0V
Full-Scale = 400mV
VIN = 0V
TA = 25°C
0°C ≤ TA ≤ +70°C
– 40°C ≤ TA ≤ +85°C
25 kΩ Between Common and VDD
(VSS – VCOM)
25 kΩ Between Common and VDD
0°C ≤ TA ≤ +70°C
– 40°C ≤ TA ≤ +85°C
VIN = 0V
0°C ≤ TA ≤ +70°C
– 40°C ≤ TA ≤ +85°C
VIN = 399mV
0°C ≤ TA ≤ +70°C
– 40°C ≤ TA ≤ +85°C
Ext Ref = 0 ppm/°C
VIN = 0V
VS = 9V
VDISP = DGND
TELCOM SEMICONDUCTOR, INC.
2
3
4
5
6
3-151
7
8
3-3/4 A/D CONVERTER WITH
FREQUENCY COUNTER
AND LOGIC PROBE
TC820
ELECTRICAL CHARACTERISTICS (Cont.)
Symbol
VIL
VIH
VOL
VOL
Parameter
Test Conditions
Min
Typ
Max
Units
Buzzer Frequency
Counter Timebase Period
Low Battery Flag Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage,
UR, OR Outputs
Output High Voltage,
UR, OR Outputs
Control Pin
Pull-Down Current
fOSC = 40kHz
fOSC = 40kHz
VDD to VSS
IL = 50µA
—
—
6.7
—
VDD – 1.5
—
5
1
7
—
—
—
—
—
7.3
DGND + 1.5
—
DGND + 0.4
kHz
Second
V
V
V
V
IL = 50µA
VDD – 1.5
—
—
V
VIN = VDD
—
5
—
µA
PIN DESCRIPTION
Pin No.
(40-Pin
Package)
Pin No.
(44-Pin Flat
Package)
Symbol
1
40
L-E4
2
3
4
5
6
7
8
9
10
11
12
13
14
15
—
41
42
43
44
1
2
3
4
5
6
7
8
9
10
11
AGD4
BC4P3
HFE3
AGD3
BC3P2
OFE2
AGD2
BC2P1
PKFE1
AGD1
BC1BT
BP3
BP2
BP1
VDISP
16
17
12
13
DGND
ANNUNC
18
14
LOGIC
19
15
RANGE/
FREQ
3-152
Description
LCD segment driver for L ("logic LOW"), polarity, and "e" segment of most
significant digit (MSD).
LCD segment drive for "a," "g," and "d" segments of MSD.
LCD segment drive for "b" and "c" segments of MSD and decimal point 3.
LCD segment drive for H ("logic HIGH"), and "f" and "e" segments of third LSD.
LCD segment drive for "a," "g," and "d" segments of third LSD.
LCD segment drive for "b" and "c" segments of third LSD and decimal point 2.
LCD segment drive for "overrange," and "f" and "e" segments of second LSD.
LCD segment drive for "a," "g," and "d" segments of second LSD.
LCD segment drive for "b " and "c" segments of second LSD and decimal point 1.
LCD segment drive for "hold peak reading," and "f" and "e" segments of LSD.
LCD segment drive for "a," "g," and "d" segments of LSD.
LCD segment drive for "b" and "c" segments of LSD and "low battery."
LCD backplane #3.
LCD backplane #2.
LCD backplane #1.
Sets peak LCD drive signal: VPEAK = (VDD ) –VDISP. VDISP may also be used to
compensate for temperature variation of LCD crystal threshold voltage.
Internal logic digital ground, the logic "0" level. Nominally 4.7V below VDD.
Square-wave output at the backplane frequency, synchronized to BP1. ANNUNC
can be used to control display annunciators. Connecting an LCD segment to
ANNUNC turns it on; connecting it to its backplane turns it off.
Logic mode control input. When connected to VDD, the converter is in logic mode.
The LCD displays "OL" and the decimal point inputs control the HIGH and LOW
annunciators. When the "low" annunciator is on, the buzzer will also be on. When
unconnected or connected to DGND, the TC820 is in the voltage/frequency
measurement mode. This pin has a 5µA internal pull-down to DGND.
Dual-purpose input. In range mode, when connected to VDD, the integration time
will be 200 counts instead of 2000 counts and the LCD will display the analog input
divided by 10. (See text for limitation with TC820.) In frequency mode, this pin is the
frequency input. A digital signal applied to this pin will be measured with a 1-second
time base. There is an internal 5µA pull-down to DGND.
TELCOM SEMICONDUCTOR, INC.
3-3/4 A/D CONVERTER WITH
FREQUENCY COUNTER
AND LOGIC PROBE
1
TC820
PIN DESCRIPTION
2
Pin No.
(40-Pin
Package)
Pin No.
(44-Pin Flat
Package)
Symbol
Description
20
16
DP0/LO
Dual-purpose input. Decimal point select input for voltage measurements. In logic
mode, connecting this pin to VDD will turn on the "low" LCD segment. There is an
internal 5µA pull-down to DGND in volts mode only. Decimal point logic:
DP1
DP0
Decimal Point Selected
0
0
None
0
1
DP1
1
0
DP2
1
1
DP3
Dual-purpose input. Decimal point select input for voltage measurements. In logic
mode, connecting this pin to VDD will turn on the "high" LCD segment. There is an
internal 5µA pull-down to DGND in volts mode only.
Buzzer output. Audio frequency, 5kHz, output which drives a piezoelectric buzzer.
Buzzer control input. Connecting BUZIN to VDD turns the buzzer on. BUZIN is
logically ORed (internally) with the "logic level low" input. There is an internal 5µA
pull-down to DGND.
Voltage or frequency measurement select input. When unconnected, or connected
to DGND, the A/D converter function is active. When connected to VDD, the
frequency counter function is active. This pin has an internal 5µA pull-down
to DGND.
Peak hold input. When connected to VDD, the converter will only update the display
if a new conversion value is greater than the preceding value. Thus, the peak
reading will be stored and held indefinitely. When unconnected, or connected to
DGND, the converter will operate normally. This pin has an internal 5µA pull-down
to DGND.
Underrange output. This output will be HIGH when the digital reading is 380 counts
or less.
Overrange output. This output will be HIGH when the analog signal input is greater
than full scale. The LCD will display "OL" when the input is overranged.
Negative supply connection. Connect to negative terminal of 9V battery.
Analog circuit ground reference point. Nominally 3.3V below VDD.
Positive connection for reference capacitor.
Negative connection for reference capacitor.
High differential reference input connection.
Low differential reference input connection.
Low analog input signal connection.
High analog input signal connection.
Buffer output. Connect to integration resistor.
Auto-zero capacitor connection.
Integrator output. Connect to integration capacitor.
Bidirectional pin. Pulses low (i.e., from VDD to DGND) at the end of each
conversion. If connected to VDD, conversions will continue, but the display is not
updated.
Crystal oscillator (input) connection.
Crystal oscillator (output) connection.
RC oscillator connection.
Positive power supply connection, typically 9V.
21
17
DP1/HI
22
23
18
19
BUZOUT
BUZIN
24
20
FREQ/
VOLTS
25
21
PKHOLD
22
UR
23
OR
26
27
28
29
30
31
32
33
34
35
36
24
25
26
27
28
29
30
31
32
33
34
35
VSS
COM
+
CREF
–
CREF
+
VREF
–
VREF
–
VIN
+
VIN
VBUFF
CAZ
VINT
EOC/
HOLD
37
38
39
40
36
37
38
39
OSC1
OSC2
OSC3
VDD
TELCOM SEMICONDUCTOR, INC.
3-153
3
4
5
6
7
8
3-3/4 A/D CONVERTER WITH
FREQUENCY COUNTER
AND LOGIC PROBE
TC820
L-E4
VDD
OSC3
OSC2
OSC1
EOC/HOLD
VINT
5
BC4P3
HFE3
6
AGD4
AGD3
PIN CONFIGURATIONS
4
3
2
1
44
43
42
41
40
BC3P2
7
39 C
AZ
OFE2
8
38 VBUFF
AGD2
9
37 VIN
BC2P1 10
36 V IN
PKFE1 11
35 VREF
AGD1 12
V+
+
–
–
34
TC820CLW
REF
–
BP1BT 13
33 CREF
BP3 14
32 CREF
+
SEGMENTS L-E4
1
40 VDD
SEGMENTS AGD4
2
39
OSC3
BP2 15
31 COM
SEGMENTS BC4P3
3
38 OSC2
BP1 16
30 VSS
V DISP 17
DGND 16
ANNUNC 17
LOGIC 18
RANGE/FREQ 19
DP0/LO 20
25 PK HOLD
24 FREQ/VOLTS
23 BUZ IN
22 BUZ OUT
21 DP1/HI
42
41 40 39
38
37
36
35
34
UR
V INT
PK HOLD
EOC/HOLD
FREQ/VOLTS
OSC1
28
44 43
BUZ IN
26 VSS
BP3 13
27
OSC2
BP1 15
SEGMENTS BC1BT 12
TC820CPL
BUZ OUT
BP2 14
SEGMENTS AGD1 11
26
OSC3
9
25
DP1/HI
SEGMENTS BCP1
SEGMENTS PKFE1 10
24
VDD
8
23
DP0/LO
SEGMENTS AGD2
34 V BUFF
+
33 V IN
–
32 V IN
–
31 V REF
+
30 V REF
–
29 CREF
+
28 CREF
27 COM
21 22
RANGE/FREQ
7
20
L–E4
SEGMENTS OFE2
18 19
AGD4
35 CAZ
LOGIC
6
BC4P3
SEGMENTS BC3P2
29 OR
ANNUNC
36 V INT
HFE3
5
DGND
4
SEGMENTS AGD3
AGD3
SEGMENTS HFE3
37 OSC1
33 C
AZ
BC3P2 1
OFE2 2
32 VBUFF
AGD2 3
31 VIN
BCP2P1 4
30 VIN
+
–
–
29 VREF
PKFE1 5
+
AGD1 6
28 VREF
TC820CKW
–
BP1BT 7
27 CREF
BP3 8
26 CREF
BP2 9
25 COM
BP1 10
24 V
SS
+
23 OR
3-154
20
21 22
FREQ/VOLTS
PK HOLD
UR
19
BUZ IN
RANGE/FREQ
18
BUZ OUT
LOGIC
17
DP1/HI
15 16
DP0/LO
14
DGND
12 13
ANNUNC
V DISP 11
TELCOM SEMICONDUCTOR, INC.
3-3/4 A/D CONVERTER WITH
FREQUENCY COUNTER
AND LOGIC PROBE
1
TC820
FUNCTIONAL BLOCK DIAGRAM
2
+
CREF
–
CREF VBUFF
CAZ
VINT OSC1
OSC2
OSC3
BUZ IN
LOGIC
LOW
+
VIN
–
VIN
+
VREF
–
VREF
COMMON
VDD
BUZZER
DRIVER
÷8
÷2
FREQUENCY COUNTER INPUT
A/D COUNTER SELECT
RANGE
SEL
A/D COUNTER
B
(3999 COUNTS)
A
LOW
TO LCD
BATT
DETECT
A/D CONTROL
TC820
RANGE/
FREQ
COMPARATOR
A>B
DEINT
4
UNDERRANGE
OVERRANGE
EOC
RANGE
DISPLAY
LATCH
LOGIC
LOW
RANGE/FREQ
INPUT
LOW BATT
LOGIC
DP0/LO
TRIPLEX
DRIVERS
VSS
DP1/HI
15
DGND UR OR
EOC/
HOLD
3
FREQ/
VOLTS
PEAK
HOLD
ANNUNC VDISP
5
SEG0 • • • BP3
6
7
8
TELCOM SEMICONDUCTOR, INC.
3-155
3-3/4 A/D CONVERTER WITH
FREQUENCY COUNTER
AND LOGIC PROBE
TC820
LOGIC HIGH
OVERRANGE
PKHOLD
LOW BATT
LOGIC LOW
VDD
NC
S1a
VIN
S1b
GND
FREQ
FREQ/
24
VOLTS
TO SWITCH
S2
18
LOGIC
100kΩ
33
+
VIN
0.01µF
32 V –
IN
16
DGND
CHANGE
COM
RANGE
S1c
ANNUNC
VDD
22kΩ
17
L-E4
AGD4
BC4P3
HFE3
AGD3
BC3P2
OFE2
AGD2
BC2P1
PK FE1
AGD1
BC1BT
BP3
BP2
BP1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
COM 27
VDD 40
VDD
+
9V
TC820
VSS
26 –
+
1µF
DGND
PIEZO
BUZZER
DGND
BUZ OUT 22
S1d
20
DP0/LO
23
VDD
PK HOLD 25
+
–
VINT CREF
CREF
VDD
LOGIC
BUZ IN
S1e
21 DP1/HI
OSC1
DGND
OSC2 OSC3 VBUFF CAZ
37
38
DP3
TO
SWITCH
S1a
VREF = 200mV
–
VREF 31
VDD
19 RANGE/FREQ
VDD
2kΩ
+
VREF 30
S2
DP2
40kHz
34
35
100
kΩ
0.47
µF
28
36
0.2
µF
29
0.1
µF
NOTE:
Pin numbers are for
40-pin package.
NC
DP1
NO DP
39
470
kΩ
22M Ω
Figure 1. Typical Operating Circuit
GENERAL THEORY OF OPERATION
Dual-Slope Conversion Principles
ANALOG
INPUT
SIGNAL
The TC820 analog-to-digital converter operates on the
principle of dual-slope integration. An understanding of the
dual-slope conversion technique will aid the user in following the detailed TC820 theory of operation following this
section. A conventional dual-slope converter measurement
cycle has two distinct phases:
Referring to Figure 2, the unknown input signal to be
converted is integrated from zero for a fixed time period
(t INT), measured by counting clock pulses. A constant
reference voltage of the opposite polarity is then integrated
until the integrator output voltage returns to zero. The
reference integration (deintegration) time (TDEINT) is then
directly proportional to the unknown input voltage (VIN).
In a simple dual-slope converter, a complete conversion requires the integrator output to "ramp-up" from zero
and "ramp-down" back to zero. A simple mathematical
equation relates the input signal, reference voltage, and
integration time:
3-156
R
INTEGRATOR
–
+
COMPARATOR
–
+
SWITCH
DRIVER
REF
VOLTAGE
PHASE
CONTROL
CONTROL LOGIC
POLARITY CONTROL
DISPLAY
INTEGRATOR
OUTPUT
(1) Input Signal Integration
(2) Reference Voltage Integration (Deintegration)
C
FIXED
SIGNAL
INTEGRATE
TIME
CLOCK
COUNTER
VIN = VFULL SCALE
VIN = 1.2 VFULL SCALE
VARIABLE
REFERENCE
INTEGRATE
TIME
Figure 2. Basic Dual-Slope Converter
TELCOM SEMICONDUCTOR, INC.
3-3/4 A/D CONVERTER WITH
FREQUENCY COUNTER
AND LOGIC PROBE
1
TC820
1
RINT CINT
∫
tINT
0
comparator) are removed from the conversion. A true digital
zero reading is assured without any external adjustments.
A complete conversion consists of four distinct phases:
VREF tDEINT
VIN (t) dt =
RINT CINT
(1)
(2)
(3)
(4)
where: VREF = Reference voltage
t INT
= Integration time
t DEINT = Deintegration time
For a constant t INT:
t DEINT
VIN = VREF 3
t INT
NORMAL MODE REJECTION (dB)
Accuracy in a dual-slope converter is unrelated to the
integrating resistor and capacitor values as long as they are
stable during a measurement cycle. An inherent benefit of
the dual-slope technique is noise immunity. Noise spikes
are integrated or averaged to zero during the integration
periods, making integrating ADCs immune to the large
conversion errors that plague successive approximation
converters in high-noise environments. Interfering signals,
with frequency components at multiples of the averaging
(integrating) period, will be attenuated (Figure 3). Integrating
ADCs commonly operate with the signal integration period
set to a multiple of the 50/60Hz power line period.
Zero Integrator Output Phase
This phase guarantees that the integrator output is at 0V
before the system zero phase is entered, ensuring that the
true system offset voltages will be compensated for even
after an overrange conversion. The duration of this phase is
500 counts plus the unused deintegrate counts.
Auto-Zero Phase
During the auto-zero phase, the differential input signal
is disconnected from the measurement circuit by opening
internal analog switches, and the internal nodes are shorted
to Analog Common (0VREF) to establish a zero input condition. Additional analog switches close a feedback loop
around the integrator and comparator to permit comparator
offset voltage error compensation. A voltage established on
CAZ then compensates for internal device offset voltages
during the measurement cycle. The auto-zero phase residual is typically 10µV to 15µV. The auto-zero duration is
1500 counts.
30
Signal Integration Phase
Upon completion of the auto-zero phase, the auto-zero
loop is opened and the internal differential inputs connect to
VIN+ and VIN–. The differential input signal is then integrated
for a fixed time period, which is 2000 counts (4000 clock
periods). The externally-set clock frequency is divided by
two before clocking the internal counters. The integration
time period is:
T = MEASUREMENT
PERIOD
20
10
t INT =
0
0.1/T
1/T
INPUT FREQUENCY
10/T
Figure 3. Normal-Mode Rejection of Dual-Slope Converter
Analog Section
In addition to the basic integrate and deintegrate dualslope phases discussed above, the TC820 design incorporates a "zero integrator output" phase and an "auto-zero"
phase. These additional phases ensure that the integrator
starts at 0V (even after a severe overrange conversion), and
that all offset voltage errors (buffer amplifier, integrator and
TELCOM SEMICONDUCTOR, INC.
2
Zero Integrator Output
Auto-Zero
Signal Integrate
Reference Deintegrate
3
4
5
6
4000
fOSC
The differential input voltage must be within the device's
common-mode range when the converter and measured
system share the same power supply common (ground). If
the converter and measured system do not share the same
power supply common, as in battery-powered applications,
VIN– should be tied to analog common.
Polarity is determined at the end of signal integration
phase. The sign bit is a "true polarity" indication in that
signals less than 1 LSB are correctly determined. This
allows precision null detection that is limited only by device
noise and auto-zero residual offsets.
3-157
7
8
3-3/4 A/D CONVERTER WITH
FREQUENCY COUNTER
AND LOGIC PROBE
TC820
Reference Integrate (Deintegrate) Phase
The reference capacitor, which was charged during the
auto-zero phase, is connected to the input of the integrating
amplifier. The internal sign logic ensures the polarity of the
reference voltage is always connected in the phase opposite
to that of the input voltage. This causes the integrator to
ramp back to zero at a constant rate determined by the
reference potential.
The amount of time required (TDEINT) for the integrating
amplifier to reach zero is directly proportional to the amplitude of the voltage that was put on the integrating capacitor
(VINT) during the integration phase:
t DEINT = RINT CINT VINT
VREF
The digital reading displayed by the TC820 is:
Digital Count = 2000
+ – V–
VIN
IN
VREF
System Timing
The oscillator frequency is divided by 2 prior to clocking
the internal decade counters. The four-phase measurement
cycle takes a total of 8000 (4000) counts or 16000 clock
pulses. The 8000 count phase is independent of input signal
magnitude or polarity.
Each phase of the measurement cycle has the following
length:
Conversion Phase
Counts
1) Auto-Zero:
2) Signal Integrate:1,2
3) Reference Integrate:
4) Integrator Output Zero:
1500
2000
1 to 4001
499 to 4499
NOTES: 1. This time period is fixed. The integration period for the
TC820 is:
t INT (TC820) =
4000
fOSC
= 2000 counts
where fOSC is the clock oscillator frequency.
2. Times shown are the RANGE/FREQ at logic low (normal
operation). When RANGE/FREQ is logic high, signal
integrate times are 200 counts. See "10:1 Range Change"
section.
Input Overrange
When the analog input is greater than full scale, the LCD
will display "OL" and the "OVERRANGE" LCD annunciator
will be on.
Peak Reading Hold
The TC820 provides the capability of holding the highest
(or peak) reading. Connecting the PK HOLD input to VDD
enables the peak hold feature. At the end of each conversion
the contents of the TC820 counter is compared to the
contents of the display register. If the new reading is higher
than the reading being displayed, the higher reading is
transferred to the display register. A "higher" reading is
defined as the reading with the higher absolute value.
The peak reading is held in the display register so the
reading will not "droop" or slowly decay with time. The held
reading will be retained until a higher reading occurs, the PK
HOLD input is disconnected from VDD, or power is removed.
The peak signal to be measured must be present during
the TC820 signal integrate period. The TC820 does not
perform transient peak detection of the analog input signal.
However, in many cases, such as measuring temperature or
electric motor starting current, the TC820 "acquisition time"
will not be a limitation. If true peak detection is required, a
simple circuit will suffice. See the applications section for
details.
The peak reading function is also available when the
TC820 is in the frequency counter mode. The counter autoranging feature is disabled when peak reading hold is
selected.
10:1 Range Change
The analog input full-scale range can be changed with
the RANGE/FREQ input. Normally, RANGE/FREQ is held
low by an internal pulldown. Connecting this pin to VS+ will
increase the full-scale voltage by a factor of 10. No external
component changes are required.
The RANGE/FREQ input operates by changing the
integrate period. When RANGE/FREQ is connected to VDD,
the signal integration phase of the conversion is reduced by
a factor of 10 (i.e., from 2000 counts to 200 counts).
For the TC820, the 10:1 range change will result in ±4V
full scale. This full-scale range will exceed the commonmode range of the input buffer when operating from a 9V
battery. If range changing is required for the TC820, a higher
supply voltage can be provided or the input voltage can be
divided by 2 externally.
Frequency Counter
In addition to serving as an analog-to-digital converter,
the TC820 internal counter can also function as a frequency
counter (Figure 4). In the counter mode, pulses at the
RANGE/FREQ input will be counted and displayed.
The frequency counter derives its time base from the
clock oscillator. The counter time base is:
tCOUNT =
3-158
fOSC
40,000
TELCOM SEMICONDUCTOR, INC.
3-3/4 A/D CONVERTER WITH
FREQUENCY COUNTER
AND LOGIC PROBE
1
TC820
Thus, the counter will operate with a 1-second time base
when a 40 kHz oscillator is used. The frequency counter
accuracy is determined by the oscillator accuracy. For
accurate frequency measurements, a crystal oscillator is
recommended.
The frequency counter will automatically select the
proper range. Auto-range operation extends over four
decades, from 3.999 kHz to 3.999 MHz. Decimal points are
set automatically in the frequency mode (Figure 5).
The logic switching levels of the RANGE/FREQ input
are CMOS levels. For best counter operation, an external
buffer is recommended. See the applications section for
details.
Logic Probe
The TC820 can also function as a simple logic probe
(Figure 6). This mode is selected when the LOGIC input is
high. Two dual-purpose pins, which normally control the
decimal points, are used as logic inputs. Connecting either
input to a logic high level will turn on the corresponding LCD
annunciator. When the "low" annunciator is on the buzzer
will be on. As with the frequency counter input, external level
shifters/buffers are recommended for the logic probe inputs.
When the logic probe function is selected while FREQ/
VOLTS is low (A/D mode), the ADC will remain in the autozero mode. The LCD will read "OL" and all decimal points will
be off (Figure 7).
If the logic probe is active while FREQ/VOLTS is high
(counter mode), the frequency counter will continue to
operate. The display will read "OL" but the decimal points will
be visible. If the logic probe input is also connected to the
RANGE/FREQ input, bringing the LOGIC input low will
immediately display the frequency at the logic probe input.
2
Analog Pin Functional Description
+
–
Differential Signal Inputs (VIN
), (VIN
)
The TC820 is designed with true differential inputs, and
accepts input signals within the input stage common-mode
voltage (VCM) range. The typical range is VDD –1V to VSS
+1.5V. Common-mode voltages are removed from the system when the TC820 operates from a battery or floating
power source (isolated from measured system) and VSS is
connected to analog common. (See Figure 8.)
3
4
5
LCD
6
COMPARATOR
FROM INTEGRATOR
OF A/D CONVERTER
CLOCK
OSCILLATOR
÷2
A/D CONVERTER
÷20,000
FREQUENCY COUNTER
FREQ/
VOLTS
ENABLE
3-3/4 DIGIT COUNTER
COUNT
OVERRANGE
DETECT
OVERFLOW
7
A/D CONVERTER/FREQUENCY
COUNTER SELECT
TC820
RANGE/
FREQ
DATA LATCH, PEAK
HOLD REGISTER,
LCD DECODER/DRIVERS
FREQUENCY
INPUT
PROGRAMMABLE
DIVIDER
( ÷1, 10, 100, 1000)
TO DECIMAL
POINT DRIVERS
UNDERRANGE
DETECT
AUTO-RANGE
CONTROL
8
Figure 4. TC820 Counter Operation
TELCOM SEMICONDUCTOR, INC.
3-159
3-3/4 A/D CONVERTER WITH
FREQUENCY COUNTER
AND LOGIC PROBE
TC820
DP3
DP2
In systems where common-mode voltages exist, the
86dB common-mode rejection ratio minimizes error. Common-mode voltages do, however, affect the integrator output level. A worst-case condition exists if a large, positive
VCM exists in conjunction with a full-scale, negative differential signal. The negative signal drives the integrator output
positive along with VCM (Figure 9). For such applications, the
integrator output swing can be reduced below the recommended 2V full-scale swing. The integrator output will swing
within 0.3V of VDD or VDD without increased linearity error.
DP1
f IN
DECIMAL POINT
0Hz – 3999Hz
4kHz – 39.99kHz
DP3
DP2
40kHz – 399.9kHz
≥ 400kHz
DP1
NONE
Figure 5. TC820 Auto-Range Decimal Point Selection
vs Frequency Counter Input
Reference (VDD, VSS)
The TC820 reference, like the analog signal input, has
true differential inputs. In addition, the reference voltage can
be generated anywhere within the power supply voltage of
the converter. The differential reference inputs permit
ratiometric measurements and simplify interfacing with sensors, such as load cells and temperature sensors.
LCD
HIGH
LOW
LOGIC
PROBE
INPUT
EXTERNAL
LOGIC LEVEL
DETECTION
AND PULSE
STRETCHING
CMOS
LOGIC
LEVELS
DP0/LO
LCD
DRIVERS
TC820
DP1/HI
VDD
LOGIC
DISABLE A/D CONVERTER
TO
BUZZER
NC
Figure 6. Logic Probe Simplified Schematic
3-160
TELCOM SEMICONDUCTOR, INC.
3-3/4 A/D CONVERTER WITH
FREQUENCY COUNTER
AND LOGIC PROBE
1
TC820
HIGH *
**
LOW
* "HIGH" ANNUNCIATOR WILL BE ON WHEN DP1/HI =
**
LOGIC HIGH
"LOW" ANNUNCIATOR AND BUZZER WILL BE ON
WHEN DP0/LO = LOGIC HIGH
Figure 7. LCD During Logic Probe Operation
To prevent roll-over-type errors from being induced by
large common-mode voltages, CREF should be large compared to stray node capacitance. A 0.1µF capacitor is
typical.
The TC820 offers a significantly improved analog
common temperature coefficient, providing a very stable
voltage suitable for use as a voltage reference. The
temperature coefficient of analog common is typically
35ppm/°C.
Analog Common
The analog common pin is set at a voltage potential
approximately 3.3V below VDD. This potential is guaranteed
to be between 3.15V and 3.45V below VDD. Analog common
is tied internally to an N-channel FET capable of sinking
3mA. This FET will hold the common line at 3.3V below VDD
should an external load attempt to pull the common line
toward VDD. Analog common source current is limited to
12µA, and is therefore easily pulled to a more negative
voltage (i.e., below VDD – 3.3V).
+
–
The TC820 connects the internal VIN
and VIN
inputs to
analog common during the auto-zero cycle. During the
–
reference integrate phase, VIN
is connected to analog
–
common. If VIN is not externally connected to analog common,
a common-mode voltage exists. This is rejected by the
converter's 86dB common-mode rejection ratio. In battery–
powered applications, analog common and VIN
are usually
connected, removing common-mode voltage concerns. In
–
systems where VIN
is connected to the power supply ground
or to a given voltage, analog common should be connected
–
to VIN
.
The analog common pin serves to set the analog section
reference or common point. The TC820 is specifically
designed to operate from a battery or in any measurement
SEGMENT
DRIVE
V
+
CAZ VINT
VIN
VIN
–
GND
–
V V
POWER GND
SOURCE
4
BP3
BP2
OSC1
–
+
V
+
VBUF
3
5
LCD
BP1
MEASURED
SYSTEM
2
6
TC820
ANALOG
+
–
COMMON VREF VREF VDD
OSC2
VSS OSC3
NC
+
9V
7
–
Figure 8. Common-Mode Voltage Removed in Battery Operation With VIN
= Analog Common
8
TELCOM SEMICONDUCTOR, INC.
3-161
3-3/4 A/D CONVERTER WITH
FREQUENCY COUNTER
AND LOGIC PROBE
TC820
INPUT
BUFFER
+
+
CI
RI
–
–
VIN
VI
+
INTEGRATOR
–
VI =
VCM
TI
V CM – VIN
RI CI
[
[
Where:
TI= Integration Time = 4000
fOSC
C I = Integration Capacitor
R I = Integration Resistor
Figure 9. Common-Mode Voltage Reduces Available
Integrator Swing (VCOM Þ VIN)
system where input signals are not referenced (float)
with respect to the TC820 power source. The analog common
potential of VDD – 3.3V gives a 7V end-of-battery-life voltage.
The analog common potential has a voltage coefficient of
0.001%/%.
With a sufficiently high total supply voltage (VDD – VSS
> 7V), analog common is a very stable potential with excellent
temperature stability (typically 35ppm/°C). This potential
can be used to generate the TC820 reference voltage. An
external voltage reference will be unnecessary in most
cases, because of the 35ppm/°C temperature coefficient.
See the applications section for details.
Function Control Input Pin
Functional Description
The TC820 operating modes are selected with the
function control inputs. The control input truth table is shown
in Table I. The high logic threshold is ≥ VDD - 1.5V and the
low logic level is ≤ DGND +1.5V.
Table I. TC820 Control Input Truth Table
Logic Input
FREQ/
VOLTS
RANGE/
FREQ
LOGIC
X
0
X
0
1
0
0
1
0
1
Frequency
Counter Input
0
TC820
Function
Logic Probe
A/D Converter,
VFULL SCALE = 2 3VREF
A/D Converter,
VFULL SCALE = 20 3VREF
Frequency Counter
FREQ/VOLTS
This input determines whether the TC820 is in the
analog-to-digital conversion mode or in the frequency counter
mode. When FREQ/VOLTS is connected to VDD, the TC820
will measure frequency at the RANGE/FREQ input. When
unconnected, or connected to DGND, the TC820 will operate as an analog-to-digital converter. This input has an
internal 5µA pull-down to DGND.
LOGIC
The LOGIC input is used to activate the logic probe
function. When connected to VDD, the TC820 will enter the
logic probe mode. The LCD will show "OL" and all decimal
points will be off. The decimal point inputs directly control
"high" and "low" display annunciators. When LOGIC is
unconnected, or connected to DGND, the TC820 will perform analog-to-digital or frequency measurements as selected by the FREQ/VOLTS input. The LOGIC input has an
internal 5 µA pull-down to DGND.
RANGE/FREQ
The function of this dual-purpose pin is determined by
the FREQ/VOLTS input. When FREQ/VOLTS is connected
to VDD, RANGE/FREQ is the input for the frequency counter
function. Pulses at this input are counted with a time base
equal to fOSC/40,000. Since this input has CMOS input levels
(VDD - 1.5V and DGND +1.5V), an external buffer is recommended.
When the TC820 analog-to-digital converter function is
selected, connecting RANGE/FREQ to VDD will divide the
integration time by 10. Therefore, the RANGE/FREQ input
can be used to perform a 10:1 range change without
changing external components.
DP0/LO, DP1/HI
The function of these dual-purpose pins is determined
by the LOGIC input. When the TC820 is in the analog-todigital converter mode, these inputs control the LCD decimal
points. The decimal point truth table is shown in Table II.
These inputs have internal 5µA pull-downs to DGND when
the voltage/frequency measurement mode is active.
Table II. TC820 Decimal Point Truth Table
Decimal Point Inputs
DP1
DP0
LCD
0
0
1
1
0
1
0
1
3999
399.9
39.99
3.999
NOTES: 1. Logic "0" = DGND
2. Logic "1" = VDD
3-162
TELCOM SEMICONDUCTOR, INC.
3-3/4 A/D CONVERTER WITH
FREQUENCY COUNTER
AND LOGIC PROBE
1
TC820
Connecting the LOGIC input to VDD places the TC820
in the logic probe mode. In this mode, the DP0/LO and DP1/
HI inputs control the LCD "low" and "high" annunciators
directly. When DP1/HI is connected to VDD, the "high"
annunciator will turn on. When DP0/LO is connected to VDD,
the "low" annunciator and the buzzer will turn on. The
internal pull-downs on these pins are disabled when the
logic probe function is selected.
These inputs have CMOS logic switching thresholds.
For optimum performance as a logic probe, external level
shifters are recommended. See the applications section for
details.
BUZ IN
This input controls the TC820 on-chip buzzer driver.
Connecting BUZ IN to VDD will turn the buzzer on. There is
an external pull-down to DGND. BUZ IN can be used with
external circuitry to provide additional functions, such as a
fast, audible continuity indication.
Additional Features
The TC820 is available in 40-pin and 44-pin packages.
Several additional features are available in the 44-pin package.
EOC/HOLD
EOC/HOLD is a dual-purpose, bidirectional pin. As an
output, this pin goes low for 10 clock cycles at the end of each
conversion. This pulse latches the conversion data into the
display driver section of the TC820.
EOC/HOLD can be used to hold (or "freeze") the display. Connecting this pin to VDD inhibits the display update
process. Conversions will continue, but the display will not
change. EOC/HOLD will hold the display reading for either
analog-to-digital or frequency measurements.
The input/output structure of the EOC/HOLD pin is
shown in Figure 10. The output drive current is only a few
microAmps, so EOC/HOLD can easily be overdriven by an
open-collector logic gate, as well as a FET, bipolar transistor, or mechanical switch. When used as an output, EOC/
HOLD will have a slow rise and fall time due to the limited
output current drive. A CMOS Schmitt trigger buffer is
recommended.
EOC/HOLD
4
DISPLAY
UPDATE
2
≈ 500 k Ω
EOC
3
TC820
Figure 10. EOC/HOLD Pin Schematic
Overrange (OR), Underrange (UR)
The OR output will be high when the analog input signal
is greater than full scale (3999 counts). The UR output will
be high when the display reading is 380 counts or less.
The OR and UR outputs can be used to provide an autoranging meter function. By logically ANDing these outputs
with the inverted EOC/HOLD output, a single pulse will be
generated each time an underranged or overranged conversion occurs (Figure 11).
4
5
EOC/HOLD
*
TC820 UR
*
OR
*
6
* 74HC132
Figure 11. Generating Underrange and Overrange Pulses
VDISP
The VDISP input sets the peak-to-peak LCD drive voltage. In the 40-pin package, VDISP is connected internally to
DGND, providing a typical LCD drive voltage of 5VP-P. The
44-pin package includes a separate VDISP input for applications requiring a variable or temperature-compensated LCD
drive voltage. See the applications information for suggested circuits.
7
8
TELCOM SEMICONDUCTOR, INC.
3-163
3-3/4 A/D CONVERTER WITH
FREQUENCY COUNTER
AND LOGIC PROBE
TC820
VDISP
The VDISP input sets the peak-to-peak LCD drive voltage. In the 40-pin package, VDISP is connected internally to
DGND, providing a typical LCD drive voltage of 5 VP-P. The
44-pin package includes a separate VDISP input for applications requiring a variable or temperature-compensated LCD
drive voltage. See the applications information for suggested circuits.
APPLICATIONS INFORMATION
Power Supplies
The TC820 is designed to operate from a single power
supply such as a 9V battery (Figure 12). The converter will
operate over a range of 7V to 15V. For battery operation,
analog common (COM) provides a common-mode bias
voltage (see analog common discussion in the theory of
operation section). However, measurements cannot be
referenced to battery ground. To do so will exceed the
negative common-mode voltage limit.
Digital Ground (DGND)
Digital ground is generated from an internal zener diode
(Figure 14). The voltage between VDD and DGND is the
internal supply voltage for the digital section of the TC820.
DGND will sink a minimum of 3mA.
DGND establishes the low logic level reference for the
TC820 mode select inputs, and for the frequency and logic
probe inputs. The DGND pin can be used as the negative
supply for external logic gates, such as the logic probe
buffers. To ensure correct counter operation at high frequency, connect a 1µF capacitor from DGND to VDD.
DGND also provides the drive voltage for the LCD. The
TC820 40-pin package internally connects the LCD VDISP
pin to DGND, and provides an LCD drive voltage of about
5VP-P. In the 44-pin package, connecting the VDISP pin to
DGND will provide a 5V LCD drive voltage.
Digital Input Logic Levels
Logic levels for the TC820 digital inputs are referenced
to VDD and DGND. The high-level threshold is VDD – 1.5V
and the low logic level is DGND +1.5V. In most cases,
digital inputs will be connected directly to VDD with a
mechanical switch. CMOS gates can also be used to
control the logic inputs, as shown in the logic probe inputs
section.
VDD
+
VREF
+
9V
–
–
VREF
TC820
COM
+
+
VIN
V IN
–
VIN
VDD
+
–
+
VREF
–
VREF
3.5V to 6V
TC04
COM
VSS
TC820
+
VIN
+
VIN
–
VIN
–
VSS
8
2
5
+
Figure 12. Powering the TC820 From a Single 9V Battery
A battery with voltage between 3.5V and 7V can be used
to power the TC820, when used with a voltage doubler, as
shown in Figure 13. The voltage doubler uses the TC7660
and two external capacitors. With this configuration measurements can be referenced either to Analog Common or
to battery ground.
3-164
10µF
4
TC7660
3
10µF
+
Figure 13. Powering the TC820 From a Low-Voltage Battery
TELCOM SEMICONDUCTOR, INC.
3-3/4 A/D CONVERTER WITH
FREQUENCY COUNTER
AND LOGIC PROBE
1
TC820
VDD
2
3.2V
12µA
COM
5V
–
5pF
TC820
10pF
N
+
LOGIC
SECTION
37
P
TC820
38
DGND
110kΩ
39
3
75pF
N
VSS
Figure 16. R-C Oscillator Circuit
Figure 14. DGND and COM Outputs
Typical values are R = 10kΩ and C = 68pF. The resistor
value should be ≥100kΩ. For accurate frequency measurement, an R-C oscillator frequency of 40kHz is required.
Clock Oscillator
The TC820 oscillator can be controlled with either a
crystal or with an inexpensive resistor-capacitor combination. The crystal circuit, shown in Figure 15, is recommended
when high accuracy is required in the frequency counter
mode. The 40kHz crystal is a standard frequency for ultrasonic alarms, and will provide a 1-second time base for the
counter or 2.5 analog-to-digital conversions per second.
Consult the crystal manufacturer for detailed applications
information.
Where low cost is important, the R-C circuit of Figure 16
can be used. The frequency of this circuit will be approximately:
0.3
fOSC =
RC
5 pF
10pF
38
37
TC820
39
470kΩ
40kHz
22 MΩ
Figure 15. Suggested Crystal Oscillator Circuit
TELCOM SEMICONDUCTOR, INC.
4
System Timing
All system timing is derived from the clock oscillator. The
clock oscillator is divided by 2 prior to clocking the A/D
counters. The clock is also divided by 8 to drive the buzzer,
by 240 to generate the LCD backplane frequency, and by
40,000 for the frequency counter time base. A simplified
diagram of the system clock is shown in Figure 17.
5
Component Value Selection
Auto Zero Capacitor — CAZ
The value of the auto-zero capacitor (CAZ) has some
influence on system noise. A 0.47µF capacitor is recommended; a low dielectric absorption capacitor (Mylar) is
required.
Reference Voltage Capacitor — CREF
The reference voltage capacitor used to ramp the integrator output voltage back to zero during the reference
integrate cycle is stored on CREF. A 0.1µF capacitor is
typical. A good quality, low leakage capacitor (such as
Mylar) should be used.
Integrating Capacitor — CINT
CINT should be selected to maximize integrator output
voltage swing without causing output saturation. Analog
common will normally supply the differential voltage
reference. For this case, a ±2V integrator output swing is
optimum when the analog input is near full scale. For 2.5
readings/second (fOSC = 40kHz) and VFS = 400mV, a 0.22µF
value is suggested. If a different oscillator frequency is used,
CINT must be changed in inverse proportion to maintain the
3-165
6
7
8
3-3/4 A/D CONVERTER WITH
FREQUENCY COUNTER
AND LOGIC PROBE
TC820
Reference Voltage Selection
R/C
OSCILLATOR
COMPONENTS
A full-scale reading (4000 counts for TC820) requires
the input signal be twice the reference voltage.
Table III. Reference Voltage Selection
XTAL
OSCILLATOR
COMPONENTS
OSC1
OSC2
OSC3
TC820
A/D
COUNTER
÷2
BUZZER
÷8
LCD
BACKPLANE
DRIVER
COUNTER
TIME BASE
÷240
÷40,000
Figure 17. System Clock Generation
nominal ±2V integrator swing. An exact expression for CINT
is:
CINT =
where: fOSC
VFS
RINT
VINT
4000 VFS
VINT RINT fOSC
= Clock frequency
= Full-scale input voltage
= Integrating resistor
= Desired full-scale integrator output swing
CINT must have low dielectric absorption to minimize
roll-over error. A polypropylene capacitor is recommended.
Integrating Resistor — RINT
The input buffer amplifier and integrator are designed
with class A output stages. The integrator and buffer can
supply 40µA drive currents with negligible linearity errors.
RINT is chosen to remain in the output stage linear drive
region but not so large that printed circuit board leakage
currents induce errors. For a 400mV full scale, RINT should
be about 100kΩ.
3-166
Full-Scale
Input Voltage
(VFS) (Note 1)
VREF
Resolution
200mV
Note 2
–
400mV
1V
2V
(Notes 3, 4)
200mV
500mV
1V
10 µV
250µV
500µV
NOTES: 1. TC820 in A/D converter mode, RANGE/FREQ = logic low.
2. Not recommended.
3. VFS > 2V may exceed the input common mode range.
See "10:1 Range Change" section.
4. Full-scale voltage values are not limited to the values
shown. For example, TC820 VFS can be any value from
400mV to 2V.
In some applications, a scale factor other than unity may
exist between a transducer output voltage and the required
digital reading. Assume, for example, that a pressure transducer output is 800mV for 4000 lb/in2. Rather than dividing
the input voltage by two, the reference voltage should be set
to 400mV. This permits the transducer input to be used
directly.
The internal voltage reference potential available at
analog common will normally be used to supply the
converter's reference voltage. This potential is stable whenever the supply potential is greater than approximately 7V.
The low-battery detection circuit and analog common operate from the same internal reference. This ensures that the
low-battery annunciator will turn on at the time the internal
reference begins to lose regulation.
The TC820 can also operate with an external reference.
Figure 18 shows internal and external reference applications.
Ratiometric Resistance Measurements
The TC820 true differential input and differential reference make ratiometric readings possible. In ratiometric
operation, an unknown resistance is measured with respect
to a known standard resistance. No accurately defined
reference voltage is needed.
The unknown resistance is put in series with a known
standard and a current is passed through the pair (Figure 19). The voltage developed across the unknown is
applied to the input and voltages across the known resistor
TELCOM SEMICONDUCTOR, INC.
3-3/4 A/D CONVERTER WITH
FREQUENCY COUNTER
AND LOGIC PROBE
1
TC820
9V
+
V
+
1µF
TC04A
+
TC820
TC820
VREF
1.2V
REF
–
VREF
VREF
ANALOG
COMMON
COMMON
–
FREQ/VOLTS
DGND
FREQUENCY
INPUT
RANGE/FREQ
DGND
GND
(a) Internal Reference
3
74HC14
SET VREF = 1/2 VFULL SCALE
(b) External Reference
Figure 18. Reference Voltage Connections
Figure 20. Frequency Counter External Buffer
Logic Probe Inputs
+
VREF
RSTANDARD
VDD
–
VREF
LCD
+
VIN
TC820
RUNKNOWN
–
VIN
ANALOG
COMMON
Figure 19. Low Parts Count Ratiometric Resistance Measurement
applied to the reference input. If the unknown equals the
standard, the input voltage will equal the reference voltage
and the display will read 2000. The displayed reading can be
determined from the following expression:
Displayed reading =
2
VDD
2kΩ
VREF
TC820
+
VDD
VDD
VREF
+9V
2kΩ
22kΩ
VSS
+
RUNKNOWN
RSTANDARD
3 2000
The DP0/LO and DP1/HI inputs provide the logic probe
inputs when the LOGIC input is high. Driving either DP0/LO
or DP1/HI to a logic high will turn on the appropriate LCD
annunciator. When DP0/LO is high, the buzzer will be on.
To provide a "single input" logic probe function, external
buffers should be used. A simple circuit is shown in Figure
21. This circuit will turn the appropriate annunciator on for
high and low level inputs.
If carefully controlled logic thresholds are required, a
window comparator can be used. Figure 22 shows a typical
circuit. This circuit will turn on the high or low annunciators
when the logic thresholds are exceeded, but the resistors
connected from DP0/LO and DP1/HI to DGND will turn both
annunciators off when the logic probe is unconnected.
The TC820 logic inputs are not latched internally, so
pulses of short duration will usually be difficult or impossible
to see. To display short pulses properly, the input pulse
should be "stretched." The circuit of Figure 22 shows cap-
The display will overrange for values of RUNKNOWN ≥ 2
3 RSTANDARD.
+9V
VDD
When the FREQ/VOLTS input is high and the LOGIC
input is low, the TC820 will count pulses at the RANGE/
FREQ input. The time base will be fOSC/40,000, or 1 second
with a 40kHz clock. The signal to be measured should swing
from VDD to DGND. The RANGE/FREQ input has CMOS
input levels without hysteresis. For best results, especially
with low-frequency sine-wave inputs, an external buffer with
hysteresis should be added. A typical circuit is shown in
Figure 20.
LOGIC
TELCOM SEMICONDUCTOR, INC.
*
5
6
TC820
Buffering the FREQ Input
LOGIC
PROBE
INPUT
4
*
7
DP1/HI
DP0/LO
DGND
* 74HC14
8
Figure 21. Simple External Logic Probe Buffer
3-167
3-3/4 A/D CONVERTER WITH
FREQUENCY COUNTER
AND LOGIC PROBE
TC820
+9V
VDD
LOGIC
R1
1N4148
PK HOLD
DP1/HI
+
R2
–
1N4148
VL +
1N4148
–
TC820
LOGIC
PROBE
INPUT
VDD
10kΩ
+
TL061
VIN
VIN
+
VH –
1MΩ
+9V
TC820
0.01µF
DP0/LO
OFFSET
NULL
1MΩ
R3
VSS
0V
DGND
NOTE: Select R1, R2, R3 for desired logic thresholds.
Figure 22. Window Comparator Logic Probe
Figure 23. External Peak Detector
acitors added across the input pull-down resistors to stretch
the input pulse and permit viewing short-duration input
pulses.
depending on the displays values. Figure 25 shows a set of
waveforms for the a, g, d outputs of one digit for several
combinations of "on" segments.
External Peak Detection
Table IV. LCD Backplane and Segment Assignments
The TC820 will hold the highest A/D conversion or
frequency reading indefinitely when the PK HOLD input is
connected to VDD. However, the analog peak input must be
present during the A/D converter's signal integrate period.
For slowly changing signals, such as temperature, the peak
reading will be properly converted and held.
If rapidly changing analog signals must be held, an
external peak detector should be added. An inexpensive
circuit can be made from an op amp and a few discrete
components, as shown in Figure 23. The droop rate of the
external peak detector should be adjusted so that the held
voltage will not decay below the desired accuracy level
during the converter's 400msec conversion time.
40-Pin DIP
Pin No.
44-Pin
Flat Pkg
Pin No.
LCD
Display
Pin No.
BP1
BP2
BP3
1
40
3
LOW
"—"
E4
2
41
4
A4
G4
D4
3
42
5
B4
C4
DP3
4
43
6
HIGH
F3
E3
5
44
7
A3
G3
D3
6
1
8
B3
C3
DP2
7
2
9
OVER
F2
E2
Liquid Crystal Display (LCD)
8
3
10
A2
G2
D2
The TC820 drives a triplex (multiplexed 3:1) LCD with
three backplanes. The LCD can include decimal points,
polarity sign, and annunciators for overrange, peak hold,
high and low logic levels, and low battery. Table IV shows the
assignment of the display segments to the backplanes and
segment drive lines. The backplane drive frequency is
obtained by dividing the oscillator frequency by 240.
Backplane waveforms are shown in Figure 24. These
appear on outputs BP1, BP2, and BP3. They remain the
same regardless of the segments being driven.
Other display output lines have waveforms that vary
9
4
11
B2
C2
DP1
10
5
12
PEAK
F1
E1
11
6
13
A1
G1
D1
12
7
14
B1
C1
BATT
13
8
2,16*
—
—
BP3
3-168
14
9
1
—
BP2
—
15
10
15
BP1
—
—
*Connect both pins 2 and 16 of LCD to TC820 BP3 output.
TELCOM SEMICONDUCTOR, INC.
3-3/4 A/D CONVERTER WITH
FREQUENCY COUNTER
AND LOGIC PROBE
1
TC820
LCD Source
BP1
Although most users will design their own custom LCD,
a standard display for the TC820 (Figure 26), Part No. ST1355-M1, is available from:
BP2
Crystaloid (USA)
Crystaloid Electronics
P.O. Box 628
5282 Hudson Dr.
Hudson, OH 44238
Phone: (216) 655-2429
Fax: (216) 655-2176
BP3
Figure 24. Backplane Waveforms
VDD
VH
SEGMENT
LINE
ALL OFF
VL
VDISP
VDD
VH
a SEGMENT
ON
d, g OFF
VL
VDISP
VDD
VH
a, g ON
d OFF
VL
VDISP
VDD
VH
ALL ON
VL
VDISP
Figure 25. Typical Display Output Waveforms
Crystaloid (Europe)
Rep France
102, rue des Nouvelles
F92150 Suresnes
France
Phone: 33-1-42 04 29 25
Fax: 33-1-45 06 46 99
2
3
Annunciator Output
The annunciator output is a square wave running
at the backplane frequency (for example, 167Hz when
fOSC = 40kHz). The peak-to-peak amplitude is equal to (VDD
– VDISP). Connecting an annunciator of the LCD to the
annunciator output turns it on; connecting it to its backplane
turns it off.
4
LCD Drive Voltage (VDISP)
The peak-to-peak LCD drive voltage is equal to (VDD –
VDISP). In the 40-pin dual-in-line package (DIP), VDISP is
internally connected to DGND, providing a typical LCD drive
voltage of 5VP-P.
For applications with a wide temperature range, some
LCDs require that the drive levels vary with temperature to
maintain good viewing angle and display contrast. In this
case, the TC820 44-pin package provides a pin connection
for VDISP. Figure 27 shows TC820 circuits that can be
adjusted to give a temperature compensation of about
10mV/°C between VDD and VDISP. The diode between GND
and VDISP should have a low turn-on voltage because VDISP
cannot exceed 0.3V below GND.
5
6
Crystal Source
Two sources of the 40 kHz crystal are:
HIGH
OVER
PEAK
BATT
LOW
Statek Corp.
512 N. Main St.
Orange, CA 92668
Phone: (714) 639-7810
Fax: (714) 997-1256
Part #: CX-1V-40.0
SPK Electronics
2F-1, No. 312, Sec. 4,
Jen Ai Rd
Taipei, Taiwan R.O.C.
Phone: (02) 754-2677
Fax: 886-2-708-4124
Part#: QRT-38-40.0kHz
8
PIN 1
Figure 26. Typical TC820 LCD
TELCOM SEMICONDUCTOR, INC.
7
3-169
3-3/4 A/D CONVERTER WITH
FREQUENCY COUNTER
AND LOGIC PROBE
TC820
V
1N4148
39kΩ
+
V
39kΩ
39
200kΩ
+
TL071 1N5817
TC820
TC820
11
5kΩ
39
2N2222
20kΩ
–
12
+
11
VDISP
1N5817
DGND
12
VDISP
DGND
18kΩ
75kΩ
24
V
24
–
V
–
NOTE: Pin numbers shown are for 44-pin flat package.
Figure 27. Temperature-Compensating Circuits
3-170
TELCOM SEMICONDUCTOR, INC.