TMT T431616C-7SG

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TE
CH
T431616C
SDRAM
512K x 16bit x 2Banks Synchronous DRAM
FEATURES
GRNERAL DESCRIPTION
1M x 16 SDRAM
•
•
•
•
•
3.3V power supply
Clock cycle time : 6 / 7 ns
Dual banks operation
LVTTL compatible with multiplexed address
All inputs are sampled at the positive going
edge of system clock
• Burst Read Single-bit Write operation
• DQM for masking
• Auto refresh and self refresh
• 32ms refresh period (2K cycle)
• MRS cycle with address key programs
- CAS Latency ( 2 & 3 )
- Burst Length ( 1 , 2 , 4 , 8 & full page)
- Burst Type (Sequential & Interleave)
• Available package type :
- 50 pin TSOP(II)/lead-free
• Operating temperature :
- 0 ~ +70 °C
The T431616C is 16,777,216 bits synchronous
high data rate Dynamic RAM organized as
2 x 524,288 words by 16 bits , fabricated with high
performance CMOS technology . Synchronous
design allows precise cycle control with the use of
system clock I/O transactions are possible on every
clock cycle . Range of operating frequencies ,
programmable burst length and programmable
latencies allow the same device to be useful for a
variety of high bandwidth , high performance
memory system applications.
ORDERING INFORMATION
CLOCK
MAX
CYCLE TIME
FREQUENCY
T431616C-6S
6ns
166 MHz
TSOP-II
0 ~ +70 °C
T431616C-6SG
6ns
166 MHz
TSOP-II
Lead-free
0 ~ +70 °C
T431616C-7S
7ns
143 MHz
TSOP-II
0 ~ +70 °C
T431616C-7SG
7ns
143 MHz
TSOP-II
Lead-free
0 ~ +70 °C
PART NO.
PACKAGE
TM Technology Inc. reserves the right
P. 1
to change products or specifications without notice.
OPERATING
TEMPERATURE
Publication Date: AUG. 2004
Revision: A
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TE
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T431616C
PIN ARRANGEMENT
(TSOP-II Top View)
VDD
1
50
V ss
DQ0
2
49
D Q 15
DQ1
3
48
D Q 14
V SSQ
4
47
V SSQ
DQ2
5
46
D Q 13
DQ3
6
45
D Q 12
VDDQ
7
44
VDDQ
DQ4
8
43
D Q 11
DQ5
9
42
D Q 10
V SSQ
10
41
V SSQ
DQ6
11
40
DQ9
39
DQ8
38
VDDQ
14
37
N .C /R F U
WE
15
36
UDQM
CAS
16
35
CLK
RAS
17
34
CKE
CS
18
33
N .C
DQ7
12
VDDQ
13
LD Q M
5 0 P IN T S O P ( II)
( 4 0 0 m il x 8 2 5 m il)
( 0 .8 m m P IN P IT C H )
BA
19
32
A9
A 1 0 /A P
20
31
A8
A0
21
30
A7
A1
22
29
A6
A2
23
28
A5
A3
24
27
A4
VDD
25
26
V ss
TM Technology Inc. reserves the right
P. 2
to change products or specifications without notice.
Publication Date: AUG. 2004
Revision: A
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T431616C
BLOCK DIAGRAM
512K x 16
512K x 16
Output Buffer
Sense AMP
Row Decoder
A DD
D ata Input Register
Row Buffeer
Refresh Counter
Col. Buffer
LCBR
LRAS
Address Register
CLK
I/O Control
Bank Select
LW E
LDQ M
D Qi
Colum n Decoder
Latency & Burst Length
LCKE
LRAS
LCBR
Program m ing R egister
LW E
LCAS
LDQ M
LW CB R
Tim ing Register
CLK
CK E
CS
RA S
CA S
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to change products or specifications without notice.
WE
L(U)DQ M
Publication Date: AUG. 2004
Revision: A
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T431616C
PIN DESCRIPTION
PIN
NAME
CLK
System Clock
CS
Chip Select
INPUT FUNCTION
Active on the positive going edge to sample all input.
Disables or enables device operation by masking or enabling all input
except CLK,CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE
Clock Enable
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
A0 ~ A10/AP
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10,column address : CA0 ~ CA7
BA
Bank Select Address
Selects bank to be activated during row address latch time.
Select bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK
RAS
Row Address Strobe with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK
CAS
Column Address Strobe with CAS low.
Enables column access .
WE
L(U)DQM
DQ0 ~ DQ15
VDD/VSS
VDDQ/VSSQ
Write Enable
Data Input/Output
Mask
Data Input/Output
Latches data in starting from CAS , WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power Supply/Ground Power and ground for the input buffers and the core logic.
Data Output
Power/Ground
No
N.C/RFU
Enables write operation and row precharge.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
This pin is recommended to be left No Connection on the device.
Connection/Reserved
for Future Use
TM Technology Inc. reserves the right
P. 4
to change products or specifications without notice.
Publication Date: AUG. 2004
Revision: A
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T431616C
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on Any Pin Relative To Vss
VIN,VOUT
-1.0 to 4.6
V
Supply Voltage Relative To Vss
VDD,VDDQ
-1.0 to 4.6
V
Iout
PD
50
mA
1
W
TOPR
0 to +70
°C
Tstg
-55 to +125
°C
Short circuit Output Current
Power Dissipation
Operating Temperature
Storage Temperature
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA = 0 to +70 °C, Voltage referenced to VSS=0V)
Parameter
Symbol
Min.
Typ
Max.
Unit
Notes
Supply Voltage
VDD,VDDQ
3.0
3.3
3.6
V
Input High Voltage
VIH
2.0
3.0
VDD+0.3V
V
1
Input Low Voltage
VIL
-0.3
0
0.8
V
2
Output logic high voltage
VOH
2.4
-
-
V
IOH=-2mA
Output logic low voltage
VOL
-
-
0.4
V
IOL=2mA
Input leakage current
IIL
-5
-
5
uA
3
Output leakage current
IOL
-5
-
5
uA
4
Note : 1. VIH (max) = 4.6V AC for pulse width ≤ 10ns acceptable.
2. VIL (min) = -1.0V AC for pulse width ≤ 10ns acceptable.
3. Any input 0V ≤ VIN ≤ VDD+ 0.3V , all other pin are not under test = 0V.
4. Dout = disable, 0V ≤ VOUT ≤ VDD .
CAPACITANCE
(TA =25 °C,VDD=3.3V, f = 1MHz)
Pin
Symbol
Min
Max
Unit
CLOCK
CCLK
2.5
4.0
pF
ADDRESS
CADD
2.5
4.0
pF
DQ0 ~ DQ15
COUT
3.0
5.0
pF
RAS,CAS,WE,CS,CKE,LDQM,
CIN
2.5
4.0
pF
UDQM
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to change products or specifications without notice.
Publication Date: AUG. 2004
Revision: A
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T431616C
DC CHARACTERISTICS
TA = 0 to 70°C, VIH(min)/VIL(max)=2.0V/0.8V
Parameter
Operating Current
( One Bank Active)
Symbol
ICC1
Speed version
-6
-7
145
140
Precharge Standby ICC2P
Current in powerICC2PS
down mode
Precharge Standby
Current in non
power-down mode
mA
3
ICC2N
mA
Active Standby
ICC3P
Current in powerICC3PS
down mode
10
Operating Current
ICC4
Refresh Current
ICC5
Self refresh
Current
ICC6
mA
mA
30
CKE ≤ VIL(max),CLK
≤ VIL(max), tCC = ∞
3
Input signals are changed one time during 30ns
CKE≥VIH(min),CLK ≤ VIL(min), tCC = ∞
3
CKE ≤ VIL(max),tCC= tCC(min)
CKE ≤ VIL(max),CLK
≤ VIL(max), tCC = ∞
3
Input signals are changed one time during 30ns
CKE≥VIH(min),CLK ≤ VIL(min), tCC = ∞
3
Input signals are stable
140
150
140
90
80
1
1,3
CKE≥VIH(min), CS ≥VIH(min),tCC= tCC(min)
40
150
tRC≥tRC(min) ,tCC≥tCC(min),IOL= 0 mA
Input signals are stable
10
Active Standby
ICC3N
Current in non
power-down mode
(One Bank Active) ICC3NS
Burst Length = 1
Note
CKE ≥ VIH(min), CS ≥ VIH(min),tCC= tCC(min)
30
2
Note:
mA
Test Condition
CKE ≤ VIL(max),tCC= tCC(min)
2
ICC2NS
(Burst Mode)
Unit
CAS Latency 3
mA
All Band Activated
CAS Latency 2
mA tRC ≥tRC(min)
mA
IOL=0 mA,Page Burst
1,3
tCCD= tCCD(min)
2,3
CKE ≤ 0.2V
1. Measured with output open. Addresses are changed only one time during tCC(min) .
2. Refresh period is 32ms. Addresses are changed only one time during tCC(min) .
3. tCC : Clock cycle time.
tRC : Row cycle time.
tCCD : Column address to column address delay time.
TM Technology Inc. reserves the right
P. 6
to change products or specifications without notice.
Publication Date: AUG. 2004
Revision: A
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T431616C
AC OPERATING CONDITIONS
(VDD=3.3V ±0.3V ,TA= 0 to 70°C)
Parameter
Input levels (VIH/VIL)
Value
Unit
2.0 / 0.8
V
1.4
V
tr / tf = 1 / 1
ns
1.4
V
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
See Fig.2
Vtt=1.4v
3.3V
50 ohm
1200 ohm
Output
Output
870 ohm
30pf
VOH(DC)=2.4,IOH=-2mA
VOL(DC)=0.4,IOL=2mA
(Fig.1) DC Output Load Circuit
TM Technology Inc. reserves the right
P. 7
to change products or specifications without notice.
ZO=50 ohm
30pf
(Fig.2)AC Output Load Circuit
Publication Date: AUG. 2004
Revision: A
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T431616C
OPERATING AC PARAMETER
(AC opterating conditions unless otherwise noted)
Parameter
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to new col. Address delay
Last data in to row precharge
Last data in to burst stop
Col. Address to col. Address delay
Number of valid output data
Symbol
tRRD(min)
tRCD(min)
tRP(min)
tRAS(min)
tRAS(max)
tRC(min)
tCDL(min)
tRDL(min)
tBDL(min)
tCCD(min)
CAS latency=3
CAS latency=2
Speed Version
-6
-7
Unit
Note
12
14
ns
1
18
21
ns
1
18
21
ns
1
36
42
ns
1
100K
60
ns
70
ns
1
1
CLK
2
2
CLK
2
1
CLK
2
1
1
1
CLK
3
ea
4
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required
with clock cycle time and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
The earliest a precharge command can be issued after a Read command without the loss of data is
CL + BL-2 clocks.
TM Technology Inc. reserves the right
P. 8
to change products or specifications without notice.
Publication Date: AUG. 2004
Revision: A
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CH
T431616C
AC CHARACTERISTICS
(AC opterating conditions unless otherwise noted)
Parameter
-6
Symbol
Min
CLK cycle time
CAS Latency = 3
CAS Latency = 2
CLK to valid
Output delay
CAS Latency = 3
tCC
tSAC
CAS Latency = 2
tOH
tCH
tCL
tSS
tSH
tSLZ
Output data hold time
CLK high pulse width
CLK low pulse width
Input setup time
Input hold time
CLK to output in Low-Z
CAS Latency = 3
6
-7
Max
1K
8
Min
7
Unit Note
Max
1K
ns
1
8.6
-
5.5
-
6
ns
-
6
-
6
ns
1
1
1
ns
2
2
2.5
ns
3
2
2.5
ns
3
2
2
ns
3
1
1
ns
3
1
1
ns
2
-
5.5
-
6
ns
-
6
-
6
ns
tSHZ
CLK to output in Hi-Z
CAS Latency = 2
Note: 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns,transient time compensation should be considered,
i.e.,[(tr+tf)/2-1]ns should be added to the parameter.
TM Technology Inc. reserves the right
P.9
to change products or specifications without notice.
Publication Date: AUG. 2004
Revision: A
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CH
T431616C
FREQUENCY vs. AC PARAMETER RELATIONAHIP TABLE
T431616C-6S
(Unit : number of clock)
Frequency
CAS
Latency
tRC
tRAS
tRP
tRRD
tRCD
tCCD
tCDL
tRDL
60ns
36ns
18ns
12ns
18ns
6ns
6ns
12ns
166MHz(6.0ns)
143MHz(7.0ns)
125MHz(8.0ns)
111MHz(9.0ns)
100MHz(10.0ns)
3
3
2
2
2
10
9
8
7
6
6
6
5
4
4
3
3
3
2
2
2
2
2
2
2
3
3
3
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
T431616C-7S
(Unit : number of clock)
Frequency
CAS
Latency
tRC
tRAS
tRP
tRRD
tRCD
tCCD
tCDL
tRDL
70ns
42ns
21ns
14ns
21ns
7ns
7ns
14ns
143MHz(7.0ns)
125MHz(8.0ns)
111MHz(9.0ns)
100MHz(10.0ns)
83MHz(12.0ns)
3
3
2
2
2
10
9
8
7
6
6
6
5
5
4
3
3
3
3
2
2
2
2
2
2
3
3
3
3
2
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
Note : 1. Clock count formula : clock ≥
base value
(round off whole number).
clock period
TM Technology Inc. reserves the right
P.10
to change products or specifications without notice.
Publication Date: MAY. 2003
Revision: D
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T431616C
MODE REGISTER
11
0
10
0
9
0
8
0
7
1
6
5
4
11
x
10
x
9
1
8
0
7
0
6
5
4
LTMODE
11
10
9
8
1
7
0
6
3
2
1
0
JEDEC Standard Test Set (refresh counter test)
5
4
3
WT
2
3
2
1
BL
0
1
0
Burst Read and Single Write (for Write Through Cache)
Use in future
11
x
10
x
9
x
8
1
7
1
6
v
5
v
4
v
11
0
10
0
9
0
8
0
7
0
6
5
4
LTMODE
3
v
3
WT
2
v
2
1
v
0
v
1
BL
0
Vender Specific
v = Valid
x = Don’t care
Mode Register Set
Burst length
Wrap type
Latency mode
Bit2-0
WT=0
WT=1
000
1
1
001
010
011
100
2
4
8
R
2
4
8
R
101
R
R
110
R
R
111
Full page
R
0
Sequential
1
Interleave
Bit6-4
CAS Latency
000
R
001
010
011
100
R
2
3
R
101
R
110
R
111
R
Remark R : Reserved
Mode Register Write Timing
CLOCK
CKE
CS
RAS
CAS
WE
A0-A11
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P.11
Publication Date: AUG. 2004
Revision: A
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T431616C
Burst Length and Sequence
(Burst of Two)
Starting Address
(column address A0 binary)
Sequential Addressing
Sequence (decimal)
Interleave Addressing
Sequence (Decimal)
0
1
0,1
1,0
0,1
1,0
Starting Address
(column address A1-A0 binary)
Sequential Addressing
Sequence (decimal)
Interleave Addressing
Sequence (Decimal)
00
01
10
11
0,1,2,3
1,2,3,0
2,3,0,1
3,0,1,2
0,1,2,3
1,0,3,2
2,3,0,1
3,2,1,0
Starting Address
(column address A2-A0 binary)
Sequential Addressing
Sequence (decimal)
Interleave Addressing
Sequence (Decimal)
000
001
010
011
100
101
0,1,2,3,4,5,6,7
1,2,3,4,5,6,7,0
2,3,4,5,6,7,0,1
3,4,5,6,7,0,1,2
4,5,6,7,0,1,2,3
5,6,7,0,1,2,3,4
0,1,2,3,4,5,6,7
1,0,3,2,5,4,7,6
2,3,0,1,6,7,4,5
3,2,1,0,7,6,5,4
4,5,6,7,0,1,2,3
5,4,7,6,1,0,3,2
110
111
6,7,0,1,2,3,4,5
7,0,1,2,3,4,5,6
6,7,4,5,2,3,0,1
7,6,5,4,3,2,1,0
(Burst of Four)
(Burst of Eight)
Full page burst is an extension of the above tables of Sequential Addressing, with the length being 256 for
1Mx16 divice.
POWER UP SEQUENCE
1. Apply power and start clock, attempt to maintain CKE = ‘H’ , L(U)DQM = ‘H’ and the other pin are NOP
condition at the inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue mode register set command to initalize the mode register.
Cf.) Sequence of 4 & 5 is regardless of the order.
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to change products or specifications without notice.
Publication Date: AUG. 2004
Revision: A
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T431616C
SIMPLIFIED TRUTH TABLE
COMMAND
Register
CKEn-1 CKEn CS
Mode Register Set
H
X
L
Auto Refresh
Refresh
Self
Refresh
Entry
Exit
Bank Active & Row Address
Auto Precharge Disable
Read Column
Auto Precharge Enable
Address
Write & Column Auto Precharge Disable
Auto Precharge Enable
Address
Burst Stop
Precharge
Bank Selection
Both Banks
Clock Suspend or
Active Power Down
Entry
Exit
Entry
Precharge Power Down
Mode
Exit
RAS CAS WE DQM BA A10/AP A9~A0 Note
L
L
L
X
X
1,2
H
H
L
L
L
L
H
H
X
L
H
X
H
H
X
H
L
H
H
X
L
H
L
H
X
L
H
L
H
X
L
H
H
X
L
H
X
H
L
L
H
H
L
L
H
DQM
H
No Operation Command
H
H
X
X
3
X
X
3
X
V
H
X
V
L
L
X
V
H
H
L
X
L
L
H
L
X
H
L
X
X
V
X
X
V
X
X
V
X
H
L
H
L
X
H
X
V
X
X
H
X
V
X
H
X
V
X
Row Address
Column
Address
(A0~A7)
Column
Address
(A0~A7)
L
H
L
H
X
V
X
L
H
4,5
4,5
6
4
X
X
X
X
X
V
X
7
H
X
X
X
X
X
L
H
H
H
(V=Valid , X=Don’t Care , H=Logic High , L=logic Low)
X
Notes :
1. OP Code : Operation Code. A0~A10/AP , BA : Program keys.(@MRS)
2. MRS can be issued only at both banks precharge state. A new command can be issued after 2 clock cycle of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row
precharge command is meant by ‘Auto’. Auto / self refresh can be issued only at both banks precharge state.
4. BA : Bank select address.
If ’Low’ : at read , wriye , row active and precharge , bank A is selected.
If ‘High’ : at read , wriye , row active and precharge , bank B is selected.
If A10/AP is ‘High’ : at row precharge , BA ignored and both banks are selected.
5. During burst read or write with auto precharge , new read/write command cannotbeissued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
TM Technology Inc. reserves the right
P.13
to change products or specifications without notice.
Publication Date: AUG. 2004
Revision: A
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CH
T431616C
Single Bit READ-Write Cycle (Same Page) @CAS Latency=3,Burst Length=1
tCH
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
t CL
tCC
HIGH
CKE
tRAS
tRC
tSH
*Note1
CS
tRCD
tSS
tRP
tS H
RAS
tSS
t CCD
t SH
CAS
tSS
tSS
tSH
ADDR
Ca
Ra
Cb
*Note2.
3
*Note2.
3
*Note2.
3
*Note4
*Note2
Bs
Bs
Bs
Bs
Bs
Bs
Ra
*Note3
*Note3
*Note3
*Note4
Rb
*Note2
A10/AP
Rb
tSH
tSS
BA
Cc
tRAC
tSH
tSRC
DQ
Qa
tSLZ
tOH
Db
Qc
tSS
tSH
WE
tSS
tSH
DQM
tSS
Row Active
Read
W rite
Read
Row Active
Precharge
:Don't care
TM Technology Inc. reserves the right
P.14
to change products or specifications without notice.
Publication Date: AUG. 2004
Revision: A
tm
TE
CH
T431616C
*note : 1. All input expect CKE & DQM can be don’t care when CS is high at the CLK high going edge.
2. Bank active & read/write are controlled by BA.
BA
Active & Read/Write
0
Bank A
1
Bnak B
3. Enable and disable auto precharge function are controlled by A10/AP in read/wirte command.
A10/AP
0
1
BA
Operation
0
Disable auto precharge,leave bank A active at end of burst.
1
Disable auto precharge,leave bank B active at end of burst.
0
Enable auto precharge, precharge bank A at end of burst.
1
Enable auto precharge, precharge bank B at end of burst.
4. A10/AP and BA control bank precharge when precharge command is asserted.
A10/AP BA
precharge
0
0
Bank A
0
1
Bank B
1
X
Both Banks
TM Technology Inc. reserves the right
to change products or specifications without notice.
P.15
Publication Date: AUG. 2004
Revision: A
tm
TE
CH
T431616C
Power Up Sequence
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
H ig h le v e l is n e c e ss a ry
SS
CS
tR P
RAS
tR C
tR C
SS
SS
SS
SS
tC C D
CAS
ADDR
BA
A 1 0 /A P
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
K ey
RAa
K ey
K ey
RAa
M o d e R e g iste r S e t
(A -B a n k )
R ow
A c tiv e
DQ
H ig h - Z
WE
DQM
SS
SS
SS
SS
H ig h le v e l is n e c e ss a ry
P rech arg e
A ll B a n k s
A u to
R e f re sh
A u to R e fr e s h
:D o n 't c a re
TM Technology Inc. reserves the right
to change products or specifications without notice.
P.16
Publication Date: AUG. 2004
Revision: A
tm
TE
CH
T431616C
Read & Write Cycle at Same Bank @Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
H IG H
CKE
* N o te1
tR C
CS
tR C D
RAS
* N o te2
CAS
ADDR
Ra
C a0
Rb
Cb0
BA
A 1 0 /A P
Ra
Rb
tO H
Q a0
CL=2
Q a1
Q a2
Q a3
D b0
D b1
D b2
D b3
t
RAC
* N o te3
DQ
tR D L
* N o te4
tS A C
tO H
Q a0
CL=3
tS H Z
Q a1
Q a2
Q a3
* N o te3
D b0
D b1
D b2
D b3
tR D L
* N o te4
tS A C
tS H Z
WE
DQM
R ow
A c tiv e (A B ank )
R ead (A B ank )
P rech arg
e (A B ank )
R o w A c tiv e
(A -B n ak )
W rite (A B nak )
P rech arg e
(a-B n ak )
: D o n 't c a r e
*Note : 1. Minimum row cycle times is requiqed to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is
available after Row precharge. Last valid output will be Hi-Z( tSHZ) after the clock.
3. Access time from Row active command. tCC*(tRCD+CAS latency-1)+tSAC
4. Output will be Hi-Z after the end of burst.(1,2,4,8 bit burst)
Burst can’t end in Full Page Mode.
TM Technology Inc. reserves the right
to change products or specifications without notice.
P.17
Publication Date: AUG. 2004
Revision: A
tm
TE
CH
T431616C
Page Read & Write Cycle at Same Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
H IG H
CKE
CS
tR C D
RAS
* N o te2
tC C D
CAS
ADDR
Ra
C a0
C c0
Cb0
Cd0
BA
A 1 0 /A P
tR D L
CL=2
Q a0
Q a1
Q b0
Q b1
Q b2
D c0
DQ
D c1
D d0
D d1
tCD L
Q a0
CL=3
Q a1
Q b0
Q b1
D c0
D c1
D d0
D d2
W E
* N o te3
* N o te1
DQM
R o w A c tiv e
(A -B n ak )
R ead (A B nak )
R ead (A B nak )
W rite (A B nak )
W rite (A B nak )
P rech arg e
(A -B n ak )
: D o n 't c a r e
*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write command to
avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge before
end of burst. Input data after Row precharge cycle will be masked internally.
TM Technology Inc. reserves the right
to change products or specifications without notice.
P.18
Publication Date: AUG. 2004
Revision: A
tm
TE
CH
T431616C
Page Read Cycle at Different Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
H IG H
CKE
* N o te1
CS
RAS
* N o te2
CAS
ADDR
RAa
CAa
RBb
CBb
CAc
CBd
CAe
BA
A 1 0 /A P
RAa
RBb
CL=2
Q A a0
Q A a1
Q A a2
Q A a3
Q B b0
Q B b1
Q B b2
Q B b3
Q A c0
Q A c1
Q B d0
Q B d1
Q A e0
Q A e1
Q A a0
Q A a1
Q A a2
Q A a3
Q B b0
Q B b1
Q B b2
Q B b3
Q A c0
Q A c1
Q B d0
Q B d1
Q A e0
DQ
CL=3
Q A e1
WE
DQM
R o w A c tiv e
(A -B a n k )
R ead (A B ank )
R ead (B B ank )
R ead (A B ank )
R ead (B B ank )
R ead (A B ank )
P rech arg e
(A -B a n k )
R o w A c tiv e
(B -B an k )
: D o n 't c a r e
*Note : 1. CS can be don’t cared when RAS , CAS and WE are high at the clock high going edge.
2. To interrupt a burst resd by row precharge, both the read and the precharge banks must be the same.
TM Technology Inc. reserves the right
to change products or specifications without notice.
P.19
Publication Date: AUG. 2004
Revision: A
tm
TE
CH
T431616C
Page Write cycle at Different Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
H IG H
CKE
CS
RAS
CAS
ADDR
* N o te 2
RAa
CAa
RBb
CBb
CAc
CBd
BA
A 1 0 /A P
RAa
DQ
RBb
D A a0
D A a1
D A a2
D A a3
D B b0
D B b1
D B b2
D B b3
D A c0
D A c1
D B d0
tC D L
D B d1
tR D L
WE
* N o te 1
DQM
R o w A c ti v e
(A -B a n k )
R o w A c ti v e
(B -B a n k )
W r it e ( B B an k )
W r it e ( A B an k )
W r it e ( A B an k )
W r it e ( B B an k )
P re c h a rg e
(A -B a n k )
:D o n 't c a r e
*Note : 1. To interrupt burst write by row precharge, DQM should be asserted to mask invalid input data.
2. To interrupt burst write by row precharge, both the write and the precharge banks must be the same.
TM Technology Inc. reserves the right
to change products or specifications without notice.
P.20
Publication Date: AUG. 2004
Revision: A
tm
TE
CH
T431616C
Read & Write Cycle at Different Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
H IG H
CKE
CS
RAS
CAS
ADDR
RAa
CAa
RBb
CBb
RAc
CAc
BA
A 1 0 /A P
RAa
RBb
RAc
* N o te1
tCD L
CL=2
Q A a0
Q A a1
Q A a2
Q A a3
Q A a0
Q A a1
Q A a2
D B b0
D B b1
D B b2
D B b3
D B b0
D B b1
D B b2
D B b3
Q A c0
Q A c1
Q A c2
Q A c0
Q A c1
DQ
CL=3
Q A a3
W E
DQM
R o w A c tiv e
(A -B a n k )
R ead (A B ank )
R o w A c tiv e
(B -B an k )
P rech arg e
(A -B a n k )
W rite (B B ank )
R o w A c tiv e
(A -B a n k )
R ead (A B ank )
: D o n 't c a r e
*Note : 1. tCDL should be met to complete write.
TM Technology Inc. reserves the right
to change products or specifications without notice.
P.21
Publication Date: AUG. 2004
Revision: A
tm
TE
CH
T431616C
Read & Write Cycle with Auto Precharge @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
H IG H
CKE
CS
RAS
CAS
ADDR
Ra
Rb
Ra
Rb
Ca
Cb
BA
A 1 0 /A P
Q a0
CL=2
Q a1
Q a2
Q a3
Q a0
Q a1
Q a2
D b0
D b1
D b2
D b3
D b0
D b1
D b2
D b3
DQ
CL=3
Q a3
W E
DQM
R o w A c tiv e
(A -B a n k )
R o w A c tiv e
(B -B an k )
R e a d w ith A u to
p re c h a rg e (A B ank )
C L = 2 A u to
P re c h a rg e S ta rt
P o in t (A -B a n k )
W rite w ith A u to
P rech arg e (B B ank )
C L = 3 A u to
P re c h a rg e S ta rt
P o in t (A -B a n k )
A u to P re c h a rg e
S ta rt P o in t (A B ank )
: D o n 't c a r e
*Note : 1. tCDL should be controlled to meet minimum tRAS before internal precharge start.
(In the case of Burst Length = 1 & 2 and BRSW mode)
TM Technology Inc. reserves the right
to change products or specifications without notice.
P.22
Publication Date: AUG. 2004
Revision: A
tm
TE
CH
T431616C
Clock suspension & DQM Operation Cycle @ CAS Latency = 2 ,Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
CS
RAS
CAS
ADDR
Ra
Ca
Cb
Cc
BA
A 1 0 /A P
Ra
DQ
Q a0
Q a1
Q a2
Q a3
Q b0
tS H Z
Q b1
D c0
D c2
tS H Z
WE
* N o te 3
DQM
R o w A c ti v e
R ead
C lo c k
S u s p e n s io n
R ead
R ead Q D M
W r it e
W r it e Q D M
W r it e Q D M
C lo c k
S u s p e n s io n
: D o n 't c a r e
*Note 1. DQM is needed to prevent bus contention.
TM Technology Inc. reserves the right
to change products or specifications without notice.
P.23
Publication Date: AUG. 2004
Revision: A
tm
TE
CH
T431616C
Read Interrupted by Precharge Command & Read Burst Stop Cycle @ Burst Length=Full Page
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
H IG H
CKE
CS
RAS
CAS
ADDR
RAa
CAa
CAb
BA
A 1 0 /A P
RAa
* N o te2
CL=2
Q A a0
1
Q A a1
Q A a2
Q A a3
Q A a4
Q A a0
Q A a1
Q A a2
Q A a3
1
Q A b0
Q A b1
Q A b2
Q A b3
Q A b4
Q A b5
Q A b0
Q A b1
Q A b2
Q A b3
Q A b4
DQ
2
CL=3
Q A a4
2
Q A b5
WE
DQM
R o w A c tiv e
(A -B a n k )
R ead (A B ank )
B u rst S to p
R ead (A B ank )
P rech arg e
(A -B a n k )
: D o n 't c a r e
*Note : 1. Burst can’t end in full page mode, so auto precharge can’t issue.
2. About the valid DQs after burst stop, it is same as the case of RAS interrupt.
Both cases are illustrated above timing diagram. See the lable 1,2 on them.
But at burst write, burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of ‘Full Page write burst stop cycle’.
3. Burst stop is valid at every burst length.
TM Technology Inc. reserves the right
to change products or specifications without notice.
P.24
Publication Date: AUG. 2004
Revision: A
tm
TE
CH
T431616C
Write Interrupted by Prechareg Command & Write Burst Stop Cycle @ Burst Length=Full Page
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
H IG H
CKE
CS
RAS
CAS
ADDR
RAa
CAa
CAb
BA
A 1 0 /A P
RAa
tB D L
tR D L
* N o te 3
DQ
D A a0
D A a1
D A a2
D A a3
D A a4
D A b0
D A b1
D A b2
D A b3
D A b4
D A b5
WE
DQM
R o w A c ti v e
(A -B a n k )
W r it e ( A B an k )
B u r s t S to p
W r it e ( A B an k )
P re c h a rg e
(A -B a n k )
: D o n 't c a r e
*Note : 1. Burst can’t end in full page mode, so auto precharge can’t issue.
2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell.
It is defined by AC parameter of tRDL.
DQM at write interrupted by precharge command is needed to prevent invalid write.
Input data after Row precharge cycle will be masked internally.
3. Burst stop is valid at every burst length.
TM Technology Inc. reserves the right
to change products or specifications without notice.
P.25
Publication Date: AUG. 2004
Revision: A
tm
TE
CH
T431616C
Burst Read Single bit Write Cycle @ Burst Length = 2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
H IG H
CKE
CS
RAS
* N o te2
CAS
ADDR
RAa
CAa
RBb
CAb
RAc
CBc
CAd
BA
A 1 0 /A P
RAa
CL=2
RBb
D A a0
RAc
D A b0
D B c0
D A b1
D A d0
D A d1
DQ
CL=3
D A a0
D A b0
D B c0
D A b1
D A d0
D A d1
W E
DQM
R o w A c tiv e
(A -B a n k )
R o w A c tiv e
(A -B a n k )
R o w A c tiv e
(A -B a n k )
W rite (A B ank )
W rite w ith A u to
P rech arg e (A B ank )
R ead (A B ank )
R e a d w ith A u to
P rech arg e (A B ank )
P rech arg e
(A -B a n k )
: D o n 't c a r e
*Note : 1. BRSW modes is enabled by setting A9 ‘High’ at MRS (Mode Register Set).
At the BRSW Mode, the burst length at write is fixed to ‘1’ regardless of programmed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not
be violated.
Auto precharge is executed at the next cycle of burst-end, so in the case of BRSW write command,
the precharge command will be issued after two clock cycle.
TM Technology Inc. reserves the right
to change products or specifications without notice.
P.26
Publication Date: AUG. 2004
Revision: A
tm
TE
CH
T431616C
Active/ Precharge Power Down Mode @ CAS latency = 2, Butsr length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SS
CLOCK
SS
SS
* N o te 2
ts s
CKE
ts s
ts s
* N o te 1
SS
* N o te 3
SS
CS
RAS
CAS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
ADDR
SS
BA
SS
SS
SS
SS
Ca
SS
SS
SS
A 1 0 /A P
SS
Ra
SS
Ra
SS
tSHZ
DQ
WE
DQM
P re c h a r g e
P o w erD o w n E n try
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
Q a0 Q a1
Q a2
R ead
R o w A c tiv e
A c tiv e
P re c h a r g e
P o w erP o w erD o w n E n try
D o w n E x it
A c tiv e
P o w erD o w n E x it
P re c h a r g e
:D o n 't c a re
*Note : 1. Both banks should be in idle state prior to entering precharge power down mode.
2. CKE should be set high at least 1CLK+tSS prior to Row active command.
3. Can not violate minimum refresh specification.(32ms)
TM Technology Inc. reserves the right
to change products or specifications without notice.
P.27
Publication Date: AUG. 2004
Revision: A
tm
TE
CH
T431616C
Self Refresh Entry & Exit Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SS
CLOCK
SS
* N o te 2
SS
* N o te 4
t R C m in
* N o te 1
* N o te 6
SS
* N o te 3
CKE
SS
tSS
SS
CS
SS
* N o te 5
SS
RAS
SS
SS
SS
SS
* N o te 7
CAS
ADDR
BA
A 1 0 /A P
H i-z
DQ
W E
DQM
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
H i-z
SS
SS
SS
SS
SS
SS
SS
SS
SS
S e lf R e fr e s h E n try
S e lf R e fr e s h E x it
A u to R e fre sh
: D o n 't c a r e
*Note : TO ENTER SELF REFRESH MODE
1.
CS , RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs inculding the system clock can be don’t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays ‘Low’.
Cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5.
CS starts from high.
6. Minimum tRC is required after CKE going high to complete self refresh exit.
7. 2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the
system uses burst refresh.
TM Technology Inc. reserves the right
to change products or specifications without notice.
P.28
Publication Date: AUG. 2004
Revision: A
tm
TE
CH
T431616C
Mode Register Set Cycle
0
1
2
3
4
Auto Refresh Cycle
5
6
0
1
2
3
4
5
6
7
8
9
10
CLOCK
SS
H IG H
H IG H
CKE
SS
SS
CS
tR P C
* N o te 2
SS
RAS
SS
* N o te 1
SS
CAS
SS
* N o te 3
ADDR
K ey
DQ
SS
SS
K ey
H i-z
H i-z
SS
SS
WE
SS
SS
DQM
SS
M RS
N ew C om m and
A u to R e fre sh
N ew C om m and
:D o n 't c a re
*Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
*Note : 1. CS , RAS , CAS & WE activation at the same clock cycle with address key will set internal
mode register.
2. Minimum 2 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
TM Technology Inc. reserves the right
to change products or specifications without notice.
P.29
Publication Date: AUG. 2004
Revision: A
tm
TE
CH
T431616C
PACKAGE DIMENSIONS
50 LEAD TSOPII (400 mil)
A
D
θ 2(4X)
A2
50
DEFAULT
A
26
R1
0.21
REF
-H-
E
1
E
R2
GAGE
A1
PLANE
25
8.78
θ
θ3 (4X)
-C1
.2.5
0.465
REF
291
B
∅ 1.5
DEFAULT
A
-C-
θ1
B
L
"A"
L1
(ZD)
b
-C-
0.10 C
e
WITH
PLATING
b
BASE METAL
SETING
PLANE
C1
C
SECTION B-B
b1
Symbol
A
A1
A2
b
b1
c
c1
D
ZD
E
E1
L
L1
e
R1
R2
θ
θ1
θ2
θ3
Min
0.05
0.95
0.30
0.30
0.12
0.10
20.82
11.56
10.03
0.40
0.12
0.12
0
0
10
10
Dimension in mm
Nom
0.10
1.00
0.35
0.127
20.95
0.875 REF
11.76
10.16
0.50
0.80 REF
0.80 BSC
15
15
Max
1.20
0.15
1.05
0.45
0.40
0.21
0.16
21.08
Min
0.002
0.037
0.012
0.012
0.005
0.004
0.820
11.96
10.29
0.60
0.455
0.394
0.016
0.25
8
20
20
0.005
0.005
0
0
10
10
TM Technology Inc. reserves the right
to change products or specifications without notice.
Dimension in inch
Nom
0.004
0.039
0.014
0.005
0.825
0.034 REF
0.463
0.400
0.020
0.031 REF
0.031 BSC
15
15
P.30
Max
0.047
0.006
0.041
0.018
0.016
0.008
0.006
0.830
0.471
0.405
0.024
0.010
8
20
20
Publication Date: AUG. 2004
Revision: A