TK75005 ADVANCED INFORMATION LOW-COST FLEXIBLE PWM CONTROLLER FEATURES APPLICATIONS ■ Can Be Used For Power Factor Correction/Line Harmonics Reduction to Meet IEC1000-3-2 Requirements ■ Maximum Duty Ratio 89% (typ.) ■ Low Standby Current for Current-Fed Start-Up ■ Current-Mode or Voltage-Mode Control ■ Internal User-Adjustable Slope Compensation ■ Pulse-by-Pulse Current Limiting ■ ■ ■ ■ Power Factor Correction Converters Off-Line Power Supplies Industrial Power Supplies Off-Line Battery Charger TK75005 DESCRIPTION DRV VCC GND EAOUT OVP EAIN 05 750 The TK75005 is an 8-pin PWM controller suitable for both voltage-mode and current-mode control. It also has advanced features not available in controllers with a higher pin count. One such feature is a sawtooth current flowing out of the feedback pin (FB), which provides a slope compensation ramp (in current mode applications) in proportion to the resistance terminating that FB pin. CT SOP-8 The TK75005 offers the same features as the TK75003 with the addition of the Error Amplifier and the Overvoltage Protection (OVP) functions, and the deletion of the Overcurrent Frequency Reduction feature. 5 7500 DRV VCC GND EAOUT OVP EAIN CT DIP-8 This PWM has features similar to the UC3842 (please refer to UC3842 Comparison Section). FB FB BLOCK DIAGRAM VCC ICT UVLO CT BANDGAP REFERENCE ICHG 175 µA 10.0 V 8.0 V OSCILLATOR fCLK IDS 1.975 mA ORDERING INFORMATION TK75005 Package Code PWM LATCH SLOPE COMPENSATION Tape/Reel Code S R OVP PACKAGE CODE TEMPERATURE RANGE TAPE/REEL CODE D: DIP-8 M: SOP-8 C: -40 TO 80 C TL: Tape Left MG: Magazine FB Q DRV OVERVOLTAGE DETECTOR Temp. Range 2.6 V CURRENT CONTROL DETECTOR EAIN 2.5 V GM STAGE 1.02 V EAOUT January 1999 TOKO, Inc. GND Page 1 TK75005 ABSOLUTE MAXIMUM RATINGS Supply Voltage (Low Impedance) ............................ 18 V Supply Voltage (ICC < 30 mA) ...................... Self Limiting Power Dissipation (Note 1) ................................ 800 mW Output Energy ........................................................... 5 µJ CT and FB Pins ........................................................ 10 V Junction Temperature ........................................... 150 °C Storage Temperature Range ................... -55 to +150 °C Operating Temperature Range ...................-20 to +80 °C Extended Temperature Range ................... -40 to +85 °C Lead Soldering Temperature (10 s) ...................... 235 °C TK75005 ELECTRICAL CHARACTERISTICS Test Conditions: VCC = 13 V, CCC = 4.7 µF, CT = 680 pF, CDRV = 1000 pF, TA = Tj = Full Operating Temperature Range, unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 0.25 0.9 mA EAIN = 2 V 12 17 mA EAIN = 3 V 14.5 19.0 mA ICC(START) Start-up Supply Current ICC(ON) Operating Supply Current VCC(ON) UVLO Voltage ON VCC Sweeps Upward 9 10 11 V VCC(OFF) UVLO Voltage OFF VCC Sweeps Downward 7 8 9 V VHYST UVLO Hysteresis 1 2.0 TA = Tj = 25 ° C 90 100 TA = Tj = Full Range 85 Current Source to VIN Pin V OSCILLATOR SECTION (CT PIN) fDRV Frequency at DRV Pin (Note 3) VCT(PK) Peak Voltage VCT(VL) Valley Voltage ICT(DIS) Discharge Current CT(MAX) Maximum Timing Capacitance 2.5 3.2 110 kHz 115 kHz 3.9 V 1.1 VCT = VCT(PK) 1.0 1.8 V 3.0 4.7 mA nF CURRENT DETECTOR, OVERVOLTAGE PROTECTION (OVP PIN) AND SLOPE COMPENSATION SECTIONS TA = Tj = 25 ° C 0.99 TA = Tj = Full Range 0.966 1.05 V 1.077 V 80 180 ns 2.60 2.69 V 2.74 V 80 180 ns -250 -205 -160 µA CT Pin = VCT(VL), TA = Tj = 25 ° C, EAOUT(HIGH) ,(Note 2) -55 -30 -5 µA CT Pin = VCT(PK), TA = Tj = 25 ° C, EAOUT(HIGH) ,(Note 2) -215 -175 -135 µA VCCD Current Control Detector Reference Voltage tCCD Propogation Delay to DRV Pin VFB steps from 0 to 2 V Overvoltage Protection Detector Reference Voltage TA = Tj = 25 ° C 2.51 VOVD TA = Tj = Full Range 2.46 tOVP Propogation Delay to DRV Pin VOVP steps from 2 to 3 V iSC(PK) Slope Compensation Peak Current CT Pin = VCT(PK), TA = Tj = 25 ° C, EAOUT(HIGH) ,(Note 2) iSC(VL) Slope Compensation Valley Current iSC(PK-VL) Slope Compensation Peak to Valley Page 2 1.02 January 1999 TOKO, Inc. TK75005 TK75005 ELECTRICAL CHARACTERISTICS (CONT.) Test Conditions: VCC = 13 V, CCC = 4.7 µF, CT = 680 pF, CDRV = 1000 pF, TA = Tj = Full Operating Temperature Range, unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS T A = T j = 25 ° C 2.43 2.50 2.57 V TA = Tj = Full Range 2.37 2.64 V ERROR AMPLIFIER AND GM STAGE SECTIONS (EAIN AND EAOUT PINS) Vref Reference Voltage IIB Input Bias Current AVD Open Loop Gain 65 1.0 µA 75 dB 2 MHz Unity Gain Bandwidth (Note 3) PSRR Power Supply Rejection Ratio (Note 3) 60 70 dB IOUT(SINK) Output Sink Current EAOUT = 1.2 V 2 6.8 mA IOUT(SOURCE) Output Source Current EAOUT = 3.5 V VOUT(HIGH) VOUT(HIGH) at EAOUT Pin EAIN @ 2 V VOUT(LOW) VOUT(LOW) at EAOUT Pin EAIN @ 3 V IGM(MAX) IOUT(MAX) at FB Pin from GM Stage EAOUT(LOW), FB @ 2 V IGM(MIN) IOUT(MIN) at FB Pin from GM Stage EAOUT(HIGH), FB @ 2 V -1.1 3.5 -1.95 -0.5 4.1 mA V 0.4 0.7 V -1.50 -1.05 mA -1.0 µA OUTPUT SECTION (DRV PIN) DDRV(MAX) Maximim Duty ratio tDRV(RISE) Rise Time tDRV(FALL) Fall Time VDRV(HIGH) Output Voltage HIGH VDRV(LOW) Output Voltage LOW 86 89 92 % 1000 pF load 25 75 ns 1000 pF load 25 75 ns IDRV = -40 mA 10.1 11.0 V IDRV = 100 mA 10.0 10.8 V IDRV = -40 mA 0.1 0.25 V IDRV = 100 mA 0.2 0.50 V IDRV = 5 mA, VIN = 6 V 0.9 1.50 V Note 1: Power dissipation for both packages (TK75005M and TK75005D) is 800 mW when mounted. Derate at 6.4 mW/°C for operation above 25 °C. Note 2: For temperature dependence refer to "Slope Compensation Peak Current vs. Temperature" graph. Note 3: Guaranteed by design; not 100% tested. January 1999 TOKO, Inc. Page 3 TK75005 TEST CIRCUIT VCC DRV 1 nF CCC 4.7 µF EAOUT GND 100 k EAIN OVP CT FB 3k CT 680pF 3k INV AMP IN TYPICAL PERFORMANCE CHARACTERISTICS FREQUENCY (kHz) ICC (mA) DEVICE ON 12 0.8 STANDBY -100 -140 1000 ISC(PK) (µA) 20 16 SLOPE COMPENSATION PEAK CURRENT vs. TEMPERATURE FREQUENCY AT DRV PIN VS. TIMING CAPACITANCE (-25 TO 85 °C) 10000 SUPPLY CURRENT vs. SUPPLY VOLTAGE 100 -220 0.4 0.0 0 4 8 12 16 10 10 20 -180 100 1000 -260 -50 10000 SUPPLY CURRENT vs. FREQUENCY AT DRV REFERENCE VOLTAGE vs. TEMPERATURE 50 2.6 40 2.56 0 50 100 TEMPERATURE (°C) CT (pF) VCC (V) SLOPE COMPENSATION RAMP 600 20 CDRV = 470 pF VFB (mV) 450 30 Vref (V) ICC (mA) CDRV = 1 nF ISC(PK) 2.52 2.48 ISC(PK) - ISC(VL) 300 150 10 0 CDRV = 0 pF 0 400 800 1200 FREQUENCY (kHz) Page 4 ISC(VL) 2.44 RFB = 3 k TO GND CT = 680 pF, EAOUT(HIGH) 0 1600 2.40 -50 0 50 TEMPERATURE (°C) 100 0 5 10 15 20 TIME (µs) January 1999 TOKO, Inc. TK75005 PIN DESCRIPTIONS DRIVE PIN (DRV) This pin drives the external MOSFET with a totem pole output stage capable of sinking or sourcing a peak current of about 1 A. In standby mode, the DRV pin can sink about 5 mA while keeping the drive pin pulled down to about 1 V. This ensures that the external MOSFET can not be inadvertently turned on by leakage currents. The maximum duty cycle of the output signal is typically 89%. GROUND PIN (GND) This pin provides ground return for the IC. OVERVOLTAGE PROTECTION INPUT PIN (OVP) This pin provides a means of turning off the external transistor drive output independent of the PWM loop. This pin is normally used for overvoltage protection, but can also be used to provide a drive disabled function. The pin is the input to comparator with its other input referenced to 2.6 V, which tracks Vref of error amp over temperature. and its output controlling the output driver of the IC. Therefore, if a voltage appears at this pin over 2.6 V, the voltage at the DRV pin drops to zero. TIMING CAPACITOR PIN (CT) The external timing capacitor is connected to the CT pin. That capacitor is the only component needed for setting the clock frequency. The frequency measured at the CT pin is the same frequency as measured at the DRV pin. As the frequency of operation increases above 200 kHz, the maximum duty cycle decreases from a typical 89% at 200 kHz to 82% at 1.6 MHz. The maximum recommended clock frequency of the device is 1.6 MHz. At normal operation, during the rising section of the timing-capacitor voltage, a trimmed internal current of 175 µA flows out from the C pin and charges the capacitor. During the falling T section of the timing-capacitor voltage, an internal current of about 1.8 mA discharges the capacitor. FEEDBACK INPUT PIN (FB) The feedback pin normally receives the sum of three signals: the switch current signal, the error signal (from the internal error amplifier and the GM stage), and a voltage ramp (from an internal sawtooth-shaped current with a peak value of about 205 µA) generated across the external terminating resistance. The switch current signal is needed January 1999 TOKO, Inc. in current-mode controlled converters and in converters with cycle-by-cycle overload protection. The error signal is needed for stabilizing the output voltage or current. The voltage ramp is needed for slope compensation (necessary for avoiding subharmonic instability in constant-frequency peak-current controlled current-mode converters above 50% duty ratio), or for Pulse Width Modulation (PWM) (in voltage-mode controlled converters). At higher clock frequencies, the bandwidth limitation of the internally-generated sawtooth-shaped current source becomes more apparent. The degree to which ramp bandwidth is tolerable depends on performance requirements at narrow pulse widths. A low impedance at the feedback pin can effectively eliminate the internallygenerated ramp effects and an external ramp can be readily created to attain higher performance at high frequencies, if desired. ERROR AMPLIFIER COMPENSATION INPUT PIN (EAIN) This pin is the inverting input of an operational amplifier which has its non-inverting input connected to 2.5 V. This is called the error amp because it amplifies the error between this pin’s voltage and 2.5 V reference, which should reflect the error in the power supply’s output regulation. The error amp provides a high gain stage so that the voltage loop gain can be high enough to provide good output voltage regulation. ERROR AMPLIFIER COMPENSATION OUTPUT PIN (EAOUT) This pin is the output of the operational amplifier mentioned in the EAIN pin description. By picking the proper resistor and capacitor network connected between pins 6 and 7, the gain and frequency response of the error amp block of the voltage loop can be set, thus providing gain and frequency compensation into the PWM voltage loop as needed. This pin also acts as the input to the GM stage of the voltage control loop. SUPPLY VOLTAGE PIN (VCC) This pin is connected to the supply voltage. The IC is in a low-current (250 µA typ.) standby mode before the supply voltage exceeds 10 V (typ.), which is the upper threshold of the undervoltage lockout circuit. The IC switches back to standby mode when the supply voltage drops below 8 V (typ.). Page 5 TK75005 THEORY OF OPERATION The TK75005 is intended for use as a highly flexible primary-side PWM controller. The TK75005 is much like the TK75003 with the addition of an error amplifier, a GM stage and an overvoltage comparator, and the deletion of the TK75003 overcurrent frequency reduction feature. The many features integrated into a simple 8-pin design allow it to be easily configured for voltage-mode or currentmode control, fixed frequency or fixed off-time operation, off-line boot-strapping, and direct drive of a power MOSFET. Using a control technique referenced in the “Application Information” section, the TK75005 can be used as a highly cost-effective controller for power factor correction. The most noteworthy integrated feature in the TK75005 is the way in which the feedback control pin is configured to receive the error signal and the current signal for currentmode control. Rather than receiving both inputs into a comparator, a single input receives both signals summed together and compares them against a fixed internal reference. This yields two desirable effects: 1) a currentlimit threshold is automatically established, and 2) the required error-signal polarity is the inverse of that of a standard two-input current-mode control system. Generally, the signal summation requires no additional external components and adds the flexibility to add more control signals if desired. timing ramp. UC3842 COMPARISON Similarities to the UC3842 1) a single-ended transistor driver output with similar drive performance 2) an inverting error amplifier referenced to 2.5 V with similar electrical characteristics 3) a maximum threshold of ~1V on the current sense voltage used to terminate the PWM pulse 4) an 8-pin SOP-8 or DIP-8 package Unique features of the TK75005 1) a multi-signal summation point at the FB pin, instead of a single function UC1842 C/S pin 2) built-in slope compensation sawtooth current coming out of the FB pin, reduced parts 3) an overvoltage protection pin compared to 2.6 V 4) switching frequency set using a single capacitor, reduced parts 5) different UVLO thresholds 10 V / 8 V 6) maximum duty cycle set at 89% Another function is integrated into the FB pin. A current ramp, which can be used to establish either the slopecompensation ramp for a current-mode control design or the voltage-comparison ramp for a voltage-mode control design, flows out of the FB pin. By adjusting the terminating resistance at the FB pin, the desired ramp magnitude is established. The switching frequency is determined by an internal current source charging an external timing capacitor. The timing capacitor is ramped between internally-fixed thresholds, valley to peak, and then quickly discharged. A fixed off-time control technique can readily be implemented by using a small transistor to keep the timing capacitor discharged during the on-time. When the on-pulse is terminated, the timing capacitor ramps up to a fixed threshold at a fixed rate to set the off-time. The Undervoltage Lockout (UVLO) feature with hysteresis minimizes the start-up current which allows a low-power boot-strap technique to be used for the housekeeping power. The duty ratio of the TK75005 is limited to approximately 89% by the time required to discharge the Page 6 January 1999 TOKO, Inc. TK75005 APPLICATIONS INFORMATION BOOST POWER FACTOR CORRECTOR APPLICATION CIRCUIT Figure 7 shows a universal-input, 100 W boost power factor corrector application circuit. The control technique is called “current-clamped control.” Both the control technique and the application circuit with waveforms are described in the paper “Low-Cost Power Factor Correction/LineHarmonics Reduction with Current-Clamped Boost Converter,” published in the conference proceedings of Power Conversion Electronics ’95/Powersystems World™ ’95. A copy of the paper can be obtained by contacting Toko. For designers who wish to explore other performance optimizations of the current-clamped boost power factor corrector, aside from the conference paper Toko offers a Mathcad© file which can accurately display current waveforms and predict power factor, harmonic distortion, and individual harmonic currents. The Mathcad file and the text which describes how to use it are available from the Colorado Springs Toko IC Design Center. The power factor corrector in Figure 7 has been optimized for general wide-range-input use. In order to obtain the same performance at power levels other than 100 W, the control components do not need to change. The power component values change as follows: C8 scales in proportion to the power level, and L1 and R8 scales in inverse proportion to the power level. Typically, although not directly related to the line-current shaping capability of the application circuit, C1 and C10 would scale in proportion to the power level. All the components in the power stage should have a current rating as needed to accommodate the power level. Below is a step-by-step design example, showing how to determine the resistance of R7 terminating the feedback pin and the resistance of the current-sense resistor R8, for the boost corrector of Figure 7. Output power: POUT = 100 W Output voltage: VOUT = 380 Vdc Minimum line voltage: VI(MIN) = 85 Vrms Efficiency at 85 Vrms: EFF = 0.93 f = 100 kHz L1 = 2.5 mH Maximum duty ratio of TK75005: DMAX = 0.88 Peak value of ramp current flowing out of the FB pin: ISC(PK) = 200 µA Threshold voltage of the current-control detector: VCCD = 0.98 V Calculations: Peak value of minimum line voltage: VI(MIN)(PK) = 2 x VI(MIN) = 120 VPK Switch duty ratio at peak of minimum line voltage: D = 1 - VI(MIN)(PK) / VOUT = 0.684 Peak-to-peak ripple current in inductor L1: I = VI(MIN)(PK) x D / (f x L1) = 0.33 A Input power at minimum line voltage: PI = POUT / EFF = 107.5 W Peak current in L1 (at peak of minimum line voltage): IL1(PK) = Assumptions: January 1999 TOKO, Inc. Switching frequency: Inductance of boost inductor: 2 x PI / VI(MIN)(PK) + I/2 = 1.95 A Resistance of resistor R7 (Note 1): R7 = DMAX x VCCD / ISC(PK) = 4.312 kohms Page 7 TK75005 APPLICATIONS INFORMATION (CONT.) Select for R7: R7 = 4.3 kohms Resistance of current-sense resistor R8 (Note 2): R8 = (VCCD - ISC(PK) x R7 x D) / IL1(PK) = 0.201 ohms Select for R8: R8 = 0.18 ohms Note 1: This value of R7 ensures that the line current will be zero around the zero-crossing of the line voltage, which is the required condition for low-distortion line current. Note 2: This value of R8 ensures that the sum of the voltage drop across R8 (caused by the peak inductor current) and the voltage drop across R 7 (caused by the instantaneous value of the stabilizing current) is equal to the threshold voltage of the current-control detector at the peak of the line voltage. F1 250 V/ 2 A TH1 10 Ω 2.5 mH t: 220 ETD-29 core gap in center leg B1 4 600 V, 1.5 A 85-265 VAC C1 0.1 F 2 L1 1 D1 1N4148 R1a 24 k 0.5 W 3 D3 HFA04TB60 R11a 200 k 0.25 W t:9 R1b 24 k 0.5 W C3 100 nF R11b 200 k 0.25 W C7 C4 100 nF 1 F R2 5.6 k D4 30 V C10 1 nF 400 V R4 C2 470 F 150 k R3 5.6 k D2 IN4148 R51a 200 k 0.25 W R51b 200 k 0.25 W R10 R9 C8 100 F 400 V 3k 100 k EAOUT EAIN VCC OVP FB DRV GND CT 380 V DC 100 W Q1 IRF840 R5 10 U1 TK75005 R52 2.43 k R6 51 C5 680 pF C6 10 nF R8 0.18 0.5 W R12 2.43 k R7 4.3 k FIGURE 7: BOOST POWER FACTOR CORRECTOR APPLICATION CIRCUIT Page 8 January 1999 TOKO, Inc. TK75005 PACKAGE OUTLINE 5 8 Marking Information Marking DIP-8 6.4 Lot Number TK75005 Country of Origin Marking xxx 4 1 + 0.3 + 0.3 3.3 0.5 min 3.8 3.3 9.5 0.25 + 0.15 - 0.05 e1 0~ 7.62 15 e 2.54 0.46 + 0.15 - 0.05 0.25 M Dimensions are shown in millimeters Tolerance: x.x = 0.2 mm (unless otherwise specified) 0.76 5 3.9 e1 8 5.4 1.27 SOP-8 e 1.27 Recommended Mount Pad 1 0.5 e 1.27 0.42 0 ~ 0.25 0.2 + 0.3 1.64 1.45 4.89 0 ~ 10 4 6.07 + 0.3 0.1 0.12 l Dimensions are shown in millimeters Tolerance: x.x = 0.2 mm (unless otherwise specified) Toko America, Inc. Headquarters 1250 Feehanville Drive, Mount Prospect, Illinois 60056 Tel: (847) 297-0070 Fax: (847) 699-7864 TOKO AMERICA REGIONAL OFFICES Midwest Regional Office Toko America, Inc. 1250 Feehanville Drive Mount Prospect, IL 60056 Tel: (847) 297-0070 Fax: (847) 699-7864 Western Regional Office Toko America, Inc. 2480 North First Street , Suite 260 San Jose, CA 95131 Tel: (408) 432-8281 Fax: (408) 943-9790 Eastern Regional Office Toko America, Inc. 107 Mill Plain Road Danbury, CT 06811 Tel: (203) 748-6871 Fax: (203) 797-1223 Semiconductor Technical Support Toko Design Center 4755 Forge Road Colorado Springs, CO 80907 Tel: (719) 528-2200 Fax: (719) 528-2375 Visit our Internet site at http://www.tokoam.com The information furnished by TOKO, Inc. is believed to be accurate and reliable. However, TOKO reserves the right to make changes or improvements in the design, specification or manufacture of its products without further notice. TOKO does not assume any liability arising from the application or use of any product or circuit described herein, nor for any infringements of patents or other rights of third parties which may result from the use of its products. No license is granted by implication or otherwise under any patent or patent rights of TOKO, Inc. January 1999 TOKO, Inc. © 1999 Toko, Inc. All Rights Reserved Page 9 IC-xxx-TK75005 0798O0.0K Printed in the USA