TI TMS470R1A128PZ-T

TMS470R1A128
16/32-Bit RISC Flash Microcontroller
www.ti.com
FEATURES
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High-Performance Static CMOS Technology
TMS470R1x 16/32-Bit RISC Core
(ARM7TDMI™)
– 28-MHz System Clock (48-MHz Pipeline
Mode)
– Independent 16/32-Bit Instruction Set
– Open Architecture With Third-Party Support
– Built-In Debug Module
– Big-Endian Format Utilized
Integrated Memory
– 128K-Byte Program Flash
• One Bank With Ten Contiguous Sectors
• Internal State Machine for Programming
and Erase
– 8K-Byte Static RAM (SRAM)
Operating Features
– Core Supply Voltage (VCC): 1.81 V–2.05 V
– I/O Supply Voltage (VCCIO): 3.0 V–3.6 V
– Low-Power Modes: STANDBY and HALT
– Extended Industrial Temperature Ranges
470+ System Module
– 32-Bit Address Space Decoding
– Bus Supervision for Memory and
Peripherals
– Analog Watchdog (AWD) Timer
– Real-Time Interrupt (RTI)
– System Integrity and Failure Detection
Zero-Pin Phase-Locked Loop (ZPLL)-Based
Clock Module With Prescaler
– Multiply-by-4 or -8 Internal ZPLL Option
– ZPLL Bypass Mode
SPNS098B – JULY 2005 – REVISED AUGUST 2006
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(1)
Six Communication Interfaces:
– Two Serial Peripheral Interfaces (SPIs)
• 255 Programmable Baud Rates
– Two Serial Communications Interfaces
(SCIs)
• 224 Selectable Baud Rates
• Asynchronous/Isosynchronous Modes
– Standard CAN Controller (SCC)
• 16-Mailbox Capacity
• Fully Compliant with CAN Protocol,
Version 2.0B
– Class II Serial Interface (C2SIa)
• Two Selectable Data Rates
• Normal Mode 10.4 Kbps and 4X Mode
41.6 Kbps
High-End Timer (HET)
– 16 Programmable I/O Channels:
• 14 High-Resolution Pins
• 2 Standard-Resolution Pins
– High-Resolution Share Feature (XOR)
– HET RAM (64-Instruction Capacity)
10-Bit Multi-Buffered ADC (MibADC)
16-Channel
– 64-Word FIFO Buffer
– Single- or Continuous-Conversion Modes
– 1.55 µs Minimum Sample and Conversion
Time
– Calibration Mode and Self-Test Features
8 External Interrupts
Flexible Interrupt Handling
11 Dedicated GIO Pins, 1 Input-Only GIO Pin,
and 38 Additional Peripheral I/Os
External Clock Prescale (ECP) Module
– Programmable Low-Frequency External
Clock (CLK)
On-Chip Scan-Base Emulation Logic, IEEE
Standard 1149.1 (1) (JTAG) Boundary-Scan
Logic
100-Pin Plastic Low-Profile Quad Flatpack
(PZ Suffix)
The test-access port is compatible with the IEEE Standard
1149.1-1990, IEEE Standard Test-Access Port and Boundary
Scan Architecture. Boundary scan is not supported on this
device.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ARM7TDMI is a trademark of Advanced RISC Machines (ARM) Limited.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2006, Texas Instruments Incorporated
TMS470R1A128
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS098B – JULY 2005 – REVISED AUGUST 2006
TMS470R1A128 100-Pin PZ Package (Top View)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
ADIN[11]
76
50
AWD
ADIN[14]
77
49
ADIN[10]
78
48
HET[18]
HET[19]
ADIN[13]
79
47
HET[20]
ADIN[9]
80
46
HET[21]
ADIN[12]
ADIN[8]
81
45
SPI2SCS
82
44
SPI2ENA
AD REFHI
83
43
SPI2SOMI
ADREFLO
84
42
SPI2SIMO
V CCAD
85
41
SPI2CLK
V SSAD
86
40
V CC
TMS
87
39
V SS
TMS2
88
38
C2SIRX
VSS
89
37
C2SITX
V CC
90
36
C2SILPN
HET[0]
91
35
HET[24]
VSS
92
34
HET[31]
V CC
93
33
SCI2TX
FLTP2
94
32
SCI2RX
FLTP1
95
31
GIOA[3]/INT[3]
V CCP
96
30
GIOA[2]/INT[2]
HET[2]
97
29
GIOA[1]/INT[1]/ECLK
HET[4]
98
28
GIOA[0]/INT[0]
HET[6]
99
27
TEST
HET[7]
100
26
TRST
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
A.
2
GIOA[0]/INT0 (pin 28) is an input-only GIO pin.
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GIOA[6]/INT[6]
3
GIOA[5]/INT[5]
GIOA[4]/INT[4]
2
GIOA[7]/INT[7]
1
(A)
TMS470R1A128
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS098B – JULY 2005 – REVISED AUGUST 2006
DESCRIPTION
The TMS470R1A128 (2) devices are members of the Texas Instruments (TI) TMS470R1x family of
general-purpose16/32-bit reduced instruction set computer (RISC) microcontrollers. The TMS470R1x
microcontroller offers high performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing
unit (CPU), resulting in a high instruction throughput while maintaining greater code efficiency. The ARM7TDMI
16/32-bit RISC CPU views memory as a linear collection of bytes numbered upwards from zero. The A128
utilizes the big-endian format, where the most significant byte of a word is stored at the lowest numbered byte
and the least significant byte at the highest numbered byte.
High-end embedded control applications demand more performance from their controllers while maintaining low
costs. The A128 RISC core architecture offers solutions to these performance and cost demands while
maintaining low power consumption.
The A128 devices contain the following:
• ARM7TDMI 16/32-Bit RISC CPU
• TMS470R1x system module (SYS) with 470+ enhancements
• 128K-byte flash
• 8K-byte SRAM
• Zero-pin phase-locked loop (ZPLL) clock module
• Analog watchdog (AWD) timer
• Real-time interrupt (RTI) module
• Two serial peripheral interface (SPI) modules
• Two serial communications interface (SCI) modules
• Standard CAN controller (SCC)
• Class II serial interface (C2SIa)
• 10-bit, 16-input channel multi-buffered analog-to-digital converter (MibADC)
• High-end timer (HET) controlling 16 I/Os
• External Clock Prescale (ECP)
• Up to 49 I/O pins and 1 input-only pin
The functions performed by the 470+ system module (SYS) include:
• Address decoding
• Memory protection
• Memory and peripherals bus supervision
• Reset and abort exception management
• Prioritization for all internal interrupt sources
• Device clock control
• Parallel signature analysis (PSA)
This data sheet includes device-specific information such as memory and peripheral select assignment, interrupt
priority, and a device memory map. For a more detailed functional description of the SYS module, see the
TMS470R1x System Module Reference Guide (literature number SPNU189).
The A128 memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte,
halfword, and word modes.
The flash memory on the A128 devices is a nonvolatile, electrically erasable and programmable memory
implemented with a 32-bit-wide data bus interface.The flash operates with a system clock frequency of up to 28
MHz. In pipeline mode, the flash operates with a system clock frequency of up to 48 MHz. For more detailed
information on the flash, see the F05 flash section of this data sheet and the TMS470R1x F05 Flash Reference
Guide (literature number SPNU213).
(2)
Throughout the remainder of this document, the TMS470R1A128 device name will be referred to as either the full device name,
TMS470R1A128, or as A128.
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TMS470R1A128
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS098B – JULY 2005 – REVISED AUGUST 2006
The A128 devices have six communication interfaces: two SPIs, two SCIs, an SCC, and a C2SIa. The SPI
provides a convenient method of serial interaction for high-speed communications between similar shift-register
type devices. The SCI is a full-duplex, serial I/O interface intended for asynchronous communication between
the CPU and other peripherals using the standard non-return-to-zero (NRZ) format. The SCC uses a serial,
multimaster communication protocol that efficiently supports distributed real-time control with robust
communication rates of up to 1 megabit per second (Mbps). The SCC is ideal for applications operating in noisy
and harsh environments (e.g., automotive and industrial fields) that require reliable serial communication or
multiplexed wiring. The C2SIa allows the A128 to transmit and receive messages on a class II network following
an SAE J1850 standard. (3)
For more detailed functional information on the C2SIa peripheral, see the TMS470R1x Class II Serial Interface
(C2SIa) Reference Guide (literature number SPNU218).
The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications.
The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an
attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well suited
for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses.
For more detailed functional information on the HET, see the TMS470R1x High-End Timer (HET) Reference
Guide (literature number SPNU199).
The A128 HET peripheral contains the XOR-share feature. This feature allows two adjacent HET high-resolution
channels to be XORed together, making it possible to output smaller pulses than a standard HET. For more
detailed information on the HET XOR-share feature, see the TMS470R1x High-End Timer (HET) Reference
Guide (literature number SPNU199).
The A128 devices have a 10-bit-resolution sample-and-hold MibADC. The MibADC channels can be converted
individually or can be grouped by software for sequential conversion sequences. There are three separate
groupings, two of which are triggerable by an external event. Each sequence can be converted once when
triggered or configured for continuous conversion mode. For more detailed functional information on the
MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature
number SPNU206).
The zero-pin phase-locked loop (ZPLL) clock module contains a phase-locked loop, a clock-monitor circuit, a
clock-enable circuit, and a prescaler (with prescale values of 1–8). The function of the ZPLL is to multiply the
external frequency reference to a higher frequency for internal use. The ZPLL provides ACLK to the system
(SYS) module. The SYS module subsequently provides system clock (SYSCLK), real-time interrupt clock
(RTICLK), CPU clock (MCLK), and peripheral interface clock (ICLK) to all other A128 device modules. For more
detailed functional information on the ZPLL, see the TMS470R1x Zero-Pin Phase-Locked Loop (ZPLL) Clock
Module Reference Guide (literature number SPNU212).
NOTE:
ACLK should not be confused with the MibADC internal clock, ADCLK. ACLK is the
continuous system clock from an external resonator/crystal reference.
The A128 devices also have an external clock prescaler (ECP) module that when enabled, outputs a continuous
external clock (ECLK) on a specified GIO pin. The ECLK frequency is a user-programmable ratio of the
peripheral interface clock (ICLK) frequency. For more detailed functional information on the ECP, see the
TMS470R1x External Clock Prescaler (ECP) Reference Guide (literature number SPNU202).
(3)
4
SAE Standard J1850 Class B Data Communication Network Interface
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TMS470R1A128
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS098B – JULY 2005 – REVISED AUGUST 2006
Device Characteristics
The TMS470R1A128 devices are a derivative of the F05 system emulation device SE470R1VB8AD. Table 1
identifies all the characteristics of the TMS470R1A128 devices except the SYSTEM and CPU, which are
generic.
Table 1. Device Characteristics
CHARACTERISTICS
DEVICE DESCRIPTION
COMMENTS
MEMORY
For the number of memory selects on this device, see the "Memory Selection Assignment" table, Table 3.
INTERNAL
MEMORY
Flash is pipeline-capable.
The A128 RAM is implemented in one 8K-byte array selected by two
memory-select signals (see the "Memory Selection Assignment"
table, Table 3).
128K-Byte flash
8K-Byte SRAM
PERIPHERALS
For the device-specific interrupt priority configurations, see the Interrupt Priority table (Table 6). For the 1K-byte peripheral address ranges
and their peripheral selects, see the "A128 Peripherals, System Module, and Flash Base Addresses" table, Table 5).
CLOCK
ZPLL Zero-pin PLL has no external loop filter pins.
GENERAL-PURPOSE
I/Os
11 I/O
1 Input only
ECP
YES
C2SIa
1
SCI
1 (3-pin)
1 (2-pin)
CAN
(HECC and/or SCC)
1 SCC
SPI
(5-pin, 4-pin or 3-pin)
2 (5-pin)
Port A has 8 external pins, and Port B has 4 external pins.
SCI2 has no external clock pin, only transmit/receive pins (SCI2TX
and SCI2RX).
Standard CAN controller
The A128 devices have both the logic and registers for a full 32-I/O
HET implemented, even though not all 32 pins are available
externally.
The high-resolution (HR) SHARE feature allows even-numbered HR
pins to share the next higher odd-numbered HR pin structures. This
HR sharing is independent of whether or not the odd pin is available
externally. If an odd pin is available externally and shared, then the
odd pin can only be used as a general-purpose I/O. For more
information on HR SHARE, see the TMS470R1x High-End Timer
(HET) Reference Guide (literature number SPNU199).
HET with XOR Share
16 I/O
HET RAM
64-Instruction Capacity
MibADC
10-bit, 16-channel
64-word FIFO
CORE VOLTAGE
1.81–2.06 V
I/O VOLTAGE
3.0–3.6 V
PINS
100
PACKAGE
PZ
Both the logic and registers for a full 16-channel MibADC are
present.
When used from -40°C to 85°C, the core voltage range for A128
devices is 1.70–2.06 V.
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TMS470R1A128
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS098B – JULY 2005 – REVISED AUGUST 2006
Functional Block Diagram
VCCP
FLTP1
FLTP2
OSCIN
FLASH
128K Bytes
(10 Sectors)
RAM
(8K Bytes)
ZPLL
OSCOUT
Crystal
External Pins
External Pins
PLLDIS
CPU Address/Data Bus
ADIN[15:0]
ADEVT
MibADC
with
64-Word
FIFO
TRST
TMS470R1x
CPU
TCK
AD REFHI
AD REFLO
VCCAD
VSSAD
TDI
TDO
Expansion Address/Data Bus
TMS
TMS2
TMS470R1x 470+ SYSTEM MODULE
RST
AWD
TEST
PORRST
CLKOUT
HET with
XOR Share
(64-Word)
SCC
HET[31,24,21:18,
13:10,8:6,4,2,0]
CANSTX
CANSRX
SCI1CLK
SCI1
SCI1TX
SCI1RX
SCI2
SCI2TX
SCI2RX
C2SITX
C2SIa
C2SIRX
6
SPI2
SPI1
SPI1SCS
SPI1ENA
SPI1SIMO
SPI1SOMI
SPI1CLK
GIOB[3:0]
GIOA[0]/INT[0]
A.
GIOA[7:2]/INT[7:2]
GIO
ECP
(A)
GIOA[1]/INT[1]/
ECLK
SPI2SCS
SPI2ENA
SPI2SIMO
SPI2SOMI
SPI2CLK
C2SILPN
GIOA[0]/INT[0] is an input-only GIO pin.
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16/32-Bit RISC Flash Microcontroller
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SPNS098B – JULY 2005 – REVISED AUGUST 2006
Table 2. Terminal Functions
TERMINAL
NAME
PIN
NUMBER
TYPE (1) (2)
INTERNAL
PULLUP/
PULLDOWN (3)
DESCRIPTION
HIGH-END TIMER (HET)
HET[0]
91
HET[2]
97
HET[4]
98
HET[6]
99
HET[7]
100
HET[8]
55
HET[10]
20
HET[11]
19
HET[12]
18
HET[13]
17
HET[18]
49
HET[19]
48
HET[20]
47
HET[21]
46
HET[24]
35
HET[31]
34
CANSRX
59
3.3-V I/O
CANSTX
60
3.3-V I/O
3.3-V I/O
IPD (20 µA)
The A128 devices have both the logic and registers for a full 32-I/O HET
implemented, even though not all 32 pins are available externally.
Timer input capture or output compare. The HET[31:0] applicable pins
can be programmed as general-purpose input/output (GIO) pins.
HET[21:18, 13:10, 8, 7, 6, 4, 2, 0] are high-resolution pins and HET[31,
24] are standard-resolution pins for A128.
The high-resolution (HR) SHARE feature allows even HR pins to share
the next higher odd HR pin structures. This HR sharing is independent of
whether or not the odd pin is available externally. If an odd pin is
available externally and shared, then the odd pin can only be used as a
general-purpose I/O.
For more information on HR SHARE, see the TMS470R1x High-End
Timer Reference Guide (literature number SPNU199).
STANDARD CAN CONTROLLER (SCC)
SCC receive pin or GIO pin
IPU (20 µA)
SCC transmit pin or GIO pin
CLASS II SERIAL INTERFACE (C2SIa)
C2SILPN
36
3.3-V 1/O
C2SIRX
38
3.3-V I/O
C2SITX
37
3.3-V I/O
(1)
(2)
(3)
IPD (20 µA)
C2SIa module loopback enable pin or GIO pin
C2SIa module receive data input pin or GIO pin
IPD (20 µA)
C2SIa module transmit data input pin or GIO pin
I = input, O = output, PWR = power, GND = ground, REF = reference voltage, NC = no connect
All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST
state.)
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TMS470R1A128
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS098B – JULY 2005 – REVISED AUGUST 2006
Table 2. Terminal Functions (continued)
TERMINAL
NAME
PIN
NUMBER
TYPE (1) (2)
INTERNAL
PULLUP/
PULLDOWN (3)
DESCRIPTION
GENERAL-PURPOSE I/O (GIO)
GIOA[0]/
INT0
28
GIOA[1]/
INT1/ECL
K
29
GIOA[2]/
INT2
30
GIOA[3]/
INT3
31
GIOA[4]/
INT4
25
GIOA[5]/
INT5
24
GIOA[6]/
INT6
23
GIOA[7]/
INT7
22
GIOB[0]
16
GIOB[1]
15
GIOB[2]
14
GIOB[3]
13
3.3-V I
IPD (20 µA)
3.3-V I/O
General-purpose input/output pins.
GIOA[0]/INT[0] is an input-only pin. GIOA[7:0]/INT[7:0] are
interrupt-capable pins.
GIOA[1]/INT[1]/ECLK pin is multiplexed with the external clock-out
function of the external clock prescale (ECP) module.
MULTI-BUFFERED ANALOG-TO-DIGITAL CONVERTER (MibADC)
8
ADEVT
66
ADIN[0]
75
ADIN[1]
74
ADIN[2]
73
ADIN[3]
72
ADIN[4]
71
ADIN[5]
69
ADIN[6]
68
ADIN[7]
67
ADIN[8]
82
ADIN[9]
80
ADIN[10]
78
ADIN[11]
76
ADIN[12]
81
ADIN[13]
79
ADIN[14]
77
ADIN[15]
70
ADREFHI
3.3-V I/O
IPD (20 µA)
MibADC event input. ADEVT can be programmed as a GIO pin.
3.3-V I
16-channel MibADC.
MibADC analog input pins
83
3.3-V
REF I
MibADC module high-voltage reference input
ADREFLO
84
GND
REF I
MibADC module low-voltage reference input
VCCAD
85
3.3-V PWR
VSSAD
86
GND
MibADC analog supply voltage
MibADC analog ground reference
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16/32-Bit RISC Flash Microcontroller
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Table 2. Terminal Functions (continued)
TERMINAL
NAME
PIN
NUMBER
TYPE (1) (2)
INTERNAL
PULLUP/
PULLDOWN (3)
DESCRIPTION
SERIAL PERIPHERAL INTERFACE 1 (SPI1)
SPI1CLK
5
SPI1 clock. SPI1CLK can be programmed as a GIO pin.
SPI1ENA
1
SPI1 chip enable. SPI1ENA can be programmed as a GIO pin.
SPI1SCS
2
SPI1 slave chip select. SPI1SCS can be programmed as a GIO pin.
3.3-V I/O
IPD (20 µA)
SPI1SIMO
3
SPI1 data stream. Slave in/master out. SPI1SIMO can be programmed
as a GIO pin.
SPI1SOMI
4
SPI2CLK
41
SPI2 clock. SPI2CLK can be programmed as a GIO pin.
SPI2ENA
44
SPI2 chip enable. SPI2ENA can be programmed as a GIO pin.
SPI2SCS
45
SPI2SIMO
42
SPI2SOMI
43
OSCIN
8
1.8-V I
Crystal connection pin or external clock input
OSCOUT
7
1.8-V O
External crystal connection pin
PLLDIS
51
3.3-V I
SCI1CLK
61
3.3-V I/O
IPD (20 µA)
SCI1 clock. SCI1CLK can be programmed as a GIO pin.
SCI1RX
63
3.3-V I/O
IPU (20 µA)
SCI1 data receive. SCI1RX can be programmed as a GIO pin.
SCI1TX
62
3.3-V I/O
IPU (20 µA)
SCI1 data transmit. SCI1TX can be programmed as a GIO pin.
SPI1 data stream. Slave out/master in. SPI1SOMI can be programmed
as a GIO pin.
SERIAL PERIPHERAL INTERFACE 2 (SPI2)
SPI2 slave chip select. SPI2SCS can be programmed as a GIO pin.
3.3-V I/O
IPD (20 µA)
SPI2 data stream. Slave in/master out. SPI2SIMO can be programmed
as a GIO pin.
SPI2 data stream. Slave out/master in. SPI2SOMI can be programmed
as a GIO pin.
ZERO-PIN PHASE-LOCKED LOOP (ZPLL)
IPD (20 µA)
Enable/disable the ZPLL. The ZPLL can be bypassed and the oscillator
becomes the system clock. If not in bypass mode, TI recommends that
PLLDIS be connected to ground or pulled down to ground by an external
resistor.
SERIAL COMMUNICATIONS INTERFACE 1 (SCI1)
SERIAL COMMUNICATIONS INTERFACE 2 (SCI2)
SCI2RX
32
3.3-V I/O
IPU (20 µA)
SCI2 data receive. SCI2RX can be programmed as a GIO pin.
SCI2TX
33
3.3-V I/O
IPU (20 µA)
SCI2 data transmit. SCI2TX can be programmed as a GIO pin.
SYSTEM MODULE (SYS)
CLKOUT
58
3.3-V I/O
IPD (20 µA)
Bidirectional pin. CLKOUT can be programmed as a GIO pin or the
output of SYSCLK, ICLK, or MCLK.
PORRST
21
3.3-V I
IPD (20 µA)
Input master chip power-up reset. External VCC monitor circuitry must
assert a power-on reset.
IPU (20 µA)
Bidirectional reset. The internal circuitry can assert a reset, and an
external system reset can assert a device reset.
On RST, the output buffer is implemented as an open drain (drives low
only).
To ensure an external reset is not arbitrarily generated, TI recommends
that an external pullup resistor be connected to RST .
RST
10
3.3-V I/O
WATCHDOG/REAL-TIME INTERRUPT (WD/RTI)
AWD
50
3.3-V I/O
IPD (20 µA)
Analog watchdog reset. The AWD pin provides a system reset if the WD
KEY is not written in time by the system, providing an external RC
network circuit is connected. If the user is not using AWD, TI
recommends that AWD be connected to ground or pulled down to ground
by an external resistor.
For more details on the external RC network circuit, see the TMS470R1x
System Module Reference Guide (literature number SPNU189) and the
application note Analog Watchdog Resistor, Capacitor and Discharge
Interval Selection Constraints (literature number SPNA005).
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16/32-Bit RISC Flash Microcontroller
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SPNS098B – JULY 2005 – REVISED AUGUST 2006
Table 2. Terminal Functions (continued)
TERMINAL
NAME
PIN
NUMBER
TYPE (1) (2)
INTERNAL
PULLUP/
PULLDOWN (3)
DESCRIPTION
TEST/DEBUG (T/D)
TCK
54
3.3-V I
IPD (20 µA)
Test clock. TCK controls the test hardware (JTAG).
TDI
52
3.3-V I
IPU (20 µA)
Test data in. TDI inputs serial data to the test instruction register, test
data register, and programmable test address (JTAG).
TDO
53
3.3-V O
IPD (20 µA)
Test data out. TDO outputs serial data from the test instruction register,
test data register, identification register, and programmable test address
(JTAG).
TEST
27
3.3-V I
IPD (20 µA)
Test enable. Reserved for internal use only. TI recommends that TEST
be connected to ground or pulled down to ground by an external resistor.
TMS
87
3.3-V I
IPU (20 µA)
Serial input for controlling the state of the CPU test access port (TAP)
controller (JTAG).
TMS2
88
3.3-V I
IPU (20 µA)
Serial input for controlling the second TAP. TI recommends that TMS2 be
connected to VCCIO or be pulled up to VCCIO by an external resistor.
TRST
26
3.3-V I
IPD (20 µA)
Test hardware reset to TAP1 and TAP2. IEEE Standard 1149-1 (JTAG)
Boundary-Scan Logic. TI recommends that TRST be pulled down to
ground by an external resistor.
FLTP1
95
FLTP2
94
VCCP
96
FLASH
NC
3.3-V PWR
Flash test pads 1 and 2. For proper operation, these pins must not be
connected (no connect [NC]).
Flash external pump voltage (3.3 V)
SUPPLY VOLTAGE CORE (1.8 V)
9
40
VCC
65
1.8-V PWR
Core logic supply voltage
90
93
SUPPLY VOLTAGE DIGITAL I/O (3.3 V)
VCCIO
12
57
3.3-V PWR
Digital I/O supply voltage
SUPPLY GROUND CORE
6
39
VSS
64
GND
Core supply ground reference
89
92
SUPPLY GROUND DIGITAL I/O
VSSIO
10
11
56
GND
Digital I/O supply ground reference
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A128 Device-Specific Information
Memory
Figure 1 shows the memory map of the TMS470R1A128 device.
0xFFFF_FFFF
Memory (4G Bytes)
SYSTEM
0xFFFF_FFFF
0xFFFF_FD00
System Module Control Registers
(512K Bytes)
Reserved
0xFFF8_0000
0xFFF7_FFFF
0xFFF0_0000
0xFFEF_FFFF
0xFFE8_C000
0xFFE8_BFFF
0xFFE8_8000
0xFFE8_7FFF
0xFFE8_4024
0xFFE8_4023
0xFFE8_4000
0xFFE8_3FFF
HET
Peripheral Control Registers
(512K Bytes)
SPI1
SCI2
Reserved
SCI1
Flash Control Registers
MibADC
Reserved
GIO/ECP
MPU Control Registers
Reserved
SCC
Reserved
SCC RAM
0xFFE0_0000
Reserved
SPI2
Reserved
RAM
(8K Bytes)
C2SIa
Reserved
Program
and
Data Area
FLASH
(128K Bytes)
10 Sectors
0xFFF8_0000
0xFFF7_FC00
0xFFF7_F800
0xFFF7_F500
0xFFF7_F400
0xFFF7_F000
0xFFF7_EC00
0xFFF7_E400
0xFFF7_E000
0xFFF7_DC00
0xFFF7_D800
0xFFF7_D400
0xFFF7_CC00
0xFFF7_C800
0xFFF0_0000
0x0000_001F
FIQ
HET RAM
(1K Byte)
IRQ
Reserved
Data Abort
Prefetch Abort
0x0000_0020
0x0000_001F
0x0000_0000
Software Interrupt
Undefined Instruction
Exception, Interrupt, and
Reset Vectors
Reset
0x0000_001C
0x0000_0018
0x0000_0014
0x0000_0010
0x0000_000C
0x0000_0008
0x0000_0004
0x0000_0000
A.
Memory addresses are configurable by the system (SYS) module within the range of 0x0000_0000 to 0xFFE0_0000.
B.
The CPU registers are not part of the memory map.
Figure 1. Memory Map
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Memory Selects
Memory selects allow the user to address memory arrays (i.e., flash, RAM, and HET RAM) at user-defined
addresses. Each memory select has its own set (low and high) of memory base address registers (MFBAHRx
and MFBALRx) that together define the array's starting (base) address, block size, and protection.
The base address of each memory select is configurable to any memory address boundary that is a multiple of
the decoded block size. For more information on how to control and configure these memory select registers,
see the bus structure and memory sections of the TMS470R1x System Module Reference Guide (literature
number SPNU189).
For the memory selection assignments and the memory selected, see Table 3.
Table 3. Memory Selection Assignment
(1)
MEMORY
SELECT
MEMORY SELECTED
(ALL INTERNAL)
0 (fine)
FLASH
1 (fine)
FLASH
2 (fine)
RAM
3 (fine)
RAM
4 (fine)
HET RAM
MEMORY
SIZE
128K
8K (1)
MPU
MEMORY BASE ADDRESS REGISTER
NO
MFBAHR0 and MFBALR0
NO
MFBAHR1 and MFBALR1
YES
MFBAHR2 and MFBALR2
YES
MFBAHR3 and MFBALR3
1K
STATIC MEM
CTL REGISTER
MFBAHR4 and MFBALR4
SMCR1
The starting addresses for both RAM memory-select signals cannot be offset from each other by a multiple of the user-defined block
size in the memory-base address register.
RAM
The A128 devices contain 8K bytes of internal static RAM configurable by the SYS module to be addressed
within the range of 0x0000_0000 to 0xFFE0_0000. This RAM is implemented in one 8K-byte array selected by
two memory-select signals. This configuration imposes an additional constraint on the memory map for RAM;
the starting addresses for both RAM memory selects cannot be offset from each other by the multiples of the
size of the physical RAM (i.e., 8K bytes for the A128 device). The RAM is addressed through memory selects 2
and 3.
The RAM can be protected by the memory protection unit (MPU) portion of the SYS module, allowing the user
finer blocks of memory protection than is allowed by the memory selects. The MPU is ideal for protecting an
operating system while allowing access to the current task. For more detailed information on the MPU portion of
the SYS module and memory protection, see the memory section of the TMS470R1x System Module Reference
Guide (literature number SPNU189).
F05 flash
The F05 flash memory is a nonvolatile electrically erasable and programmable memory implemented with a
32-bit-wide data bus interface. The F05 flash has an external state machine for programming and erase
functions. See the flash read and flash program and erase sections.
NOTE:
Flash must be mapped to a boundary of zero or a multiple of 0x00100000. RAM
cannot be mapped into the same 0x00100000 space.
flash protection keys
The A128 devices provide flash protection keys. These four 32-bit protection keys prevent
program/erase/compaction operations from occurring until after the four protection keys have been matched by
the CPU loading the correct user keys into the FMPKEY control register. The protection keys on the A128 are
located in the last four words of the first 8K sector. For more detailed information on the flash protection keys
and the FMPKEY control register, see the protection keys portions of the TMS470R1x F05 Flash Reference
Guide (literature number SPNU213).
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flash read
The A128 Flash memory is configurable by the SYS module to be addressed within the range of 0x0000_0000
to 0xFFE0_0000. The flash is addressed through memory selects 0 and 1.
NOTE:
The flash external pump voltage (VCCP) is required for all operations (program, erase,
and read).
flash pipeline mode
When in pipeline mode, the flash operates with a system clock frequency of up to 48 MHz (versus a system
clock in normal mode of up to 28 MHz). Flash in pipeline mode is capable of accessing 64-bit words and
provides two 32-bit pipelined words to the CPU. Also in pipeline mode, the flash can be read with no wait states
when memory addresses are contiguous (after the initial 1-or 2-wait-state reads).
NOTE:
After a system reset, pipeline mode is disabled (the ENPIPE bit FMREGOPT[0] = 0).
In other words, the A128 devices power up and come out of reset in non-pipeline
mode. Furthermore, setting the flash configuration mode bit (GLBCTRL[4]) will
override pipeline mode.
flash program and erase
The A128 device flash has one 128K-byte bank that consists of ten sectors. These ten sectors are shown in
Table 4.
Table 4. Flash Sectors
SECTOR NO.
SEGMENT
LOW ADDRESS
HIGH ADDRESS
0
8K Bytes
0x0000_0000
0x0000_1FFF
1
8K Bytes
0x0000_2000
0x0000_3FFF
2
16K Bytes
0x0000_4000
0x0000_7FFF
3
16K Bytes
0x0000_8000
0x0000_BFFF
4
16K Bytes
0x0000_C000
0x0000_FFFF
5
16K Bytes
0x0001_0000
0x0001_3FFF
6
16K Bytes
0x0001_4000
0x0001_7FFF
7
16K Bytes
0x0001_8000
0x0001_BFFF
8
8K Bytes
0x0001_C000
0x0001_DFFF
9
8K Bytes
0x0001_E000
0x0001_FFFF
The minimum size for an erase operation is one sector. The maximum size for a program operation is one 16-bit
word.
NOTE:
The flash external pump voltage (VCCP) is required for all operations (program, erase,
and read).
For more detailed information on flash program and erase operations, see the TMS470R1x F05 Flash Reference
Guide (literature number SPNU213).
HET RAM
The A128 devices contain HET RAM. The HET RAM has a 64-instruction capability. The HET RAM is
configurable by the SYS module to be addressed within the range of 0x0000_0000 to 0xFFE0_0000. The HET
RAM is addressed through memory select 4.
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Peripheral Selects and Base Addresses
The A128 devices use 10 of the 16 peripheral selects to decode the base addresses of the peripherals. These
peripheral selects are fixed and transparent to the user since they are part of the decoding scheme used by the
SYS module.
Control registers for the peripherals, SYS module, and flash begin at the base addresses shown in Table 5.
Table 5. TMS470R1A128 Peripherals, System Module, and Flash Base Addresses
CONNECTING MODULE
PERIPHERAL SELECTS
ENDING ADDRESS
0xFFFF_FD00
0xFFFF_FFFF
Reserved
0xFFF8_0000
0xFFFF_FCFF
N/A
HET
0xFFF7_FC00
0xFFF7_FFFF
PS[0]
SPI1
0xFFF7_F800
0xFFF7_FBFF
PS[1]
SCI2
0XFFF7_F500
0XFFF7_F7FF
SCI1
0xFFF7_F400
0xFFF7_F4FF
SYSTEM
14
ADDRESS RANGE
BASE ADDRESS
N/A
PS[2]
ADC
0xFFF7_F000
0xFFF7_F3FF
PS[3]
GIO/ECP
0xFFF7_EC00
0xFFF7_EFFF
PS[4]
Reserved
0xFFF7_E400
0xFFF7_EBFF
PS[5]–PS[6]
SCC
0xFFF7_E000
0xFFF7_E3FF
PS[7]
SCC RAM
0xFFF7_DC00
0xFFF7_DFFF
PS[8]
Reserved
0XFFF7_D800
0XFFF7_DBFF
PS[9]
SPI2
0XFFF7_D400
0XFFF7_D7FF
PS[10]
Reserved
0xFFF7_CC00
0xFFF7_D3FF
PS[11]–PS[12]
C2SIA
0XFFF7_C800
0XFFF7_CBFF
PS[13]
Reserved
0xFFF7_C000
0xFFF7_C7FF
PS[14]–PS[15]
Reserved
0xFFF0_0000
0xFFF7_BFFF
N/A
Flash Control Registers
0xFFE8_8000
0xFFE8_BFFF
N/A
MPU Control Registers
0xFFE8_4000
0xFFE8_4023
N/A
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Interrupt Priority
The central interrupt manager (CIM) portion of the SYS module manages the interrupt requests from the device
modules (i.e., SPI1 or SPI2, SCI1 or SCI2, and RTI, etc.).
Although the CIM can accept up to 32 interrupt request signals, the A128 devices only use 21 of those interrupt
request signals. The request channels are maskable so that individual channels can be selectively disabled. All
interrupt requests can be programmed in the CIM to be of either type:
• Fast interrupt request (FIQ)
• Normal interrupt request (IRQ)
The precedences of request channels decrease with ascending channel order in the CIM (0 [highest] and 31
[lowest] priority). For these channel priorities and the associated modules, see Table 6.
Table 6. Interrupt Priority
MODULES
INTERRUPT SOURCES
INTERRUPT LEVEL/CHANNEL
SPI1
SPI1 end-transfer/overrun
0
RTI
COMP2 interrupt
1
RTI
COMP1 interrupt
2
RTI
TAP interrupt
3
SPI2
SPI2 end-transfer/overrun
4
GIO
Interrupt A
5
Reserved
HET
6
Interrupt A
Reserved
SCI1/SCI2
7
8
SCI1/SCI2 error interrupt
9
SCI1
SCI1 receive interrupt
10
C2SIa
C2SIa interrupt
11
Reserved
12
Reserved
13
SCC
Interrupt A
Reserved
14
15
MibADC
End event conversion
16
SCI2
SCI2 receive interrupt
17
Reserved
18
Reserved
SCI1
System
19
SCI1 transmit interrupt
20
SW interrupt (SSI)
21
Reserved
HET
22
Interrupt B
Reserved
23
24
SCC
Interrupt B
25
SCI2
SCI2 transmit interrupt
26
MibADC
End Group1 conversion
27
Reserved
GIO
MibADC
28
Interrupt B
29
End Group2 conversion
30
Reserved
31
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MibADC
The multi-buffered analog-to-digital converter (MibADC) accepts an analog signal and converts the signal to a
10-bit digital value.
The A128 MibADC module can function in two modes: compatibility mode, where its programmer's model is
compatible with the TMS470R1x ADC module and its digital results are stored in digital result registers; or in
buffered mode, where the digital result registers are replaced with three FIFO buffers, one for each conversion
group [event, group1 (G1), and group2 (G2)]. In buffered mode, the MibADC buffers can be serviced by
interrupts.
MibADC Event Trigger Enhancements
The MibADC includes two major enhancements over the event-triggering capability of the TMS470R1x ADC.
• Both group1 and the event group can be configured for event-triggered operation, providing up to two
event-triggered groups.
• The trigger source and polarity can be selected individually for both group1 and the event group from the
three options identified in Table 7.
Table 7. MibADC Event Hookup Configuration
EVENT #
SOURCE SELECT BITS for G1 or EVENT
(G1SRC[1:0] or EVSRC[1:0])
SIGNAL PIN NAME
EVENT1
00
ADEVT
EVENT2
01
HET18
EVENT3
10
HET19
EVENT4
11
reserved
For group1, these event-triggered selections are configured via the group1 source select bits (G1SRC[1:0]) in
the AD event source register (ADEVTSRC[5:4]). For the event group, these event-triggered selections are
configured via the event group source select bits (EVSRC[1:0]) in the AD event source register
(ADEVTSRC[1:0]).
For more detailed functional information on the MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital
Converter (MibADC) Reference Guide (literature number SPNU206).
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Documentation Support
Extensive documentation supports all of the TMS470 microcontroller family of devices. The types of
documentation available include data sheets with design specifications; complete user's guides for all devices
and development support tools; and hardware and software application notes. Useful reference documentation
includes:
• Bulletin
– TMS470 Microcontroller Family Product Bulletin (literature number SPNB086)
• User's Guides
– TMS470R1x System Module Reference Guide (literature number SPNU189)
– TMS470R1x GeneralPurpose Input/Output (GIO) Reference Guide (literature number SPNU192)
– TMS470R1x Direct Memory Access (DMA) Controller Reference Guide (literature number SPNU194)
– TMS470R1x Serial Peripheral Interface (SPI) Reference Guide (literature number SPNU195)
– TMS470R1x Serial Communication Interface (SCI) Reference Guide (literature number SPNU196)
– TMS470R1x Controller Area Network (CAN) Reference Guide (literature number SPNU197)
– TMS470R1x HighEnd Timer (HET) Reference Guide (literature number SPNU199)
– TMS470R1x External Clock Prescale (ECP) Reference Guide (literature number SPNU202)
– TMS470R1x MultiBuffered AnalogtoDigital (MibADC) Reference Guide (literature number SPNU206)
– TMS470R1x ZeroPin PhaseLocked Loop (ZPLL) Clock Module Reference Guide (literature number
SPNU212)
– TMS470R1x F05 Flash Reference Guide (literature number SPNU213)
– TMS470R1x Class II Serial Interface B (C2SIb) Reference Guide (literature number SPNU214)
– TMS470R1x Class II Serial Interface A (C2SIa) Reference Guide (literature number SPNU218)
– TMS470R1x Inter-Integrated Circuit (I2C) Reference Guide (literature number SPNU223)
– TMS470 Peripherals Overview Reference Guide (literature number SPNU248)
• Errata Sheet:
– TMS470R1A128 TMS470 Microcontrollers Silicon Errata (literature number SPNZ132)
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Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP
devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS
(e.g., TMS470R1A128). Texas Instruments recommends two of three possible prefix designators for its support
tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering
prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX
Experimental device that is not necessarily representative of the final device's electrical
specifications
TMP
Final silicon die that conforms to the device's electrical specifications but has not completed quality
and reliability verification
TMS
Fully qualified production device
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS
Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability
of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
Figure 2 illustrates the numbering and symbol nomenclature for the TMS470R1x family.
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TMS 470 R1 A 128
PZ
T
PREFIX
TMS = Fully Qualified Device
OPTIONS
FAMILY
470 = TMS470 RISC − Embedded
Microcontroller Family
ARCHITECTURE
R1 = ARM7TDM1 CPU
TEMPERATURE RANGE
T = −40°C to 105°C
Q = −40°C to 125°C
PZ = 100-pin Low-Profile Quad Flatpack (LQFP)
DEVICE TYPE A
With 128K−Bytes Flash Memory:
48-MHz Frequency
1.8V Core, 3.3V I/O
Flash Program Memory
ZPLL Clock
8K−Byte Static RAM
1K−Byte HET RAM (64 Instructions)
AWD
RTI
10−bit, 16−input MibADC
Two SPI Modules
Two SCI Modules
C2SIa
CAN [SCC]
HET, 16 Channels
ECP
REVISION CHANGE
Blank = Original
FLASH MEMORY
128 = 128K-Bytes Flash Memory
Figure 2. TMS470R1x Family Nomenclature
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Device Identification Code Register
The device identification code register identifies the silicon version, the technology family (TF), a ROM or flash
device, and an assigned device-specific part number (see Figure 3 and Table 8). The A128 device identification
code register value is 0xn83F.
Figure 3. TMS470 Device ID Bit Allocation Register [offset = FFFF_FFFO]
31
16
Reserved
15
12
11
10
9
3
2
1
VERSION
TF
R/F
PART NUMBER
1
1
1
R-K
R-K
R-K
R-K
R-1
R-1
R-1
LEGEND:
For bits 3-15: R = Read only, -K = Value constant after RESET
For bits 0-2: R = Read only, -1 = Value after RESET
Table 8. TMS Device ID Bit Allocation Register Field Description
Bit
Name
31–16
Reserved
Reads are undefined and writes have no effect.
15–12
VERSION
Silicon version (revision)
These bits identify the silicon version of the device.
11
TF
Technology family
This bit distinguishes the technology family core power supply.
10
Value
Description
0
3.3 V for F10/C10 devices
1
1.8 V for F05/C05 devices
R/F
ROM/Flash
This bit distinguishes between ROM and flash devices:
0
Flash device
1
ROM device
9–3
PART NUMBER
Device-specific part number
These bits identify the assigned device-specific part number.
The assigned device-specific part number for the A128 devices is 0000111.
2–0
1
Mandatory High
Bits 2, 1, and 0 are tied high by default.
20
0
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DEVICE ELECTRICAL SPECIFICATIONS AND TIMING PARAMETERS
Absolute Maximum Ratings
over operating free-air temperature range (1)
Supply voltage range:
VCC (2)
-0.5 V to 2.5 V
Supply voltage range:
VCCIO, VCCAD, VCCP (Flash pump)
Input voltage range:
All input pins
Input clamp current:
IIK (VI < 0 or VI> VCCIO)
(2)
-0.5 V to 4.1 V
-0.5 V to 4.1 V
All pins except ADIN[0:11], PORRST,
TRST, TEST and TCK
±20 mA
IIK (VI < 0 or VI> VCCAD)
ADIN[0:11]
Operating free-air temperature range, TA:
±10 mA
T version
-40°C to 105°C
Q version
-40°C to 125°C
Operating junction temperature range, TJ
-40°C to 150°C
Storage temperature range, Tstg
-65°C to 150°C
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the devices at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to their associated grounds.
Device Recommended Operating Conditions
(1)
MIN
NOM
UNIT
VCC
Digital logic (and flash supply voltage for A128) (Core)
2.06
V
VCCIO
Digital logic supply voltage (I/O)
3
3.3
3.6
V
VCCAD
ADC supply voltage
3
3.3
3.6
V
VCCP
Flash pump supply voltage
3
3.3
3.6
V
VSS
Digital logic supply ground
VSSAD
ADC supply ground
TA
Operating free-air temperature
TJ
Operating junction temperature
(1)
1.81
MAX
0
V
-0.1
0.1
Q version
-40
125
T version
-40
105
-40
150
V
°C
°C
All voltages are with respect to VSS, except VCCAD, which is with respect to VSSAD.
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Electrical Characteristics over Recommended Operating Free-Air Temperature Range (1)
PARAMETER
Vhys
Input hysteresis
VIL
Low-level input
voltage
VIH
High-level input
voltage
TEST CONDITIONS
OSCIN only
-0.3
0.35 VCC
2
VCCIO + 0.3
0.65 VCC
VCC + 0.3
1.35
1.8
V
45
Ω
All inputs except
OSCIN
RDSON
Drain to source on
resistance
AWD only (3)
VOL
Low-level output voltage (4)
VOH
High-level output voltage (4)
IIC
Input clamp current (I/O pins) (5)
VOL = 0.35 V @ IOL = 8 mA
IOL = IOL MAX
High-level output
current
VCC Digital supply
current (operating
mode)
ICC
(4)
(5)
(6)
(7)
(8)
22
0.8 VCCIO
IOH = 50 µA
VI < VSSIO - 0.3 or VI> VCCIO + 0.3
-2
2
VI = VSS
-1
1
IIHPulldown
VI = VCCIO
5
40
IILPullup
VI= VSS
-40
-5
IIHPullup
VI= VCCIO
-1
1
All other pins
No pullup or pulldown
-1
1
CLKOUT, AWD, TDO VOL = VOL MAX
8
RST, SPI1CLK,
SPI1SOMI,
SPI1SIMO, SPI2CLK, VOL = VOL MAX
SPI2SOMI,
SPI2SIMO
4
(6)
VOL = VOL MAX
CLKOUT, TDO
V
V
V
V
VCCIO - 0.2
IILPulldown
mA
µA
mA
2
VOH = VOH MIN
-8
SPI1CLK, SPI1SOMI,
SPI1SIMO, SPI2CLK,
VOH = VOH MIN
SPI2SOMI,
SPI2SIMO
-4
All other output pins
except RST (6)
-2
VOH = VOH MIN
mA
Pipeline
SYSCLK = 48 MHz,
ICLK = 24 MHz, VCC = 2.06 V
70
mA
Non-pipeline
SYSCLK = 28 MHz,
ICLK = 14 MHz, VCC = 2.06 V
50
mA
OSCIN = 6 MHz, VCC = 2.06 V
3.0
mA
All frequencies, VCC = 2.06 V
1.0
mA
VCC Digital supply current (halt mode)
(1)
(2)
(3)
0.2
IOH = IOH MIN
VCC Digital supply current (standby mode)
ICCIO
0.2 VCCIO
IOL = 50 µA
All other output pins
IOH
V
0.8
AWD only
Low-level output
current
UNIT
-0.3
Input threshold
voltage
IOL
MAX
0.15
Vth
Input current (I/O
pins)
TYP
All inputs (2) except
OSCIN
OSCIN only
II
MIN
(7)
(7)
VCCIO Digital supply current (operating mode)
No DC load, VCCIO = 3.6 V
(8)
10
mA
VCCIO Digital supply current (standby mode)
No DC load, VCCIO = 3.6 V
(8)
300
µA
VCCIO Digital supply current (halt mode)
No DC load, VCCIO = 3.6 V
(8)
300
µA
Source currents (out of the device) are negative while sink currents (into the device) are positive.
This does not apply to the PORRST pin. For PORRST exceptions, see the RST and PORRST timings section.
These values help to determine the external RC network circuit. For more details, see the TMS470R1x System Module Reference Guide
(literature number SPNU189).
VOL and VOH are linear with respect to the amount of load current (IOL/IOH) applied.
Parameter does not apply to input-only or output-only pins.
The 2 mA buffers on these devices are called zero-dominant buffers. If two of these buffers are shorted together and one is outputting a
low level and the other is outputting a high level, the resulting value will always be low.
For flash banks/pumps in sleep mode.
I/O pins configured as inputs or outputs with no load. All pulldown inputs ≤ 0.2 V. All pullup inputs≥ VCCIO - 0.2 V.
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Electrical Characteristics over Recommended Operating Free-Air Temperature
Range (continued)
PARAMETER
ICCAD
ICCP
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCCAD supply current (operating mode)
All frequencies, VCCAD = 3.6 V
15
mA
VCCAD supply current (standby mode)
All frequencies, VCCAD = 3.6 V
20
µA
VCCAD supply current (halt mode)
All frequencies, VCCAD = 3.6 V
20
µA
VCCP = 3.6 V read operation
50
mA
VCCP = 3.6 V program and erase
70
mA
VCCP = 3.6 V standby mode
operation(7)
20
µA
20
µA
VCCP pump supply current
VCCP = 3.6 V halt mode
operation(7)
CI
Input capacitance
2
pF
CO
Output capacitance
3
pF
Parameter Measurement Information
IOL
Tester Pin
Electronics
50 Ω
V LOAD
Output
Under
Test
CL
I OH
Where:
IOL
=
IOH
=
VLOAD =
CL
=
IOL MAX for the respective pin (A)
IOH MIN for the respective pin(A)
1.5 V
150-pF typical load-circuit capacitance(B)
A.
For these values, see the "Electrical Characteristics over Recommended Operating Free-Air Temperature Range"
table.
B.
All timing parameters measured using an external load capacitance of 150 pF unless otherwise noted.
Figure 4. Test Load Circuit
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Timing Parameter Symbology
Timing parameter symbols have been created in accordance with JEDEC Standard 100. To shorten the
symbols, some of the pin names and other related terminology have been abbreviated as follows:
CM
Compaction, CMPCT
RD
Read
CO
CLKOUT
RST
Reset, RST
ER
Erase
RX
SCInRX
ICLK
Interface clock
S
Slave mode
M
Master mode
SCC
SCInCLK
OSC, OSCI
OSCIN
SIMO
SPInSIMO
OSCO
OSCOUT
SOMI
SPInSOMI
P
Program, PROG
SPC
SPInCLK
R
Ready
SYS
System clock
R0
Read margin 0, RDMRGN0
TX
SCInTX
R1
Read margin 1, RDMRGN1
Lowercase subscripts and their meanings are:
a
access time
r
rise time
c
cycle time (period)
su
setup time
d
delay time
t
transition time
f
fall time
v
valid time
h
hold time
w
pulse duration (width)
The following additional letters are used with these meanings:
H
High
X
Unknown, changing, or don't care level
L
Low
Z
High impedance
V
Valid
24
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External Reference Resonator/Crystal Oscillator Clock Option
The oscillator is enabled by connecting the appropriate fundamental 4–20 MHz resonator/crystal and load
capacitors across the external OSCIN and OSCOUT pins as shown in Figure 5a. The oscillator is a single-stage
inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test measurement
and HALT mode. TI strongly encourages each customer to submit samples of the device to the
resonator/crystal vendors for validation. The vendors are equipped to determine what load capacitors will
best tune their resonator/crystal to the microcontroller device for optimum start-up and operation over
temperature/voltage extremes.
An external oscillator source can be used by connecting a 1.8-V clock signal to the OSCIN pin and leaving the
OSCOUT pin unconnected (open) as shown in Figure 5b.
OSCIN
C1(A)
OSCOUT
Crystal
C2(A)
OSCIN
External
Clock Signal
(toggling 0-1.8 V)
(a)
A.
OSCOUT
(b)
The values of C1 and C2 should be provided by the resonator/crystal vendor.
Figure 5. Crystal/Clock Connection
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16/32-Bit RISC Flash Microcontroller
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SPNS098B – JULY 2005 – REVISED AUGUST 2006
ZPLL AND CLOCK SPECIFICATIONS
Timing Requirements for ZPLL Circuits Enabled or Disabled
MIN
MAX
UNIT
4
20
MHz
f(OSC)
Input clock frequency
tc(OSC)
Cycle time, OSCIN
50
ns
tw(OSCIL)
Pulse duration, OSCIN low
15
ns
tw(OSCIH)
Pulse duration, OSCIN high
15
ns
f(OSCRST)
(1)
OSC FAIL
frequency (1)
53
kHz
Causes a device reset (specifically a clock reset) by setting the RST OSC FAIL (GLBCTRL.15) and the OSC FAIL flag (GLBSTAT.1)
bits equal to 1. For more detailed information on these bits and device resets, see the TMS470R1x System Module Reference Guide
(literature number SPNU189).
Switching Characteristics over Recommended Operating Conditions for Clocks (1) (2)
TEST CONDITIONS (3)
PARAMETER
f(SYS)
System clock frequency (4)
f(CONFIG)
System clock frequency - flash config mode
f(ICLK)
Interface clock frequency
f(ECLK)
External clock output frequency for ECP Module
tc(SYS)
Cycle time, system clock
Cycle time, interface clock
tc(ECLK)
Cycle time, ECP module external clock output
(1)
(2)
(3)
(4)
26
MAX
48
Pipeline mode disabled
28
24
Pipeline mode enabled
25
Pipeline mode disabled
24
Pipeline mode enabled
25
Pipeline mode disabled
24
Pipeline mode enabled
20.8
Pipeline mode disabled
35.7
tc(CONFIG) Cycle time, system clock - flash config mode
tc(ICLK)
MIN
Pipeline mode enabled
41.6
Pipeline mode enabled
40
Pipeline mode disabled
41.6
Pipeline mode enabled
40
Pipeline mode disabled
41.6
UNIT
MHz
MHz
MHz
MHz
ns
ns
ns
ns
f(SYS) = M × f(OSC) / R, where M = {4 or 8}, R = {1,2,3,4,5,6,7,8} when PLLDIS = 0. R is the system-clock divider determined by the
CLKDIVPRE [2:0] bits in the global control register (GLBCTRL[2:0]) and M is the PLL multiplier determined by the MULT4 bit, also in the
GLBCTRL register (GLBCTRL[3]).
f(SYS) = f(OSC) / R, where R = {1,2,3,4,5,6,7,8} when PLLDIS = 1.
f(ICLK)= f(SYS) / X, where X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0[4:1]
bits in the SYS module.
f(ECLK) = f(ICLK) / N, where N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL[7:0] register bits in the ECP module.
Pipeline mode enabled or disabled is determined by the ENPIPE bit (FMREGOPT.0).
Flash Vread must be set to 5V to achieve maximum system clock frequency.
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Switching Characteristics over Recommended Operating Conditions for External Clocks (1) (2) (3)
(see Figure 6 and Figure 7)
PARAMETER
TEST CONDITIONS
MIN
SYSCLK or MCLK (4)
tw(COL)
Pulse duration, CLKOUT low
ICLK, X is even or 1 (5)
ICLK, X is odd and not
tw(COH)
Pulse duration, CLKOUT high
0.5tc(ICLK) - tf
1 (5)
0.5tc(SYS) - tr
ICLK, X is even or 1 (5)
0.5tc(ICLK) - tr
1 (5)
Pulse duration, ECLK low
0.5tc(ECLK) - tf
N is odd and X is even
N is odd and X is odd and not 1
Pulse duration, ECLK high
(1)
(2)
(3)
(4)
(5)
0.5tc(ECLK) - tr
N is odd and X is even
N is odd and X is odd and not 1
ns
ns
0.5tc(ECLK)+ 0.5tc(SYS) - tf
N is even and X is even or odd
tw(EOH)
ns
0.5tc(ICLK)- 0.5tc(SYS) - tr
N is even and X is even or odd
tw(EOL)
UNIT
0.5tc(ICLK)+ 0.5tc(SYS) - tf
SYSCLK or MCLK (4)
ICLK, X is odd and not
MAX
0.5tc(SYS) - tf
ns
0.5tc(ECLK)- 0.5tc(SYS) - tr
X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0[4:1] bits in the SYS module.
N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL[7:0] register bits in the ECP module.
CLKOUT/ECLK pulse durations (low/high) are a function of the OSCIN pulse durations when PLLDIS is active.
Clock source bits selected as either SYSCLK (CLKCNTL[6:5] = 11 binary) or MCLK (CLKCNTL[6:5] = 10 binary).
Clock source bits selected as ICLK (CLKCNTL[6:5] = 01 binary).
tw(COH)
CLKOUT
tw(COL)
Figure 6. CLKOUT Timing Diagram
tw(EOH)
ECLK
tw(EOL)
Figure 7. ECLK Timing Diagram
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RST AND PORRST TIMINGS
Timing Requirements for PORRST
(see Figure 8)
MIN
MAX
UNIT
0.6
V
VCCPORL
VCC low supply level when PORRST must be active during power up
VCCPORH
VCC high supply level when PORRST must remain active during power up and become active
during power down
VCCIOPORL
VCCIO low supply level when PORRST must be active during power up
VCCIOPORH
VCCIO high supply level when PORRST must remain active during power up and become
active during power down
VIL
Low-level input voltage after VCCIO > VCCIOPORH
VIL(PORRST)
Low-level input voltage of PORRST before VCCIO > VCCIOPORL
tsu(PORRST)r
Setup time, PORRST active before VCCIO > VCCIOPORL during power up
0
ms
tsu(VCCIO)r
Setup time, VCCIO > VCCIOPORL before VCC > VCCPORL
0
ms
th(PORRST)r
Hold time, PORRST active after VCC > VCCPORH
1
ms
tsu(PORRST)f
Setup time, PORRST active before VCC≤ VCCPORH during power down
8
µs
th(PORRST)rio
Hold time, PORRST active after VCC > VCCIOPORH
1
ms
th(PORRST)d
Hold time, PORRST active after VCC < VCCPORL
0
ms
tsu(PORRST)fio
Setup time, PORRST active before VCC≤ VCCIOPORH during power down
0
ns
tsu(VCCIO)f
Setup time, VCC < VCCPORL before VCCIO< VCCIOPORL
0
ns
V CCP /VCCIO
V CCIOPORH
V CC
th(PORRST)rio
V CCPORH
V CC
VCCP/VCCIO
PORRST
1.1
V
2.75
V
V
0.5
V
V CCIOPORH
V CCIO
tsu(VCCIO)f
V CC
tsu(PORRST)f
V CCPORH
tsu(PORRST)fio
tsu(PORRST)f
V CCPORL
th(PORRST)r
tsu(VCCIO)r
V CCPORL
V CCIOPORL
th(PORRST)d
tsu(PORRST)r
V IL(PORRST)
V
0.2 VCCIO
th(PORRST)r
V CCIOPORL
1.5
V IL
VIL
VIL
V IL
V IL(PORRST)
NOTE: VCCIO > 1.1 V before VCC > 0.6 V
Figure 8. PORRST Timing Diagram
Switching Characteristics over Recommended Operating Conditions for RST (1)
PARAMETER
tv(RST)
tfsu
(1)
28
Valid time, RST active after PORRST inactive
Valid time, RST active (all others)
MIN
4112tc(OSC)
8tc(SYS)
Flash start up time, from RST inactive to fetch of first instruction from flash (flash
pump stabilization time)
336tc(OSC)
MAX
UNIT
ns
ns
Specified values do NOT include rise/fall times. For rise and fall timings, see the "Switching Characteristics for Output Timings versus
Load Capacitance" table.
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JTAG Scan Interface Timing (JTAG Clock Specification 10-MHz and 50-pF Load on TDO
Output)
MIN
MAX
UNIT
tc(JTAG)
Cycle time, JTAG low and high period
50
ns
tsu(TDI/TMS - TCKr)
Setup time, TDI, TMS before TCK rise (TCKr)
15
ns
th(TCKr
15
ns
10
ns
-TDI/TMS)
Hold time, TDI, TMS after TCKr
th(TCKf
-TDO)
Hold time, TDO after TCKf
td(TCKf
-TDO)
Delay time, TDO valid after TCK fall (TCKf)
45
ns
Figure 9. JTAG Scan Timings
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OUTPUT TIMINGS
Switching Characteristics for Output Timings versus Load Capacitance (CL)
(see Figure 10)
PARAMETER
tr
tf
tf
tf
tr
tf
Rise time, CLKOUT, AWD, TDO
Fall time, CLKOUT, AWD, TDO
Rise time, SPI1CLK, SPI1SOMI, SPI1SIMO, SPI2CLK,
SPI2SOMI, SPI2SIMO
Fall time, RST, SPI1CLK, SPI1SOMI, SPI1SIMO, SPI2CLK,
SPI2SOMI, SPI2SIMO
Rise time, all other output pins
Fall time, all other output pins
MIN
MAX
CL = 15 pF
0.5
2.50
CL = 50 pF
1.5
5
CL = 100 pF
3
9
CL = 150 pF
4.5
12.5
CL = 15 pF
0.5
2.5
CL = 50 pF
1.5
5
CL = 100 pF
3
9
CL = 150 pF
4.5
12.5
CL = 15 pF
2.5
8
CL= 50 pF
5
14
CL = 100 pF
9
23
CL = 150 pF
13
32
CL = 15 pF
2.5
8
CL= 50 pF
5
14
CL = 100 pF
9
23
CL = 150 pF
13
32
CL = 15 pF
2.5
10
CL = 50 pF
6.0
25
CL = 100 pF
12
45
CL = 150 pF
18
65
CL = 15 pF
3
10
CL = 50 pF
8.5
25
CL = 100 pF
16
45
CL = 150 pF
23
65
tr
tf
80%
Output
VCC
80%
20%
20%
Figure 10. CMOS-Level Outputs
30
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0
UNIT
ns
ns
ns
ns
ns
ns
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16/32-Bit RISC Flash Microcontroller
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SPNS098B – JULY 2005 – REVISED AUGUST 2006
INPUT TIMINGS
Timing Requirements for Input Timings (1)
(see Figure 11)
MIN
tpw
(1)
Input minimum pulse width
MAX
UNIT
tc(ICLK) + 10
ns
tc(ICLK) = interface clock cycle time = 1/f(ICLK)
tpw
Input
80%
V CC
80%
20%
20%
0
Figure 11. CMOS-Level Inputs
FLASH TIMINGS
Timing Requirements for Program Flash
(1)
MIN
TYP
MAX
UNIT
4
16
200
µs
1
4
s
tprog(16-bit)
Half word (16-bit) programming time
tprog(Total)
128K-byte programming time (2)
terase(sector)
Sector erase time
twec
Write/erase cycles at TA = –40°C to 125°C
tfp(RST)
Flash pump settling time from RST to SLEEP
67tc(SYS)
ns
tfp(SLEEP)
Initial flash pump settling time from SLEEP to STANDBY
67tc(SYS)
ns
tfp(STANDBY)
Initial flash pump settling time from STANDBY to ACTIVE
34tc(SYS)
ns
(1)
(2)
1.7
50000
s
cycles
For more detailed information on the flash core sectors, see the flash program and erase section of this data sheet.
The 128K-byte programming times include overhead of the state machine.
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SPIn MASTER MODE TIMING PARAMETERS
SPIn MASTER MODE EXTERNAL TIMING PARAMETERS (1) (2) (3)
(CLOCK PHASE = 0, SPInCLK = OUTPUT, SPInSIMO = OUTPUT, AND SPInSOMI = INPUT) (see Figure 12)
NO.
1
2 (5)
3 (5)
MIN
MAX
Unit
100
256tc(ICLK)
ns
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)M- tr
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)M - tf
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)M- tf
0.5tc(SPC)M + 5
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)M - tr
0.5tc(SPC)M + 5
td(SPCH-SIMO)M
Delay time, SPInCLK high to SPInSIMO valid
(clock polarity = 0)
10
td(SPCL-SIMO)M
Delay time, SPInCLK low to SPInSIMO valid
(clock polarity = 1)
10
tv(SPCL-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK low
(clock polarity = 0)
tc(SPC)M - 5 - tf
tv(SPCH-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK high
(clock polarity = 1)
tc(SPC)M - 5 - tr
tsu(SOMI-SPCL)M
Setup time, SPInSOMI before SPInCLK low
(clock polarity = 0)
6
tsu(SOMI-SPCH)M
Setup time, SPInSOMI before SPInCLK high
(clock polarity = 1)
6
tv(SPCL-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK low
(clock polarity = 0)
4
tv(SPCH-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK high
(clock polarity = 1)
4
tc(SPC)M
Cycle time, SPInCLK
tw(SPCH)M
4(5)
5(5)
6(5)
7(5)
(1)
(2)
(3)
(4)
(5)
(4)
ns
ns
ns
ns
ns
The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.
tc(ICLK) = interface clock cycle time = 1/f(ICLK)
For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(ICLK)≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
For PS values of 0: tc(SPC)M = 2tc(ICLK)≥ 100 ns.
The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSIMO
Master Out Data Is Valid
6
7
SPInSOMI
Master In Data
Must Be Valid
Figure 12. SPIn Master Mode External Timing (CLOCK PHASE = 0)
32
ns
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SPIn MASTER MODE EXTERNAL TIMING PARAMETERS
(1) (2) (3)
(CLOCK PHASE = 1, SPInCLK = OUTPUT, SPInSIMO = OUTPUT, AND SPInSOMI = INPUT) (see Figure 13)
NO.
1
2 (5)
3 (5)
4(5)
5(5)
6(5)
7(5)
(1)
(2)
(3)
(4)
(5)
MIN
MAX
Unit
100
256tc(ICLK)
ns
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)M- tr
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)M - tf
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)M- tf
0.5tc(SPC)M + 5
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)M - tr
0.5tc(SPC)M + 5
tv(SIMO-SPCH)M
Valid time, SPInCLK high after SPInSIMO data valid
(clock polarity = 0)
0.5tc(SPC)M - 10
tv(SIMO-SPCL)M
Valid time, SPInCLK low after SPInSIMO data valid
(clock polarity = 1)
0.5tc(SPC)M - 10
tv(SPCH-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK high
(clock polarity = 0)
0.5tc(SPC)M - 5 - tr
tv(SPCL-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK low
(clock polarity = 1)
0.5tc(SPC)M - 5 - tf
tsu(SOMI-SPCH)M
Setup time, SPInSOMI before SPInCLK high
(clock polarity = 0)
6
tsu(SOMI-SPCL)M
Setup time, SPInSOMI before SPInCLK low
(clock polarity = 1)
6
tv(SPCH-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK high
(clock polarity = 0)
6
tv(SPCL-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK low
(clock polarity = 1)
6
tc(SPC)M
Cycle time, SPInCLK
tw(SPCH)M
(4)
ns
ns
ns
ns
ns
ns
The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is set.
tc(ICLK) = interface clock cycle time = 1/f(ICLK)
For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
When the SPI is in master mode, the following must be true:
For PS values from 1 to 255: tc(SPC)M≥ (PS +1)tc(ICLK)≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
For PS values of 0: tc(SPC)M = 2tc(ICLK)≥ 100 ns.
The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSIMO
Master Out Data Is Valid
Data Valid
6
7
SPInSOMI
Master In Data
Must Be Valid
Figure 13. SPIn Master Mode External Timing (CLOCK PHASE = 1)
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SPIn SLAVE MODE TIMING PARAMETERS
SPIn SLAVE MODE EXTERNAL TIMING PARAMETERS (1) (2) (3) (4)
(CLOCK PHASE = 0, SPInCLK = INPUT, SPInSIMO = INPUT, AND SPInSOMI = OUTPUT) (see Figure 14)
NO
.
1
2 (6)
3 (6)
4 (6)
MIN
100
256tc(ICLK)
tw(SPCH)S
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)S - 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)S - 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)S - 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCH)S
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)S - 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
td(SPCH-
Delay time, SPInCLK high to SPInSOMI valid
(clock polarity = 0)
6 + tr
Delay time, SPInCLK low to SPInSOMI valid
(clock polarity = 1)
6 + tf
SOMI)S
td(SPCL-
SOMI)S
tv(SPCLSOMI)S
tsu(SIMOSPCL)S
tsu(SIMOSPCH)S
tv(SPCL7 (6)
SIMO)S
tv(SPCHSIMO)S
(1)
(2)
(3)
(4)
(5)
(6)
34
ns
Cycle time, SPInCLK (5)
tv(SPCH-
6 (6)
Unit
tc(SPC)S
SOMI)S
5 (6)
MAX
ns
ns
ns
Valid time, SPInSOMI data valid after SPInCLK high
(clock polarity =0)
tc(SPC)S - 6 - tr
Valid time, SPInSOMI data valid after SPInCLK low
(clock polarity =1)
tc(SPC)S - 6 - tf
ns
Setup time, SPInSIMO before SPInCLK low
(clock polarity = 0)
6
Setup time, SPInSIMO before SPInCLK high
(clock polarity = 1)
6
Valid time, SPInSIMO data valid after SPInCLK low
(clock polarity = 0)
6
Valid time, SPInSIMO data valid after SPInCLK high
(clock polarity = 1)
6
ns
ns
The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.
If the SPI is in slave mode, the following must be true: tc(SPC)S≥ (PS + 1) tc(ICLK), where PS = prescale value set in SPInCTL1[12:5].
For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
tc(ICLK) = interface clock cycle time = 1/f(ICLK)
When the SPIn is in slave mode, the following must be true:
For PS values from 1 to 255: tc(SPC)S≥ (PS +1)tc(ICLK)≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
For PS values of 0: tc(SPC)S = 2tc(ICLK)≥ 100 ns.
The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
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1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
55
SPInSOMI
SPISOMI Data Is Valid
6
7
SPInSIMO
SPISIMO Data
Must Be Valid
Figure 14. SPIn Slave Mode External Timing (CLOCK PHASE = 0)
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SPIn SLAVE MODE EXTERNAL TIMING PARAMETERS (1) (2) (3) (4)
(CLOCK PHASE = 1, SPInCLK = INPUT, SPInSIMO = INPUT, AND SPInSOMI = OUTPUT) (see Figure 15)
NO
.
1
100
256tc(ICLK)
ns
tw(SPCH)S
Pulse duration, SPInCLK high (clock polarity =
0)
0.5tc(SPC)S-0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity =
1)
0.5tc(SPC)S-0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity =
0)
0.5tc(SPC)S-0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCH)S
Pulse duration, SPInCLK high (clock polarity =
1)
0.5tc(SPC)S-0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tv(SOMI-SPCH)S
Valid time, SPInCLK high after SPInSOMI data
valid (clock polarity = 0)
0.5tc(SPC)S - 6 - tr
tv(SOMI-SPCL)S
Valid time, SPInCLK low after SPInSOMI data
valid (clock polarity = 1)
0.5tc(SPC)S - 6 - tf
tv(SPCH-SOMI)S
Valid time, SPInSOMI data valid after SPInCLK
high (clock polarity =0)
0.5tc(SPC)S - 6 - tr
tv(SPCL-SOMI)S
Valid time, SPInSOMI data valid after SPInCLK
low (clock polarity =1)
0.5tc(SPC)S - 6 - tf
tsu(SIMO-SPCH)S
Setup time, SPInSIMO before SPInCLK high
(clock polarity = 0)
6
tsu(SIMO-SPCL)S
Setup time, SPInSIMO before SPInCLK low
(clock polarity = 1)
6
tv(SPCH-SIMO)S
Valid time, SPInSIMO data valid after SPInCLK
high (clock polarity = 0)
6
tv(SPCL-SIMO)S
Valid time, SPInSIMO data valid after SPInCLK
low (clock polarity = 1)
6
4 (6)
5 (6)
6 (6)
7 (6)
36
Unit
Cycle time, SPInCLK (5)
3 (6)
(6)
MAX
tc(SPC)S
2 (6)
(1)
(2)
(3)
(4)
(5)
MIN
ns
ns
ns
ns
ns
ns
The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is set.
If the SPI is in slave mode, the following must be true: tc(SPC)S≥ (PS + 1) tc(ICLK), where PS = prescale value set in SPInCTL1[12:5].
For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
tc(ICLK) = interface clock cycle time = 1/f(ICLK)
When the SPIn is in slave mode, the following must be true:
For PS values from 1 to 255: tc(SPC)S≥ (PS +1)tc(ICLK)≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
For PS values of 0: tc(SPC)S = 2tc(ICLK)≥ 100 ns.
The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
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1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSOMI
SPISOMI Data Is Valid
Data Valid
6
7
SPISIMO Data Must
Be Valid
SPInSIMO
Figure 15. SPIn Slave Mode External Timing (CLOCK PHASE = 1)
SCIn ISOSYNCHRONOUS MODE TIMINGS INTERNAL CLOCK
Timing Requirements for Internal Clock SCIn Isosynchronous Mode (1) (2) (3)
(BAUD + 1)
IS EVEN OR BAUD = 0
(BAUD + 1)
IS ODD AND BAUD ≠ 0
UNIT
MIN
MAX
MIN
MAX
2tc(ICLK)
224tc(ICLK)
3tc(ICLK)
(224 -1) tc(ICLK)
ns
tc(SCC)
Cycle time, SCInCLK
tw(SCCL)
Pulse duration, SCInCLK
low
0.5tc(SCC) - tf
0.5tc(SCC) + 5
0.5tc(SCC)+0.5tc(ICLK) - tf
0.5tc(SCC)+0.5tc(ICLK)
ns
tw(SCCH)
Pulse duration, SCInCLK
high
0.5tc(SCC) - tr
0.5tc(SCC) + 5
0.5tc(SCC)-0.5tc(ICLK) - tr
0.5tc(SCC)-0.5tc(ICLK)
ns
td(SCCH-
Delay time, SCInCLK
high to SCInTX valid
10
ns
TXV)
tv(TX)
Valid time, SCInTX data
after SCInCLK low
tsu(RX-SCCL)
Setup time, SCInRX
before SCInCLK low
tv(SCCL-RX)
Valid time, SCInRX data
after SCInCLK low
(1)
(2)
(3)
10
tc(SCC) - 10
tc(SCC)- 10
ns
tc(ICLK) + tf + 20
tc(ICLK) + tf + 20
ns
- tc(ICLK) + tf + 20
- tc(ICLK) + tf + 20
ns
BAUD = 24-bit concatenated value formed by the SCI[H,M,L]BAUD registers.
tc(ICLK) = interface clock cycle time = 1/f(ICLK)
For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
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tc(SCC)
tw(SCCL)
tw(SCCH)
SCICLK
tv(TX)
td(SCCHĆTXV)
Data Valid
SCITX
tsu(RXĆSCCL)
SCIRX
A.
tv(SCCLĆRX)
Data Valid
Data transmission/reception characteristics for isosynchronous mode with internal clocking are similar to the
asynchronous mode. Data transmission occurs on the SCICLK rising edge, and data reception occurs on the
SCICLK falling edge.
Figure 16. SCIn Isosynchronous Mode Timing Diagram for Internal Clock
38
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SCIn ISOSYNCHRONOUS MODE TIMINGS EXTERNAL CLOCK
Timing Requirements for External Clock SCIn Isosynchronous Mode (1) (2)
MIN
SCInCLK (3)
MAX
tc(SCC)
Cycle time,
tw(SCCH)
Pulse duration, SCInCLK high
0.5tc(SCC)- 0.25tc(ICLK)
0.5tc(SCC) + 0.25tc(ICLK)
ns
tw(SCCL)
Pulse duration, SCInCLK low
0.5tc(SCC)- 0.25tc(ICLK)
0.5tc(SCC) + 0.25tc(ICLK)
ns
td(SCCH-TXV)
Delay time, SCInCLK high to SCInTX valid
2tc(ICLK) + 12 + tr
ns
tv(TX)
Valid time, SCInTX data after SCInCLK low
tsu(RX-SCCL)
Setup time, SCInRX before SCInCLK low
tv(SCCL-RX)
Valid time, SCInRX data after SCInCLK low
(1)
(2)
(3)
8tc(ICLK)
UNIT
ns
2tc(SCC)-10
ns
0
ns
2tc(ICLK) + 10
ns
tc(ICLK) = interface clock cycle time = 1/f(ICLK)
For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
When driving an external SCInCLK, the following must be true: tc(SCC)≥ 8tc(ICLK)
tc(SCC)
tw(SCCH)
tw(SCCL)
SCICLK
tv(TX)
td(SCCHĆTXV)
Data Valid
SCITX
tsu(RXĆSCCL)
SCIRX
A.
tv(SCCLĆRX)
Data Valid
Data transmission / reception characteristics for isosynchronous mode with external clocking are similar to the
asynchronous mode. Data transmission occurs on the SCICLK rising edge, and data reception occurs on the
SCICLK falling edge.
Figure 17. SCIn Isosynchronous Mode Timing Diagram for External Clock
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HIGH-END TIMER (HET) TIMINGS
Minimum PWM Output Pulse Width:
This is equal to one high resolution clock period (HRP). The HRP is defined by the 6-bit high resolution prescale
factor (hr), which is user defined, giving prescale factors of 1 to 64, with a linear increment of codes.
Therefore, the minimum PWM output pulse width = HRP(min) = hr(min)/SYSCLK = 1/SYSCLK
For example, for a SYSCLK of 30 MHz, the minimum PWM output pulse width = 1/30 = 33.33ns
Minimum Input Pulses that Can Be Captured:
The input pulse width must be greater or equal to the low resolution clock period (LRP), i.e., the HET loop (the
HET program must fit within the LRP). The LRP is defined by the 3-bit loop-resolution prescale factor (lr), which
is user defined, with a power of 2 increment of codes. That is, the value of lr can be 1, 2, 4, 8, 16, or 32.
Therefore, the minimum input pulse width = LRP(min) = hr(min) * lr(min)/SYSCLK = 1 * 1/SYSCLK
For example, with a SYSCLK of 30 MHz, the minimum input pulse width = 1 * 1/30 = 33.33 ns
NOTE:
Once the input pulse width is greater than LRP, the resolution of the measurement is
still HRP. (That is, the captured value gives the number of HRP clocks inside the
pulse.)
Abbreviations:
hr = HET high resolution divide rate = 1, 2, 3,...63, 64
lr = HET low resolution divide rate = 1, 2, 4, 8, 16, 32
High resolution clock period = HRP = hr/SYSCLK
Loop resolution clock period = LRP = hr*lr/SYSCLK
STANDARD CAN CONTROLLER (SCC) MODE TIMINGS
Dynamic Characteristics for the CANSTX and CANSRX Pins
PARAMETER
td(CANSTX)
Delay time, transmit shift register to CANSTX pin (1)
td(CANSRX)
Delay time, CANSRX pin to receive shift register
(1)
40
These values do not include the rise/fall times of the output buffer.
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MIN
MAX
UNIT
15
ns
5
ns
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MULTI-BUFFERED A-TO-D CONVERTER (MibADC)
The multi-buffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that enhances
the A-to-D performance by preventing digital switching noise on the logic circuitry which could be present on
VSSand VCC from coupling into the A-to-D analog stage. All A-to-D specifications are given with respect to
ADREFLO unless otherwise noted.
Resolution
10 bits (1024 values)
Monotonic
Assured
Output conversion code
00h to 3FFh [00 for VAI≤ADREFLO; 3FF for VAI≥
ADREFHI]
MibADC Recommended Operating Conditions (1)
MIN
MAX
UNIT
ADREFHI
A-to-D high -voltage reference source
VSSAD
VCCAD
V
ADREFLO
A-to-D low-voltage reference source
VSSAD
VCCAD
V
VAI
Analog input voltage
VSSAD- 0.3
VCCAD + 0.3
V
-2
2
mA
current (2)
Analog input clamp
(VAI < VSSAD - 0.3 or VAI > VCCAD + 0.3)
IAIC
(1)
(2)
For VCCAD and VSSAD recommended operating conditions, see the "Device Recommended Operating Conditions" table.
Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels.
Operating Characteristics over Full Ranges of Recommended Operating Conditions (1) (2)
PARAMETER
Ri
Analog input resistance
DESCRIPTION/CONDITIONS
Ci
Analog input capacitance
See Figure 18.
IAIL
Analog input leakage current
See Figure 18.
IADREFHI
ADREFHI input current
ADREFHI = 3.6 V, ADREFLO = VSSAD
CR
Conversion range over which specified
accuracy is maintained
ADREFHI - ADREFLO
EDNL
Differential nonlinearity error
EINL
ETOT
(1)
(2)
MIN
See Figure 18.
Conversion
Sampling
TYP
MAX
250
500
UNIT
Ω
10
pF
30
pF
1
µA
5
mA
3.6
V
Difference between the actual step width and the
ideal value after offset correction. See Figure 19.
±2
LSB
Integral nonlinearity error
Maximum deviation from the best straight line
through the MibADC. MibADC transfer
characteristics, excluding the quantization error
after offset correction. See Figure 20.
±2
LSB
Total error/Absolute accuracy
Maximum value of the difference between an
analog value and the ideal midstep value. See
Figure 21.
±2
LSB
-1
3
VCCIO = VCCAD = ADREFHI
1 LSB = (ADREFHI - ADREFLO)/210 for the MibADC
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External
Rs
MibADC
Input Pin
Ri
Sample Switch
Sample
Capacitor
Parasitic
Capacitance
V src
R leak
Ci
Figure 18. MibADC Input Equivalent Circuit
Multi-Buffer ADC (MibADC) Timing Requirements
MIN
tc(ADCLK)
Cycle time, MibADC clock
td(SH)
Delay time, sample and hold time
td(C)
td(SHC)
(1)
(1)
MAX
UNIT
0.05
µs
1
µs
Delay time, conversion time
0.55
µs
Delay time, total sample/hold and conversion time
1.55
µs
This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors; for
more details, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206).
The differential nonlinearity error shown in Figure 19 (sometimes referred to as differential linearity) is the
difference between an actual step width and the ideal value of 1 LSB.
!
!
A.
1 LSB = (ADREFHI - ADREFLO)/210
Figure 19. Differential Nonlinearity (DNL)
The integral nonlinearity error shown in Figure 20 (sometimes referred to as linearity error) is the deviation of the
values on the actual transfer function from a straight line.
42
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0 ... 111
0 ... 110
Ideal
Transition
0 ... 101
Actual
Transition
0 ... 100
At Transition
011/100
(ć 1/2 LSB)
0 ... 011
0 ... 010
End-Point Lin. Error
0 ... 001
At Transition
001/010 (ć 1/4 LSB)
0 ... 000
0
1
2
3
4
5
6
7
Analog Input Value (LSB)
A.
1 LSB = (ADREFHI - ADREFLO)/210
Figure 20. Integral Nonlinearity (INL) Error
The absolute accuracy or total error of an MibADC as shown in Figure 21 is the maximum value of the
difference between an analog value and the ideal midstep value.
A.
1 LSB = (ADREFHI - ADREFLO)/210
Figure 21. Absolute Accuracy (Total) Error
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THERMAL RESISTANCE CHARACTERISTICS
44
PARAMETER
°C/W
RθJA
51
RθJC
5
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Revision History
This revision history highlights the changes made to the device-specific datasheet.
Table 9. Revision History
SPNS098A to SPNS098B
Revised the Family Nomenclature drawing, Figure 2, to add Q version of the temperature range.
Revised "Absolute Maximum Ratings" table to add Q version of the temperature range.
Revised "Device Recommended Operating Conditions" table to add Q version of the temperature range.
Added note to PORRST Timing Diagram.
Changed TA range to –40°C to 125°C on twec in "Timing Requirements for Program Flash" table.
Added twec MIN value of 50000 and deleted MAX value in "Timing Requirements for Program Flash" table.
Changed terase(sector) TYP value to 1.7 and removed MAX value in "Timing Requirements for Program Flash" table.
SPNS098 to SPNS098A
Moved "XOR Share" section to "Description" section.
Changed the Family Nomenclature drawing, Figure 2, to reflect T version of the temperature range.
Revised "Absolute Maximum Ratings" table to show T version of the temperature range.
Revised "Device Recommended Operating Conditions" table to show T version of the temperature range.
Added "Device and Development-Support Tool Nomenclature" information.
Changed VCC to 2.06 V in the ICC in the "Electrical Characteristics over Recommended Operating Free-Air Temperature Range" table.
Moved 2.75 from Max to Min column for VCCIOPORH in "Timing Requirements for PORRST" table.
Added row for Tfsu to "Switching Characteristics over Recommended Operating Conditions for RST" table.
Added rows for Tfp(RST), Tfp(SLEEP), and Tfp(STANDBY) to "Flash Timings" table.
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Jun-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
TMS470R1A128PZ-T
ACTIVE
LQFP
PZ
Pins Package Eco Plan (2)
Qty
100
90
Green (RoHS &
no Sb/Br)
Lead/Ball Finish
CU NIPDAU
MSL Peak Temp (3)
Level-3-260C-168HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
0,08 M
51
76
50
100
26
1
0,13 NOM
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
16,20
SQ
15,80
0,05 MIN
1,45
1,35
0,25
0°– 7°
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040149 /B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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