T R I Q U I N T S E M I C O N D U C T O R, I N C . TQ2059 REFCLK GND NC NC 10 9 8 7 6 5 High-Frequency Clock Generator 4 NC 12 Phase Detector ÷10 VCO NC 13 TEST1 14 TEST2 15 NC 16 NC 17 27 NC GND 18 26 MUX ÷2 MUX 3 NC 2 NC 1 NC Control 28 NC 19 20 21 22 23 24 25 EVDD PDR2 QN Q PDR1 GND AGND AVDD TriQuint’s TQ2059 is a high-frequency clock generator. It utilizes a 20 MHz to 35 MHz TTL input to generate a 200 MHz to 350 MHz PECL output. The TQ2059 has a completely self-contained Phase-Locked Loop (PLL) running at 400 MHz to 700 MHz. This stable PLL allows for a low period-to-period output jitter of 120 ps (max), and enables tight duty-cycle control of 55%to 45% (worst case). The TQ2059 provides optional 200-ohm on-chip pull-down resistors which are useful if the output is AC-coupled to the device being driven. In order to use these resistors, pin 20 (PDR2) should be connected to pin 21 (QN), and pin 23 (PDR1) should be connected to pin 22 (Q). Features • Output frequency range: 200 MHz to 350 MHz • One differential PECL output: 600 mV (min) swing • Common-mode voltage: VDD –1.2 V (max), VDD –1.6 V (min) • Period-to-period output jitter: 30 ps peak-to-peak (typ) 120 ps peak-to-peak (max) • Reference clock input: 20 MHz to 35 MHz TTL-level crystal oscillator SYSTEM TIMING PRODUCTS VDD TESTIN 11 NC GND Figure 1. Pinout Diagram • Self-contained loop filter • Optional 200-ohm pull-down resistors for AC-coupled outputs • +5 V power supply • 28-pin J-lead surface-mount package • Ideal for designs based on DEC Alpha AXP™ processors Various test modes on the chip simplify debug and testing of systems by slowing the clock output or by bypassing the PLL. For additional information and latest specifications, see our website: www.triquint.com 1 TQ2059 Figure 2. Simplified Block Diagram REFCLK Phase Detector ÷10 VCO (20 MHz to 35 MHz) ÷2 MUX MUX (200 MHz QN to Q 350 MHz) TESTIN TEST1 Control TEST2 Table 1. Mode Selection TEST1 TEST2 TESTIN 1 REFCLK 2 Q, QN 1 (Test) 0 0 fTESTCLK “don't care” fTESTCLK ÷ 20 2 (Test) 3 (Test) 4 (Bypass) 5 (Normal) 0 1 1 1 1 0 1 1 “don’t care” fTESTCLK 0 1 “don't care” “don't care” fREFCLK fREFCLK 0, 1 fTESTCLK ÷ 2 fREFCLK 10 x fREFCLK 3 Mode Note: 1. In modes 1 and 3, TESTIN may be used to bypass the PLL. A clock input at TESTIN will be divided as shown. 2. REFCLK = 20 MHz to 35 MHz. 3. Q, QN = 200 MHz to 350 MHz. Recommended Layout (Not to scale) Pin 1 VDD 0.1 µF GND GND Q 50 OHMS QN REFCLK (from TTLoscillator) (From TTL Oscillator) VDD GND 0.1 µF VDD 0.1 µF GND 2 For additional information and latest specifications, see our website: www.triquint.com TQ2059 Absolute Maximum Ratings Storage Temperature Ambient temperature with power applied –65°C to +150°C –55°C to +110°C Supply voltage to ground potential –0.5 V to +7.0 V DC input voltage DC input current –0.5 V to (VDD + 0.5) V –30 mA to +5 mA Package thermal resistance (MQuad) Die junction temperature θJA = 45°C/W TJ = 150°C Note: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. The device should be operated only under the DC and AC conditions shown below. DC Characteristics (VDD = +5 V + 5%, TA = 0 °C to +70 °C)1 Symbol Description Test Conditions VOH Output HIGH voltage VCC = Min PECL load VOL Output LOW voltage VCC = Min PECL load VCMO Output common Min Limits 1 Typ Max Unit VCC–1.20 VCC–0.50 V VCC–2.00 VCC–1.60 V PECL VCC–1.60 VCC–1.20 V 1.2 V mode voltage ∆ VOUT Output differential voltage PECL 0.6 VIH2 Input HIGH level Guaranteed input logical 2.0 V VIL2 Input LOW level IIL Input LOW current VDD = Max VIN = 0.40 V IIH Input HIGH current VDD = Max VIN = 2.7 V II Input HIGH current VDD = Max VIN = 5.3 V IDDS3 Power supply current VDD = Max VI Input clamp voltage VDD = Min Symbol Description Test Conditions CIN Input Capacitance VIN = 2.0 V at f = 1 MHz 6 pF COUT Output Capacitance VOUT = 2.0 V at f = 1 MHz 9 pF Guaranteed input logical LOW Voltage for all inputs IIN = –18 mA 0.8 V –150 –400 µA 0 25 µA 2 1000 µA 85 120 mA –0.70 –1.2 V Typ Max Unit SYSTEM TIMING PRODUCTS HIGH Voltage for all inputs Capacitance Min Notes: 1. Typical limits are at VDD = 5.0 V and TA = 25˚C. 2. These are absolute values with respect to device ground and include all overshoots due to system or tester noise. 3. This parameter is measured with device not switching and unloaded. For additional information and latest specifications, see our website: www.triquint.com 3 TQ2059 AC Characteristics (VDD = +5 V + 5%, TA = 0 °C to +70 °C) Symbol Input Clock (REFCLK) Test Conditions Min Typ Max Unit tCPWH CLK pulse width HIGH Figure 2 4 — — ns tCPWL CLK pulse width LOW Figure 2 4 — — ns — — 2.0 ns tIR Symbol tOR, tOF Input rise time (0.8 V – 2.0 V) Input Clock (REFCLK) Test Conditions Min Typ Max Unit ps Rise/fall time (20% – 80%) Figure 2 100 220 350 tCYC Duty-cycle Figure 2 45 50 55 % tJP2 Period-to-Period Jitter — 30 120 ps tSYNC3 Synchronization Time — 10 500 µs Notes: 1. All measurements are tested with a REFCLK having a rise time of 0.5 ns (0.8 V to 2.0 V). 2. Jitter specification is peak to peak. Period-to-Period jitter is the jitter on the output with respect to the output's previous crossing. 3. tSYNC is the time required for the PLL to synchronize and assumes the presence of a CLK signal. Figure 1 4 Figure 2 For additional information and latest specifications, see our website: www.triquint.com TQ2059 28-Pin MQuad J-Leaded Package Mechanical Specification (All dimensions in inches) .172 ±.005 .490 ±.005 .132 ±.005 .445 ±.005 .045 X 45°° .040 MIN PIN 1 8 .490 ±.005 22 .018 .445 .028 ±.005 .445 ±.005 .050 TYP. 0.125 VENT PLUG 15 .015 X 45°° .410 ±.015 .060 .104 ±.005 .050 TYP. NON-ACCUM. Pin Name Description I/O Pin # 1 NC No Connect — 15 TEST2 Test Control 2 2 NC No Connect — 16 NC No Connect 3 NC No Connect — 17 NC No Connect O 4 NC No Connect — 18 GND Ground — 5 NC No Connect — 19 EVDD VDD for ECL Output (+5 V) — 6 NC No Connect — 20 PDR2 Pull-down Resistor 2 (200 Ω) I 7 GND Ground — 21 QN Differential PECL Output (–) O 8 REFCLK Reference Clock I 22 Q Differential PECL Output (+) O Pin # Pin Name Description I/O I — I 23 PDR1 Pull-down Resistor 1 (200 Ω) — 24 GND Ground Logic Ground — 25 AGND Analog Ground — Logic VDD (+5 V) — 26 AVDD Analog VDD (+5 V) — — 27 NC No Connect — I 28 NC No Connect — 9 TESTIN Test Input 10 NC No Connect 11 GND 12 VDD 13 NC No Connect 14 TEST1 Test Control 1 For additional information and latest specifications, see our website: www.triquint.com SYSTEM TIMING PRODUCTS 28-Pin MQuad Pin Description I — 5 TQ2059 Ordering Information To order, please specify as shown below: TQ2059-MC High-Frequency Clock Generator Temperature range: 0°C to 70°C (Commercial) Package: 28-Pin MQuad Additional Information For latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint: Web: www.triquint.com Email: [email protected] Tel: (503) 615-9000 Fax: (503) 615-8900 For technical questions and additional information on specific applications: Email: [email protected] The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or omissions. TriQuint assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems. Copyright © 1997 TriQuint Semiconductor, Inc. All rights reserved. Revision 1.0.A October 1997 6 For additional information and latest specifications, see our website: www.triquint.com