TI TMS27C240

TMS27C240 262144 BY 16-BIT UV ERASABLE
TMS27PC240 262144 BY 16-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS240D– NOVEMBER 1990 – REVISED SEPTEMBER 1997
D
D
D
D
D
D
D
D
D
TMS27PC240 FN PACKAGE
( TOP VIEW )
DQ13
DQ14
DQ15
E
V PP
NC
V CC
A17
A16
A15
A14
Organization . . . 262 144 by 16 Bits
Single 5-V Power Supply
All Inputs / Outputs Fully TTL Compatible
Static Operations (No Clocks, No Refresh)
Max Access / Min Cycle Time
VCC ± 10%
’27C/ PC240-10
100 ns
’27C/ PC240-12
120 ns
’27C/ PC240-15
150 ns
16-Bit Output For Use in
Microprocessor-Based Systems
Very High Speed SNAP! Pulse
Programming
Power-Saving CMOS Technology
3-State Output Buffers
400-mV Minimum DC Noise Immunity With
Standard TTL Loads
Latchup Immunity of 250 mA on All Input
and Output Lines
No Pullup Resistors Required
Low Power Dissipation ( VCC = 5.5 V )
– Active . . . 275 mW Worst Case
– Standby . . . 0.55 mW Worst Case
(CMOS-Input Levels)
Temperature Range Options
6 5
DQ12
DQ11
DQ10
DQ9
DQ8
GND†
NC
DQ7
DQ6
DQ5
DQ4
4
3
2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
17
29
A13
A12
A11
A10
A9
GND†
NC
A8
A7
A6
A5
18 19 20 21 22 23 24 25 26 27 28
DQ3
DQ2
DQ1
DQ0
G
NC
A0
A1
A2
A3
A4
D
D
D
D
D
PIN NOMENCLATURE
A0 – A17
DQ0 – DQ15
E
G
GND
NC
VCC
VPP
Address Inputs
Inputs (programming) / Outputs
Chip Enable
Output Enable
Ground
No Connection
5-V Supply
13-V Power Supply ‡
† Pins 11 and 30 (J package) and pins 12 and 34
(FN package) must be connected externally to
ground.
‡ Only in program mode
description
The TMS27C240 series are 262 144 by 16-bit (4 194 304-bit), ultraviolet-light erasable, electrically
programmable read-only memories (EPROMs).
The TMS27PC240 series are 262 144 by 16-bit (4 194 304-bit), one-time programmable (OTP) electrically
programmable read-only memories (PROMs).
These devices are fabricated using power-saving CMOS technology for high speed and simple interface with
MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 74 TTL circuits
without the use of external pull-up resistors. Each output can drive one Series 74 TTL circuit without external
resistors.
The TMS27C240 EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in
mounting hole rows on 15,2-mm (600-mil) centers. The TMS27C240 is offered with two choices of temperature
ranges of 0°C to 70°C (JL suffix) and – 40°C to 85°C (JE suffix). See Table 1.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
TMS27C240 262144 BY 16-BIT UV ERASABLE
TMS27PC240 262144 BY 16-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS240D– NOVEMBER 1990 – REVISED SEPTEMBER 1997
TMS27C240 J PACKAGE
( TOP VIEW )
VPP
E
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
GND†
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
G
2
POST OFFICE BOX 1443
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
A17
A16
A15
A14
A13
A12
A11
A10
A9
GND†
A8
A7
A6
A5
A4
A3
A2
A1
A0
• HOUSTON, TEXAS 77251–1443
TMS27C240 262144 BY 16-BIT UV ERASABLE
TMS27PC240 262144 BY 16-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS240D– NOVEMBER 1990 – REVISED SEPTEMBER 1997
description (continued)
The TMS27PC240 OTP PROM is offered in a 44-lead plastic leaded chip carrier package using 1,25-mm
(50-mil) lead spacing ( FN suffix). The TMS27PC240 is offered with two choices of temperature ranges of 0°C
to 70°C (FNL suffix) and –40°C to 85°C (FNE suffix). See Table 1.
Table 1. Temperature Range Suffixes
SUFFIX FOR OPERATING FREEAIR TEMPERATURE RANGES
0°C TO 70°C
– 40°C TO 85°C
TMS27C240-XXX
JL
JE
TMS27PC240-XXX
FNL
FNE
These EPROMs and OTP PROMs operate from a single 5-V supply ( in the read mode), and they are ideal for
use in microprocessor-based systems. One other (13 V) supply is needed for programming . All programming
signals are TTL level. For programming outside the system, existing EPROM programmers can be used.
operation
The eight modes of operation for the TMS27C240 and TMS27PC240 are listed in Table 2. The read mode
requires a single 5-V supply. All inputs are TTL level except for VPP during programming (13 V for SNAP! Pulse),
and 12 V on A9 for the signature mode.
Table 2. Operation Modes
FUNCTION †
E
G
VPP
VCC
A9
A0
I/O
Read
VIL
VIL
VCC
VCC
X
X
DQ0 – DQ7
DQ8 – DQ15
Output Disable
VIL
VIH
VIL
VIH
X
VCC
VCC
VCC
VCC
X
X
Hi-Z
X
X
Hi-Z
VIH
VIL
VPP
VPP
VCC
VCC
X
X
Data In
X
X
Data Out
VIH
VPP
VCC
X
X
Hi-Z
Standby
Programming
Verify
Program Inhibit
VIH
VIH
Signature Mode (Mfg)
VIL
VIL
VCC
VCC
VH‡
VIL
Manufacturer’s
Code
0097
Signature Mode (Device)
VIL
VIL
VCC
VCC
VH‡
VIH
Device Code
0030
† X can be VIL or VIH.
‡ VH = 12 V ± 0.5 V.
read/ output disable
When the outputs of two or more TMS27C240s or TMS27PC240s are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from the competing outputs
of the other devices. To read the output of a single device, a low-level signal is applied to the E and G pins. All
other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these
pins.
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TMS27C240 262144 BY 16-BIT UV ERASABLE
TMS27PC240 262144 BY 16-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS240D– NOVEMBER 1990 – REVISED SEPTEMBER 1997
latchup immunity
Latchup immunity on the TMS27C240 and TMS27PC240 is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P.C. board level when the devices
are interfaced to industry-standard TTL or MOS logic devices. Input-output layout approach controls latchup
without compromising performance or packing density.
power down
Active ICC supply current can be reduced from 50 mA to 1 mA by applying a high TTL input on E and to
100 µA by applying a high CMOS input on E. In this mode all outputs are in the high-impedance state.
erasure ( TMS27C240)
Before programming, the TMS27C240 is erased by exposing the chip through the transparent lid to a high
intensity ultraviolet light (wavelength 2537 Å). The recommended minimum exposure dose (UV intensity ×
exposure time) is 15-W⋅s / cm2. A 12-mW / cm2, filterless UV lamp erases the device in 21 minutes. The lamp
should be located about 2.5 cm above the chip during erasure. After erasure, all bits are in the high state. It
should be noted that normal ambient light contains the correct wavelength for erasure. Therefore, when using
the TMS27C240, the window should be covered with an opaque label.
initializing ( TMS27PC240)
The one-time programmable TMS27PC240 PROM is provided with all bits in the logic high state, then logic lows
are programmed into the desired locations. Logic lows programmed into an OTP PROM cannot be erased.
SNAP! Pulse programming
The TMS27C240 and TMS27PC240 are programmed by using the SNAP! Pulse programming algorithm. The
programming sequence is shown in the SNAP! Pulse programming flow chart, shown in Figure 1.
The initial setup is VPP = 13 V, VCC = 6.5 V, E = VIH, and G = VIH. Once the initial location is selected, the data
is presented in parallel (eight bits) on pins DQ0 through DQ15. Once addresses and data are stable, the
programming mode is achieved when E is pulsed low ( VIL) with a pulse duration of tw(PGM). Every location is
programmed only once before going to interactive mode.
In the interactive mode, the word is verified at VPP = 13 V, VCC = 6.5 V, E = VIH, and G = VIL. If the correct data
is not read, the programming is performed by pulling E low with a pulse duration of tw(PGM). This sequence of
verification and programming is performed up to a maximum of 10 times. When the device is fully programmed,
all bytes are verified with VCC = VPP = 5 V ± 10%.
program inhibit
Programming can be inhibited by maintaining a high level input on the E and G pins.
program verify
Programmed bits can be verified with VPP = 13 V when G = VIL and E = VIH.
4
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TMS27C240 262144 BY 16-BIT UV ERASABLE
TMS27PC240 262144 BY 16-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS240D– NOVEMBER 1990 – REVISED SEPTEMBER 1997
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode is
activated when A9 ( pin 31 for the J package) is forced to 12 V. Two identifier bytes are accessed by toggling
A0. DQ0–DQ7 contain the valid codes. All other addresses must be held low. The signature code for these
devices is 9730. A0 low selects the manufacturer’s code 97 ( Hex), and A0 high selects the device code 30
( Hex), as shown in Table 3.
Table 3. Signature Mode
IDENTIFIER†
MANUFACTURER CODE
DEVICE CODE
PINS
A0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
HEX
VIL
VIH
1
0
0
1
0
1
1
1
97
0
0
1
1
0
0
0
0
30
† E = G = VIL, A9 = VH, A1 – A8 = VIL, A10 – A17 = VIL, VPP = VCC, PGM = VIH or VIL.
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TMS27C240 262144 BY 16-BIT UV ERASABLE
TMS27PC240 262144 BY 16-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS240D– NOVEMBER 1990 – REVISED SEPTEMBER 1997
Start
Address = First Location
Program
Mode
VCC = 6.5 V, VPP = 13 V
Program One Pulse = tw = 100 µs
Increment Address
No
Last
Address?
Yes
Address = First Location
X=0
Program One Pulse = tw = 100 µs
No
Increment
Address
Verify
One Byte
Fail
X=X+1
X = 10?
Interactive
Mode
Pass
No
Last
Address?
Yes
Yes
VCC = VPP = 5 V ±10%
Compare
All Bytes
To Original
Data
Device Failed
Fail
Final
Verification
Pass
Device Passed
Figure 1. SNAP! Pulse Programming Flow Chart
6
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TMS27C240 262144 BY 16-BIT UV ERASABLE
TMS27PC240 262144 BY 16-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS240D– NOVEMBER 1990 – REVISED SEPTEMBER 1997
logic symbol†
EPROM 256K × 16
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
E
21
0
22
A∇
19
23
A∇
18
24
A∇
17
25
A∇
16
26
A∇
15
27
A∇
14
28
A∇
13
A∇
12
31
A∇
10
32
A∇
9
33
A∇
8
34
A∇
7
35
A∇
6
36
A∇
5
37
A∇
4
38
A∇
3
A
29
39
2
0
262 143
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
17
[PWR DWN]
&
G
20
EN
† These symbols are in accordance with ANSI / IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers are for the J package.
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TMS27C240 262144 BY 16-BIT UV ERASABLE
TMS27PC240 262144 BY 16-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS240D– NOVEMBER 1990 – REVISED SEPTEMBER 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 7 V
Supply voltage range, VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 13 V
Input voltage range (see Note 1): All inputs except A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to VCC + 1 V
A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 13.5 V
Output voltage range (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to VCC + 1 V
Operating free-air temperature range (’27C240-_ _JL; ’27PC240-_ _ FNL) . . . . . . . . . . . . . . . . 0° C to 70° C
Operating free-air temperature range (’27C240-_ _JE, ’27PC240-_ _FNE) . . . . . . . . . . . . . . – 40° C to 85° C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150° C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
recommended operating conditions
VCC
Supply voltage
VPP
Supply voltage
VIH
High level dc input voltage
High-level
VIL
Low level dc input voltage
Low-level
TA
Operating free-air temperature
TA
Operating free-air temperature
Read mode (see Note 2)
SNAP! Pulse programming algorithm
Read mode
SNAP! Pulse programming algorithm
TTL
CMOS
TTL
CMOS
MIN
NOM
MAX
4.5
5
5.5
6.25
6.5
6.75
VCC – 0.6
12.75
13
VCC+0.6
13.25
V
VCC+0.5
VCC+0.5
V
2
VCC – 0.2
– 0.5
0.8
UNIT
V
V
– 0.5
0.2
’27C240-_ _JL
’27PC240-_ _ FNL
0
70
°C
’27PC240-_ _FNE
’27C240-_ _JE
– 40
85
°C
NOTE 2: VCC must be applied before or at the same time as VPP and removed after or at the same time as VPP. The device must not be inserted
into or removed from the board when VPP or VCC is applied.
8
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TMS27C240 262144 BY 16-BIT UV ERASABLE
TMS27PC240 262144 BY 16-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS240D– NOVEMBER 1990 – REVISED SEPTEMBER 1997
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
VOH
High level dc output voltage
High-level
IOH = – 400 µA
IOH = – 20 µA
VOL
Low level dc output voltage
Low-level
IOL = 2.1 mA
IOL = 20 µA
0.4
II
IO
Input current (leakage)
VI = 0 V to 5.5 V
VO = 0 V to VCC
±1
µA
Output current (leakage)
±1
µA
IPP1
IPP2
VPP supply current
VPP supply current (during program pulse)
VPP = VCC = 5.5 V
VPP = 13 V
10
µA
50
mA
1
mA
100
µA
50
mA
V
VCC – 0.1
E = VIH
E = VCC
VCC = 5.5 V,
E = VIL,
tcycle = minimum cycle time,
outputs open
ICC2 VCC supply current (active)
capacitance over recommended
temperature, f = 1 MHz†
ranges
of
supply
PARAMETER
voltage
and
TEST CONDITIONS
Input capacitance
operating
MIN
VI = 0 V
VO = 0 V
Co
Output capacitance
† Capacitance measurements are made on a sample basis only.
‡ Typical values are at TA = 25°C and nominal voltages.
V
0.1
VCC = 5.5 V,
VCC = 5.5 V,
ICC1 VCC supply current (standby)
Ci
2.4
free-air
TYP‡
MAX
4
8
pF
8
12
pF
UNIT
switching characteristics over recommended ranges of operating conditions (see Notes 3
and 4)
PARAMETER
TEST CONDITIONS
’27C240 - 10
’27 PC240 - 10
MIN
MAX
’27C240 - 12
’27 PC240 - 12
MIN
MAX
’27C240 - 15
’27 PC240 - 15
MIN
UNIT
MAX
ta(A)
Access time from address
100
120
150
ns
ta(E)
Access time from chip enable
100
120
150
ns
ten(G)
Output enable time from G
50
50
50
ns
tdis
Output disable time from G or E, whichever
occurs first†
50
ns
tv(A)
Output data valid time after change of
address, E, or G, whichever occurs first§
CL = 100 pF,
F,
1 Series 74
l d
TTL load,
Input tr ≤ 20 ns,
In
ut tf ≤ 20 ns
Input
0
0
50
0
0
50
0
0
ns
§ Value calculated from 0.5 V delta to measured level.
NOTES: 3. For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low (see Figure 2).
4. Common test conditions apply for tdis except during programming.
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9
TMS27C240 262144 BY 16-BIT UV ERASABLE
TMS27PC240 262144 BY 16-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS240D– NOVEMBER 1990 – REVISED SEPTEMBER 1997
switching characteristics for programming: VCC = 6.5 V and VPP = 13 V (SNAP! Pulse), TA = 25°C
(see Note 3)
PARAMETER
tdis(G)
ten(G)
Output disable time from G
MIN
MAX
UNIT
0
100
ns
150
ns
Output enable time from G
NOTE 3: For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low. (See Figure 2)
timing requirements for programming
NOM
MAX
UNIT
95
100
105
µs
Pulse duration, program
Setup time, address
2
µs
tsu(E)
tsu(G)
Setup time, E
2
µs
Setup time, G
2
µs
tsu(D)
tsu(VPP)
Setup time, data
2
µs
Setup time, VPP
2
µs
tsu(VCC)
th(A)
Setup time, VCC
2
µs
Hold time, address
0
µs
th(D)
Hold time, data
2
µs
10
SNAP! Pulse programming algorithm
MIN
tw(PGM)
tsu(A)
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TMS27C240 262144 BY 16-BIT UV ERASABLE
TMS27PC240 262144 BY 16-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS240D– NOVEMBER 1990 – REVISED SEPTEMBER 1997
PARAMETER MEASUREMENT INFORMATION
2.08 V
RL = 800 Ω
Output
Under Test
CL = 100 pF
(see Note A)
2.4 V
2V
2V
0.8 V
0.40 V
0.8 V
NOTES: A. CL includes probe and fixture capacitance.
B. The ac testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. Timing
measurements are made at 2 V for logic high and 0.8 V for logic low for both inputs
and outputs.
Figure 2. The ac Testing Output Load Circuit and Waveform
A0 – A17
Address Valid
E
ta(E)
G
ten(G)
ta(A)
DQ0 – DQ15
tdis
tv(A)
Output
Valid
Hi-Z
Hi-Z
Figure 3. Read-Cycle Timing
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TMS27C240 262144 BY 16-BIT UV ERASABLE
TMS27PC240 262144 BY 16-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS240D– NOVEMBER 1990 – REVISED SEPTEMBER 1997
PARAMETER MEASUREMENT INFORMATION
Verify
Program
A0 – A17
Address Stable
tsu(A)
DQ0 – DQ15
Data-In Stable
tsu(D)
th(A)
Data-Out
Stable
Hi-Z
ten(G)
tdis(G)
VPP
tsu(VPP)
VCC
tsu(E)
th(D)
tsu(VCC)
E
tsu(G)
tw(PGM)
G
† 13-V VPP and 6.5-V VCC for SNAP! Pulse programming
Figure 4. Programming-Cycle Timing (SNAP! Pulse Programming)
12
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TMS27C240 262144 BY 16-BIT UV ERASABLE
TMS27PC240 262144 BY 16-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS240D– NOVEMBER 1990 – REVISED SEPTEMBER 1997
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
D
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
E
18
D2 / E2
E1
D2 / E2
14
8
0.021 (0,53)
0.013 (0,33)
0.007 (0,18) M
0.050 (1,27)
9
13
0.008 (0,20) NOM
D/E
D2 / E2
D1 / E1
NO. OF
PINS
**
MIN
MAX
MIN
MAX
MIN
MAX
20
0.385 (9,78)
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.169 (4,29)
28
0.485 (12,32)
0.495 (12,57)
0.450 (11,43)
0.456 (11,58)
0.191 (4,85)
0.219 (5,56)
44
0.685 (17,40)
0.695 (17,65)
0.650 (16,51)
0.656 (16,66)
0.291 (7,39)
0.319 (8,10)
52
0.785 (19,94)
0.795 (20,19)
0.750 (19,05)
0.756 (19,20)
0.341 (8,66)
0.369 (9,37)
68
0.985 (25,02)
0.995 (25,27)
0.950 (24,13)
0.958 (24,33)
0.441 (11,20)
0.469 (11,91)
84
1.185 (30,10)
1.195 (30,35)
1.150 (29,21)
1.158 (29,41)
0.541 (13,74)
0.569 (14,45)
4040005 / B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
13
TMS27C240 262144 BY 16-BIT UV ERASABLE
TMS27PC240 262144 BY 16-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS240D– NOVEMBER 1990 – REVISED SEPTEMBER 1997
J (R-CDIP-T**)
CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE
24 PIN SHOWN
B
13
24
C
12
1
Lens Protrusion
0.010 (0,25) MAX
0.065 (1,65)
0.045 (1,14)
0.090 (2,29)
0.060 (1,53)
0.018 (0,46) MIN
0.175 (4,45)
0.140 (3,56)
A
Seating Plane
0°– 10°
0.125 (3,18) MIN
0.022 (0,56)
0.014 (0,36)
0.100 (2,54)
A
B
C
28
24
PINS**
NARR
DIM
0.012 (0,30)
0.008 (0,20)
WIDE
NARR
32
WIDE
NARR
40
WIDE
NARR
WIDE
MAX
0.624(15,85) 0.624(15,85)
0.624(15,85) 0.624(15,85)
0.624(15,85) 0.624(15,85)
0.624(15,85) 0.624(15,85)
MIN
0.590(14,99) 0.590(14,99)
0.590(14,99) 0.590(14,99)
0.590(14,99) 0.590(14,99)
0.590(14,99) 0.590(14,99)
MAX
1.265(32,13) 1.265(32,13)
1.465(37,21) 1.465(37,21)
1.668(42,37) 1.668(42,37)
2.068(52,53) 2.068(52,53)
MIN
1.235(31,37) 1.235(31,37)
1.435(36,45) 1.435(36,45)
1.632(41,45) 1.632(41,45)
2.032(51,61) 2.032(51,61)
MAX
0.541(13,74) 0.598(15,19)
0.541(13,74) 0.598(15,19)
0.541(13,74) 0.598(15,19)
0.541(13,74) 0.598(15,19)
MIN
0.514(13,06) 0.571(14,50)
0.514(13,06) 0.571(14,50)
0.514(13,06) 0.571(14,50)
0.514(13,06) 0.571(14,50)
4040084 / B 04/95
NOTES: A.
B.
C.
D.
14
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
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