TI 74ACT16863

54ACT16863, 74ACT16863
18-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS162B – JUNE 1990 – REVISED NOVEMBER 1996
D
D
D
D
D
D
D
D
54ACT16863 . . . WD PACKAGE
74ACT16863 . . . DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus  Family
Inputs Are TTL-Voltage Compatible
3-State Outputs Drive Bus Lines Directly
Flow-Through Architecture Optimizes
PCB Layout
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
EPIC  (Enhanced-Performance Implanted
CMOS) 1-µm Process
500-mA Typical Latch-Up Immunity at
125°C
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
1OEAB
1B1
1B2
GND
1B3
1B4
VCC
1B5
1B6
1B7
GND
1B8
1B9
GND
GND
2B1
2B2
GND
2B3
2B4
2B5
VCC
2B6
2B7
GND
2B8
2B9
2OEAB
description
The ’ACT16863 are 18-bit noninverting
transceivers
designed
for
asynchronous
communication between data buses. The
control-function
implementation
minimizes
external timing requirements.
The ’ACT16863 can be used as two 9-bit
transceivers or one 18-bit transceiver. They allow
data transmission from the A bus to the B bus or
from the B bus to the A bus, depending on the logic
level at the output-enable (OEAB or OEBA)
inputs.
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OEBA
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
1A7
GND
1A8
1A9
GND
GND
2A1
2A2
GND
2A3
2A4
2A5
VCC
2A6
2A7
GND
2A8
2A9
2OEBA
The 74ACT16863 is packaged in TI’s shrink small-outline package (DL), which provides twice the I/O pin count
and functionality of standard small-outline packages in the same printed-circuit-board area.
The 54ACT16863 is characterized for operation over the full military temperature range of –55°C to 125°C. The
74ACT16863 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 9-bit section)
INPUTS
OPERATION
OEAB
OEBA
H
L
B data to A bus
L
H
A data to B bus
H
H
Isolation
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
54ACT16863, 74ACT16863
18-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS162B – JUNE 1990 – REVISED NOVEMBER 1996
logic symbol†
56
EN1
1OEBA
1OEAB
1
EN2
29
EN3
2OEBA
2OEAB
1A1
28
EN4
55
1
1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
1A9
2A1
3
52
5
51
6
49
8
48
9
47
10
45
12
44
13
41
16
3
2A3
2A4
2A5
2A6
2A7
2A8
2A9
1B1
2
54
1
1
2A2
2
1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
1B9
2B1
4
40
17
38
19
37
20
36
21
34
23
33
24
31
26
30
27
2B2
2B3
2B4
2B5
2B6
2B7
2B8
2B9
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1OEBA
1OEAB
1A1
56
2OEBA
1
2OEAB
55
2
1B1
2A1
29
28
41
To Eight Other Channels
2
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16
To Eight Other Channels
• DALLAS, TEXAS 75265
2B1
54ACT16863, 74ACT16863
18-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS162B – JUNE 1990 – REVISED NOVEMBER 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±450 mA
Maximum package power dissipation at TA = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . . 1.4 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.
recommended operating conditions (see Note 2)
54ACT16863
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
High-level output current
IOL
∆t/∆v
Low-level output current
High-level input voltage
74ACT16863
MIN
2
2
0.8
Input transition rise or fall rate
0
TA
Operating free-air temperature
–55
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
UNIT
V
V
0.8
V
VCC
VCC
V
–24
–24
mA
24
24
mA
VCC
VCC
0
0
V
10
0
10
ns/V
125
–40
85
°C
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
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54ACT16863, 74ACT16863
18-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS162B – JUNE 1990 – REVISED NOVEMBER 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
4.5 V
IOH = –50
50 µA
VOH
24 mA
IOH = –24
IOH = –50 mA†
IOH = –75 mA†
TA = 25°C
TYP
MAX
54ACT16863
MIN
MAX
MIN
4.4
4.4
5.5 V
5.4
5.4
5.4
4.5 V
3.94
3.7
3.8
5.5 V
4.94
4.7
4.8
MAX
V
3.85
4.5 V
0.1
0.1
5.5 V
0.1
0.1
0.1
4.5 V
0.36
0.5
0.44
5.5 V
0.36
0.5
0.44
IOL = 50 mA†
IOL = 75 mA†
5.5 V
UNIT
3.85
5.5 V
IOL = 24 mA
74ACT16863
4.4
5.5 V
IOL = 50 µA
VOL
MIN
0.1
V
1.65
5.5 V
1.65
II
Control inputs
VI = VCC or GND
5.5 V
±0.1
±1
±1
µA
IOZ‡
ICC
A or B ports
VO = VCC or GND
5.5 V
±0.5
±10
±5
µA
VI = VCC or GND,
IO = 0
One input at 3.4 V,
Other inputs at VCC or GND
5.5 V
8
160
80
µA
5.5 V
0.9
1
1
mA
∆ICC§
Ci
Control inputs
VI = VCC or GND
VO = VCC or GND
5V
4.5
pF
Cio
A or B ports
5V
17
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
§ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
pF
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
B or A
tPZH
tPZL
OEBA or OEAB
A or B
tPHZ
tPLZ
OEBA or OEAB
A or B
MIN
TA = 25°C
TYP
MAX
54ACT16863
74ACT16863
MIN
MAX
MIN
MAX
4.1
7
9.9
4.1
12.1
4.1
11.1
3.1
6.4
10.6
3.1
12.5
3.1
11.8
3
5.9
9.6
3
11.5
3
10.6
3.9
7.4
12.3
3.9
14.7
3.9
13.6
5.7
8.2
10.6
5.7
12.3
5.7
11.6
5.4
7.7
10
5.4
11.6
5.4
11
UNIT
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance per transceiver
TEST CONDITIONS
Outputs enabled
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
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• DALLAS, TEXAS 75265
CL = 50 pF,
f = 1 MHz
TYP
62
UNIT
pF
54ACT16863, 74ACT16863
18-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS162B – JUNE 1990 – REVISED NOVEMBER 1996
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
Output
Control
(low-level
enabling)
3V
1.5 V
1.5 V
0V
tPLH
tPHL
VOH
Output
S1
Open
2 × VCC
GND
500 Ω
LOAD CIRCUIT
Input
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
50% VCC
50% VCC
VOL
3V
0V
tPZL
[ VCC
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
1.5 V
50% VCC
VOL
tPHZ
tPZH
VOLTAGE WAVEFORMS
20% VCC
50% VCC
80% VCC
VOH
[0V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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Copyright  1998, Texas Instruments Incorporated