SN54ALS841, SN54AS841, SN54ALS842, SN54AS842 SN74ALS841, SN74AS841, SN74ALS842, SN74AS842 10-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS059B – D2910, DECEMBER 1983 – REVISED MAY 1986 • • • • 3-State Buffer-Type Outputs Drive Bus-Lines Directly • • Bus-Structured Pinout Provide Extra Bus Driving Latches Necessary for Wider Address/Data Paths or Buses with Parity Buffered Control Inputs to Reduce DC Loading • Power-Up High-Impedance State Package Options Include Plastic Small Outline Packages, Both Plastic and Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs Dependable Texas Instruments Quality and Reliability description These 10-bit latches feature 3-state outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The ten latches are transparent D-type. The ’ALS841 and ’AS841 have noninverting data (D) inputs. The ’ALS842 and ’AS842 have inverting D inputs. SN54ALS841, SN54AS841 . . . JT PACKAGE SN74ALS841, SN74AS841 . . . DW OR NT PACKAGE SN54ALS841, SN54AS841 . . . FK PACKAGE SN74ALS841, SN74AS841 . . . FN PACKAGE (TOP VIEW) 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q C SN54ALS842, SN54AS842 . . . JT PACKAGE SN74ALS842, SN74AS842 . . . DW OR NT PACKAGE 3D 4D 5D NC 6D 7D 8D 4 5 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 SN54ALS842, SN54AS842 . . . FK PACKAGE SN74ALS842, SN74AS842 . . . FN PACKAGE (TOP VIEW) 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q C 2D 1D OC NC VCC 1Q 2Q 24 3Q 4Q 5Q NC 6Q 7Q 8Q 3D 4D 5D NC 6D 7D 8D 4 5 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 3Q 4Q 5Q NC 6Q 7Q 8Q 9D 10D GND NC C 10Q 9Q 1 25 6 (TOP VIEW) OC 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D GND 3 2 1 28 27 26 9D 10D GND NC C 10Q 9Q OC 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D GND 2D 1D OC NC VCC 1Q 2Q (TOP VIEW) Copyright 1986, Texas Instruments Incorporated 5BASIC PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ALS841, SN54AS841, SN54ALS842, SN54AS842 SN74ALS841, SN74AS841, SN74ALS842, SN74AS842 10-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS059B – D2910, DECEMBER 1983 – REVISED MAY 1986 description (continued) A buffered output control (OC) input can be used to place the ten outputs in either a normal logic state (high or low levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive the bus lines in a bus-organized system without need for interface or pullup components. The output control does not affect the internal operation of the latches. Old data can be retained or new data can be entered while the outputs are off. The - 1 versions of the SN74ALS841 and SN74ALS842 parts are identical to the standard versions except that the recommended maximum IOL is increased to 48 mA. There are no - 1 versions of the SN54ALS841 and SN54ALS842. The SN54ALS841, SN54AS841, SN54ALS842, and SN54AS842 are characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74ALS841, SN74AS841, SN74ALS842, and SN74AS842 are characterized for operation from 0°C to 70°C. Function Tables ’ALS841, ’AS841 INPUTS OC C L H L H L L H X 2 D H L X X OUTPUT Q H L Q0 Z POST OFFICE BOX 655303 ’ALS842, ’AS842 INPUTS OC C L H L H L L H X • DALLAS, TEXAS 75265 D H L X X OUTPUT Q L H Q0 Z SN54ALS841, SN54AS841, SN74ALS841, SN74AS841 10-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS059B – D2910, DECEMBER 1983 – REVISED MAY 1986 ’ALS841, ’AS841 logic symbol† OC C 1 13 ’ALS841, ’AS841 logic diagram (positive logic) OC EN C1 C 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D 2 3 4 5 6 7 8 9 10 11 1D 23 22 21 20 19 18 17 16 15 14 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and EC Publication 617-12. 1 13 C1 1D 2 C1 2D 3 3D 4D 5D 6D 7D 8D 10 10D 19 5Q 18 6Q 17 7Q 16 8Q 15 9Q 1D C1 11 4Q 1D C1 9D 20 1D C1 9 3Q 1D C1 8 21 1D C1 7 2Q 1D C1 6 22 1D C1 5 1Q 1D C1 4 23 1D 14 10Q 1D Pin numbers shown are for DW, JT, and NT packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ALS841, SN54AS841, SN54ALS842, SN54AS842 SN74ALS841, SN74AS841, SN74ALS842, SN74AS842 10-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS059B – D2910, DECEMBER 1983 – REVISED MAY 1986 ’ALS842, ’AS842 logic symbol† OC C 1 13 ’ALS842, ’AS842 logic diagram (positive logic) OC EN C1 C 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D 2 3 4 5 6 7 8 9 10 11 1D 23 22 21 20 19 18 17 16 15 14 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 1 13 C1 1D 2 C1 2D 3 3D 4D 5D 6D 7D 8D 10 10D 19 5Q 18 6Q 17 7Q 16 8Q 15 9Q 1D C1 11 4Q 1D C1 9D 20 1D C1 9 3Q 1D C1 8 21 1D C1 7 2Q 1D C1 6 22 1D C1 5 1Q 1D C1 4 23 1D 14 10Q 1D Pin numbers shown are for DW, JT, and NT packages. absolute maximum ratings over operating free-air temperature range unless otherwise noted Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range: SN54ALS841, SN54AS841, SN54ALS842, SN54AS842 . . . . . . – 55°C to 125°C SN74ALS841, SN74AS841, SN74ALS842, SN74AS842 . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ALS841, SN74ALS841 10-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS059B – D2910, DECEMBER 1983 – REVISED MAY 1986 recommended operating conditions SN54ALS841 SN74ALS841 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.7 0.8 High-level output current –1 – 2.6 mA IOL Low level output current Low-level 12 24 48† mA tw tsu Pulse duration, C high 25 20 ns Setup time, data before C↓ 16 10 ns High-level input voltage 2 2 th Hold time,, data after C↓ 7 TA Operating free-air temperature – 55 125 † The 48-mA limit applies only to the - 1 versions and only if VCC is maintained between 4.75 V and 5.25 V. V V 5 V ns 0 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VOL IOZH IOZL II IIH IIL IO§ ICC SN54ALS841 TYP‡ MAX TEST CONDITIONS MIN SN74ALS841 TYP‡ MAX MIN VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = – 18 mA IOH = – 0.4 mA VCC = 4.5 V, VCC = 4.5 V, IOH = – 1 mA IOH = – 2.6 mA VCC = 4.5 V, VCC = 4.5 V, IOL = 12 mA IOL = 24 mA VCC = 4.75 V, VCC = 5.5 V, IOL = 48 mA (–1 versions) VO = 2. 7 V 20 20 VCC = 5.5 V, VCC = 5.5 V, VO = 0.4 V VI = 7 V – 20 – 20 µA 0.1 0.1 mA VCC = 5.5 V, VCC = 5.5 V, VO = 2.7 V VI = 0 .4 V 20 20 µA – 0.1 mA VCC = 5.5 V, VO = 2.25 V Outputs high – 112 mA VCC = 5.5 V – 1.2 VCC – 2 2.4 – 1.2 UNIT V VCC – 2 3.3 V 2.4 0.25 0.4 3.2 0.25 0.4 0.35 0.5 0.35 0.5 – 0.1 – 30 – 112 – 30 19 30 19 30 Outputs low 38 62 38 62 Outputs disabled 23 40 23 40 V µA mA ‡ All typical values are at VCC = 5 V, TA = 25°C. § The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54ALS841, SN74ALS841 10-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS059B – D2910, DECEMBER 1983 – REVISED MAY 1986 ’ALS841 switching characteristics (see Note 1) PARAMETER FROM TO (INPUT) (OUTPUT) VCC = 5 V, CL = 50 pF, VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 Ω, R1 = 500 Ω, R2 = 500 Ω, R2 = 500 Ω, MIN tPLH tPHL D Q tPLH tPHL C Q tPZH tPZL OC Q tPHZ tPLZ OC Q UNIT TA = MIN to MAX† SN54ALS841 SN74ALS841 TA = 25°C ′ALS841 TYP MAX MIN MAX MIN MAX 8.5 11 2 15 2 13 8.5 11 2 15 2 13 14 18 7 25 7 21 17 23 8 30 8 26 7.5 10 2 14 2 12 7.5 10 2 14 2 12 6 8 2 12 2 10 7 9 2 14 2 12 † The conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. NOTE 1: Load circuit and voltage waveforms are shown in Section 1. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns ns ns ns SN54ALS842, SN74ALS842 10-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS059B – D2910, DECEMBER 1983 – REVISED MAY 1986 recommended operating conditions SN54ALS842 SN74ALS842 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.7 0.8 High-level output current –1 – 2.6 mA IOL Low level output current Low-level 12 24 48† mA tw tsu Pulse duration, C high 25 20 ns Setup time, data before C↓ 16 10 ns High-level input voltage 2 2 th Hold time,, data after C↓ 7 TA Operating free-air temperature – 55 125 † The 48-mA limit applies only to the – 1 versions and only if VCC is maintained between 4.75 V and 5.25 V. V V 5 V ns 0 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VOL IOZH IOZL II IIH IIL IO§ ICC SN54ALS842 TYP‡ MAX TEST CONDITIONS MIN SN74ALS842 TYP‡ MAX MIN VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = – 18 mA IOH = – 0.4 mA VCC = 4.5 V, VCC = 4.5 V, IOH = – 1 mA IOH = – 2.6 mA VCC = 4.5 V, VCC = 4.5 V, IOL = 12 mA IOL = 24 mA VCC = 4.75 V, VCC = 5.5 V, IOL = 48 mA (- 1 versions) VO = 2. 7 V 20 20 VCC = 5.5 V, VCC = 5.5 V, VO = 0.4 V VI = 7 V – 20 – 20 µA 0.1 0.1 mA VCC = 5.5 V, VCC = 5.5 V, VO = 2.7 V VI = 0.4 V 20 20 µA – 0.1 mA VCC = 5.5 V, VO = 2.25 V Outputs high – 112 mA VCC = 5.5 V – 1.2 VCC – 2 2.4 – 1.2 UNIT V VCC – 2 3.3 V 2.4 0.25 0.4 3.2 0.25 0.4 0.35 0.5 0.35 0.5 – 0.1 – 30 – 112 – 30 20 35 20 35 Outputs low 48 74 48 74 Outputs disabled 27 44 27 44 V µA mA ‡ All typical values are at VCC = 5 V, TA = 25°C. § The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN54ALS842, SN74ALS842 10-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS059B – D2910, DECEMBER 1983 – REVISED MAY 1986 ’ALS842 switching characteristics (see Note 1) PARAMETER FROM TO (INPUT) (OUTPUT) VCC = 5 V, CL = 50 pF, VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 Ω, R1 = 500 Ω, R2 = 500 Ω, R2 = 500 Ω, MIN tPLH tPHL D Q tPLH tPHL C Q tPZH tPZL OC Q tPHZ tPLZ OC Q TA = MIN to MAX† SN54ALS842 SN74ALS842 TA = 25°C ’ALS842 TYP MIN MAX MIN MAX 11 MAX 15 4 22 4 18 8 11 3 17 3 13 17 23 8 31 8 27 13 18 6 24 6 20 8 10 2 14 2 12 8 11 2 14 2 12 6 8 1 12 1 10 7 9 2 14 2 12 † The conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. NOTE 1: Load circuit and voltage waveforms are shown in Section 1. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ns ns ns ns SN54AS841, SN54AS842, SN74AS841, SN54AS842 10-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS059B – D2910, DECEMBER 1983 – REVISED MAY 1986 recommended operating conditions SN54AS841 SN54AS842 VCC VIH Supply voltage VIL IOH Low-level input voltage IOL tw Low-level output current tsu th Setup time, data before C↓ TA Operating free-air temperature High-level input voltage SN74AS841 SN74AS842 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 2 2 High-level output current Hold time,, data after C↓ V V 0.8 0.8 V – 24 – 24 mA 48 mA 32 Pulse duration, C high UNIT 5 4 ns 3.5 2.5 ns 3.5 2.5 – 55 125 ns 0 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54AS841 PARAMETER VIK TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = – 18 mA IOH = – 2 mA VCC = 4.5 V, VCC = 4.5 V, IOH = – 15 mA IOH = – 24 mA VOL VCC = 4.5 V, VCC = 4.5 V, IOL = 32 mA IOL = 48 mA IOZH IOZL VCC = 5.5 V, VCC = 5.5 V, VO= 2. 7 V VO = 0.4 V II IIH VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VO = 2.7 V IIL IO‡ VCC = 5.5 V, VCC = 5.5 V, VI = 0 .4 V VO = 2.25 V VOH ’AS841 ICC VCC = 5 5.5 5V ’AS842 SN74AS841 SN54AS842 MIN TYP‡ MAX SN74AS842 TYP‡ MAX – 1.2 VCC – 2 2.4 – 1.2 VCC – 2 2.4 3.2 2 UNIT MIN 3.2 V V 2 0.25 0.5 0.35 V µA 50 50 – 50 – 50 µA 0.1 0.1 mA 20 20 µA – 0.5 mA – 112 mA – 0.5 – 30 0.5 – 112 – 30 Outputs high 36 60 36 60 Outputs low 58 94 58 94 Outputs disabled 56 92 56 92 Outputs high 38 62 38 62 Outputs low 60 97 60 97 Outputs disabled 58 95 58 mA 95 † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN54AS841, SN54AS842, SN74AS841, SN54AS842 10-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS059B – D2910, DECEMBER 1983 – REVISED MAY 1986 ’AS841 switching characteristics (see Note 1) VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 Ω, PARAMETER FROM TO (INPUT) (OUTPUT) tPLH tPHL D Q tPLH tPHL C Q tPZH tPZL OC Q tPHZ tPLZ OC Q R2 = 500 Ω, TA = MIN to MAX† SN54AS841 SN74AS841 MIN MAX MIN MAX 1 8.5 1 6.5 1 10 1 9 2 13 2 12 2 13 2 12 2 13.5 2 10.5 2 15 2 13.5 1 10 1 8 1 10 1 8 UNIT ns ns ns ns ’AS842 switching characteristics (see Note 1) VCC = 4.5 V to 5.5 V, CL = 50 pF, PARAMETER FROM (INPUT) R1 = 500 Ω, TO (OUTPUT) tPLH tPHL D Q tPLH tPHL C Q tPZH tPZL OC Q tPHZ tPLZ OC Q R2 = 500 Ω, UNIT TA = MIN to MAX† SN54AS842 SN74AS842 MIN MAX MIN MAX 1 11 1 8.5 1 10 1 9 2 13 2 12 2 13 2 12 2 14.5 2 12 2 15 2 12.5 1 10 1 8 1 10 1 8 † The conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. NOTE 1: Load circuit and voltage waveforms are shown in Section 1. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns ns ns ns IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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