VITESSE VSC7959W

VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7959
3.125Gb/s CML Limiting Amplifier with LOS Detect
Features
Applications
• SONET/SDH at 622Mb/s, 1.244Gb/s, 2.488Gb/s,
and 3.125Gb/s
• Full-Speed Fibre Channel (1.062Gb/s)
• Small Form Factor (SFF) Receivers
• ATM Optical Receivers
• 3.3V or 5V Power Supply
• Typical Supply Current of 32mA
• Current-Mode Logic Outputs
• Optional Output Squelch
• Loss of Signal Detect
• Output Offset Correction
• Rise/Fall Times Faster than 100ps
• Packages: TSSOP-16, Bare Die
General Description
The VSC7959 is a single supply limiting amplifier with Loss of Signal (LOS) detect for SONET/SDH and
Fibre Channel applications up to 3.125Gb/s. The VSC7959 provides a constant output signal swing for a wide
range of input voltages and has Current-Mode Logic (CML) outputs. The VSC7961 provides the same functionality as the VSC7959 with positive emitter-coupled logic (PECL) outputs. Key features of the VSC7959 are its
RMS power detectors for programmable LOS detection, optional output squelch, adjustable output levels,
excellent jitter performance, and fast edge rates. The VSC7959 is available in die form or in a TSSOP-16 package.
Block Diagram
VSC7959
VCC
8kΩ
LOS
VCC
8kΩ
TH
LOS
SQUELCH
RMS Power
Detect and
Control
Output Control
IN+
LEVEL
OUT+
100Ω
OUT-
IN-
Lowpass Filter
10pF
Offset Correction
CZ1
G52358-0, Rev 2.0
02/09/01
CZ2
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected]
Internet: www.vitesse.com
Page 1
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7959
3.125Gb/s CML Limiting Amplifier with LOS Detect
Electrical Characteristics
Table 1: DC Specifications
Symbol
Parameter
VCC
Power Supply Voltage
ICC
Power Supply Current(1)
IEE
Power Supply Current(1)
ICCSQ
Min
Typ
3.135
Max
Units
5.5
V
Conditions
31
mA
VCC = 3.3V
35
mA
VCC = 5V
38
mA
VCC = 3.3V
43
mΑ
VCC = 5V
Power Supply Current when
Squelched(1)
21
mA
VCC = 3.3V
25
mA
VCC = 5V
IEESQ
Power Supply Current when
Squelched(1)
24
mA
VCC = 3.3V
28
mA
VCC = 5V
ISQ
Squelch Input Current
0
PSSR
Power Supply Rejection Ratio
20
400
µA
30
dB
f < 2MHz
NOTE: (1) See Figure 5 for supply current measurement setup.
Table 2: DC Specifications
Symbol
Parameter
VIN
JD
JR
tR, tF
VN
RDIFF
Data Rate
Input Voltage Range
Deterministic Jitter
Random Jitter
Rise and Fall Times
Input Referred Noise
Differential Input Resistance
fL
Low Frequency Cutoff
VSQ
Output Signal When Squelched
VCML
CML Output Voltage
ZO
Output Resistance
Min
Typ
3.125
10
55
Max
1200
25
8
100
230
100
2
2
20
1200
1800
20
550
1100
100
Units
Gb/s
mV
ps
ps
ps
µV
Ω
MHz
kHz
mV
mV
mV
mV
Ω
Conditions
Peak-to-peak
See Note 1
See Note 2, RMS
20% to 80%
RMS, IN+ to ININ+ to INCZ open
CZ = 0.1µF
Output AC-coupled
Level = open, RL = 50Ω
Level = GND, RL = 75Ω
Squelched
Single-ended
NOTES: (1) Deterministic jitter measured peak-to-peak with K28.5 pattern. (2) Random jitter measured with minimum input.
Page 2
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected]
Internet: www.vitesse.com
G52358-0, Rev 2.0
02/09/01
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7959
3.125Gb/s CML Limiting Amplifier with LOS Detect
Table 3: Loss of Signal Specifications
Symbol
Parameter
Min
Typ
Max
Units
HLOS
LOS Hystersis
3.1
3.3
5.5
dB
ILOS
LOS Assert/Deassert Time
0.22
0.25
0.28
µs
8.2
VTHA
LOS Assert Threshold
VTHD
12.8
LOS Deassert Threshold
VLOSH
LOS Output HIGH Voltage
VLOSL
LOS Output LOW Voltage
19.8
21.8
Conditions
HLOS = 20 log (VTHD/VTHA)
mV
RTH = 2.5kΩ
mV
RTH = 7kΩ
57.2
mV
RTH = 20kΩ
11.4
mV
RTH = 2.5kΩ
mV
RTH = 7kΩ
75.2
mV
RTH = 20kΩ
V
ILOS = –30µA
0.168
V
ILOS = +1.2µA
26.2
29.0
3.3
31.6
Table 4: Loss of Signal Truth Table
SQUELCH
LOS
Output
High
Low
Off
Low
High
On
High
Low
On
Low
Low
On
Absolute Maximum Ratings(1)
Power Supply Voltage (VCC)............................................................................................................. -0.5V to +6V
Maximum Junction Temperature Range .........................................................................................................TBD
Storage Temperature Range (TS)................................................................................................. -55°C to +150°C
NOTE: (1) CAUTION: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended
periods may affect device reliability.
Recommended Operating Conditions
Positive Voltage Rail (VCC).................................................................................................................. 3.3V or 5V
Junction Temperature Range (TJ)................................................................................................ -40°C to +100°C
Ambient Temperature Range (TA)................................................................................................. -40°C to +85°C
G52358-0, Rev 2.0
02/09/01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected]
Internet: www.vitesse.com
Page 3
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7959
3.125Gb/s CML Limiting Amplifier with LOS Detect
Package Pin Descriptions
Figure 1: Pin Diagram
Top View
TSSOP-16 Package
CZ1
1
16
NC
CZ2
2
15
SQUELCH
GND
3
14
VCC
IN+
4
13
OUT+
VSC7959
IN-
5
12
OUT-
GND
6
11
VCC
LEVEL
7
10
LOS
TH
8
9
LOS
Table 5: Pin Identifications
Pin Name
Pin No.
Description
CZ1
1
Offset Correction Loop Capacitor. Place capacitor between this pin and CZ2 to alter time constant
of offset correction loop. See Detailed Description section.
CZ2
2
Offset Correction Loop Capacitor. Place capacitor between this pin and CZ1 to alter time constant
of offset correction loop. See Detailed Description section.
GND
3
Supply Ground
IN+
4
Noninverted Input Signal
IN-
5
Inverted Input Signal
GND
6
Supply Ground
LEVEL
7
Output Current Level. This pin may either be connected to ground or left unconnected. Connecting
to ground causes output current to be 20mA. The output is 16mA when left unconnected. See
Detailed Description section.
TH
8
Loss of Signal (LOS) Threshold. Connect a resistor from this pin to ground to set the input signal
level at which LOS outputs will be asserted. See Application Information section.
LOS
9
Inverted Loss of Signal Output. LOS is HIGH for input signals above the threshold programmed by
TH. See Detailed Description section.
LOS
10
Noninverted Loss of Signal Output. LOS is LOW for input signals above the threshold programmed
by TH. See Detailed Description section.
VCC
11
Power Supply
OUT-
12
Inverted Data Output
OUT+
13
Noninverted Data Output
VCC
14
Power Supply
SQUELCH
15
Squelch Input. Squelch is disabled if this pin is unconnected or set LOW. When SQUELCH is
HIGH, OUT+ and OUT- are forced to static levels.
NC
16
No Connection
Page 4
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodi[email protected]
Internet: www.vitesse.com
G52358-0, Rev 2.0
02/09/01
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7959
3.125Gb/s CML Limiting Amplifier with LOS Detect
Bare Die Descriptions
Figure 2: Pad Assignments
1597µm (0.06287")
Pad1
CAZ1
1597µm
(0.06287")
Pad 16
NC
Pad 2
CAZ2
Pad 15
SQ
Pad 3
GNDA
Pad 14
VCCA
Pad 4
LAINP
Pad 13
LAOP
VSC7959
Pad 5
LAINM
Pad 12
LAOM
Pad 6
GNDA
Pad 11
VCCA
Pad 7
LVL
Pad 10
LOS
Pad 8
TH
Pad 9
LOS
Die Size:
1597µm x 1597µm (0.06287" x 0.06287")
Pad Pitch:
180µm (0.00709")
Pad Passivation Opening: 95µm x 95µm (0.00374" x 0.00374")
The back side of the die may either be left floating or connected ot ground.
G52358-0, Rev 2.0
02/09/01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected]
Internet: www.vitesse.com
Page 5
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7959
3.125Gb/s CML Limiting Amplifier with LOS Detect
Table 6: Pad Coordinates
Pad
Name
Pin Name
Pad/Pin
Number
Coordinates (µm)
Description
X
Y
CZ1
CZ1
1
270.525
1359.05
Offset Correction Loop Capacitor. Place capacitor between
this pin and CZ2 to alter time constant of offset correction
loop. See Detailed Description section.
CZ2
CZ2
2
80.95
1170.525
Offset Correction Loop Capacitor. Place capacitor between
this pin and CZ1 to alter time constant of offset correction
loop. See Detailed Description section.
GNDA
GND
3
80.95
990.525
Supply Ground
LAINP
IN+
4
80.95
810.525
Noninverted Input Signal
LAINM
IN-
5
80.95
630.525
Inverted Input Signal
GNDA
GND
6
80.95
450.525
Supply Ground
270.525
Output Current Level. This pin may either be connected to
ground or left unconnected. Connecting to ground causes
output current to be 20mA. The output is 16mA when left
unconnected. See Detailed Description section.
LVL
LEVEL
7
80.95
TH
TH
8
270.525
80.95
Loss of Signal (LOS) Threshold. Connect a resistor from
this pin to ground to set the input signal level at which LOS
outputs will be asserted. See Application Information
section.
LOS
LOS
9
1169.475
80.95
Inverted Loss of Signal Output. LOS is HIGH for input
signals above the threshold programmed by TH. See
Detailed Description section.
LOS
LOS
10
1359.05
270.525
Noninverted Loss of Signal Output. LOS is LOW for input
signals above the threshold programmed by TH. See
Detailed Description section.
VCCA
VCC
11
1359.05
450.525
Power Supply
LOAM
OUT-
12
1359.05
630.525
Inverted Data Output
LAOP
OUT+
13
1359.05
810.525
Noninverted Data Output
VCCA
VCC
14
1359.05
990.525
Power Supply
SQ
SQUELCH
15
1359.05
1170.525
Squelch Input. Squelch is disabled if this pin is unconnected
or set LOW. When SQUELCH is HIGH, OUT+ and OUTare forced to static levels.
—
NC
—/16
1169.475
1359.05
No Connection
Page 6
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected]
Internet: www.vitesse.com
G52358-0, Rev 2.0
02/09/01
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7959
3.125Gb/s CML Limiting Amplifier with LOS Detect
Detailed Description
The VSC7959 is a high speed limiting amplifier with Loss-of-Signal (LOS) detect. The device is designed
to operate with a 3.3V or 5V supply in SDH/SONET and Fibre Channel applications up to 3.125Gb/s. The
VSC7959 has current-mode logic (CML) outputs. The VSC7961 provides the same functionality as the
VSC7959 with positive emitter-coupled logic (PECL) outputs. The key features of the VSC7959 are Loss-ofSignal (LOS) detect, output offset correction, output squelch, adjustable output levels, low power supply current, and fast rise and fall times.
The inputs of the device provide 100Ω input impedance between IN+ and IN- and are intended to be DCcoupled. The CML output circuits are designed to tolerate output impedance mismatches and may be AC- or
DC-coupled.
Loss of Signal (LOS) Detect
This features utilizes an RMS power detector with programmable LOS indicator to provide two outputs,
LOS and LOS. The input TH is used to set the threshold at which the loss of signal detector outputs, LOS and
LOS, change state. See the Loss of Signal Specifications (Table 3) for setting the resistor value between TH and
ground. The Loss of Signal Truth Table (Table 4) clarifies how LOS and SQUELCH interact.
Optional Squelch
Squelch is disabled when SQUELCH is not connected or is set to TTL low level. When SQUELCH is set to
TTL high level and LOS is asserted, the data outputs, OUT+ and OUT- are forced to static levels. If LOS is not
asserted, the outputs will not be squelched.
Offset Correction
This feature is provided to ensure that the offsets in the limiting amplifier coupled with its gain do not cause
the output buffer to give a false output. Because of the high gain of the amplifier, offset correction using a lowfrequency feedback loop reduces input offset. If no component is placed between pins CZ1 and CZ2, the low
frequency cut-off is 2MHz. If a 0.1µF capacitor is placed between CZ1 and CZ2, the low frequency cut-off is
lowered to about 2kHz. For Fibre Channel and Gigabit Ethernet applications, leave pins CZ1 and CZ2 open. For
ATM/SONET and other scrambled non-return-to-zero (NRZ) applications, place a 0.1µF capacitor between
CZ1 and CZ2. This maintains a one-decade separation between the lowest input frequency and the low frequency cut-off. The low frequency cut-off of the offset correction loop is given by the following equation:
fOC = 43 / [2π * 35k (CZ + 100pF)]
= 196 • 10-6 / (CZ + 100pF)
= 196 • 10-6 / (0.1µF + 100pF)
= 1.96kHz
G52358-0, Rev 2.0
02/09/01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected]
Internet: www.vitesse.com
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VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7959
3.125Gb/s CML Limiting Amplifier with LOS Detect
Output Level Control
The LEVEL pin adjusts the output levels to 20mA when grounded and to 16mA when left unconnected.
Figure 3: Supply Current Measurement
VCC
A
ICC
IOUT
100Ω
100Ω
100Ω
100Ω
IMOD
VSC7959
A
Supply Current (ICC and IEE)
IEE
VEE
Applications Information
Wire Bonding
For best performance, gold ball-bonding techniques are recommended. To minimize inductance, keep wire
bond lengths short.
PCB Layout Guidelines
Use high frequency PCB layout techniques with solid ground planes to minimize crosstalk and EMI. Keep
high speed traces as short as possible for signal integrity. Short input and output traces will provide best performance.
Page 8
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected]
Internet: www.vitesse.com
G52358-0, Rev 2.0
02/09/01
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7959
3.125Gb/s CML Limiting Amplifier with LOS Detect
Package Information
TSSOP-16
1. All dimensioning and tolerancing per ASME. Y14.5-1994
2. Controlling dimension: millimeter
3. This outline conforms to JEDEC Publication 95 Registration MS-026
G52358-0, Rev 2.0
02/09/01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected]
Internet: www.vitesse.com
Page 9
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7959
3.125Gb/s CML Limiting Amplifier with LOS Detect
Ordering Information
The order number for this product is formed by a combination of the device type and package type.
VSC7959 xx
Device Type
3.125Gb/s CML Limiting Amplifier
with LOS Detect
Package
YD: TSSOP-16
W: Dice Waffle Pack
Notice
Vitesse Semiconductor Corporation (“Vitesse”) provides this document for informational purposes only. This document contains pre-production
information about Vitesse products in their concept, development and/or testing phase. All information in this document, including descriptions of
features, functions, performance, technical specifications and availability, is subject to change without notice at any time. Nothing contained in this
document shall be construed as extending any warranty or promise, express or implied, that any Vitesse product will be available as described or
will be suitable for or will accomplish any particular task.
Vitesse products are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent is prohibited.
Page 10
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected]
Internet: www.vitesse.com
G52358-0, Rev 2.0
02/09/01