VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM VIS Description The device is CMOS Dynamic RAM organized as 4,194,304 words x 4 bits. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 5V only or 3.3V only power supply. Low voltage operation is more suitable to be used on battery backup, portable electronic application. A new refresh feature called “ self-refresh “ is supported and very slow CBR cycles are being performed. It is packaged in JEDEC standard 26/24 - pin plastic SOJ or TSOP (II). Features • Single 5V ( ± 10 %) or 3.3V (+10%,-5%) only power supply • High speed tRAC access time : 50/60 ns • Low power dissipation - Active mode : 5V version 605/550 mW (Max.) 3.3V version 396/360 mW (Max.) - Standby mode : 5V version 1.375 mW (Max.) 3.3V version 0.54 mW (Max.) • Fast Page Mode access • I/O level : TTL compatible (Vcc = 5V) LVTTL compatible (Vcc = 3.3V) • 2048 refresh cycles in 32 ms (Std) or 128ms (S - version) • 4 refresh mode : - RAS only refresh - CAS-before-RAS refresh - Hidden refresh - Self - refresh (S - version) Document : Rev. Page 1 VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM VIS Pin configuration 26/24 - PIN 300mil Plastic SOJ 1 26 VSS DQ1 2 25 DQ4 DQ2 3 24 WE 4 23 CAS RAS 5 22 OE NC 6 21 A9 A10 8 19 A8 A0 9 18 A7 A1 10 17 A6 A2 11 16 A5 A3 12 15 A4 VCC 13 14 VSS VG26(V) (S)17400EJ VCC DQ3 Pin Description Pin Name A0 - A10 Function Address inputs - Row address - Column address - Refresh address DQ1 ~ DQ4 Data - in/data - out RAS Row address strobe CAS Column address strobe WE Write enable OE Output enable Vcc Power (+ 5V or + 3.3V) Vss Ground Document : A0 - A10 A0 - A10 A0 - A10 Rev. Page 2 VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM VIS Block Diagram WE CONTROL LOGIC CAS DATA - IN BUFFER DQ1 DQ4 NO. 2 CLOCK GENERATOR DATA - OUT BUFFER COLUMNADDRESS BUFFERS (11) COLUMN DECODER A0 A1 A2 2048 REFRESH CONTROLLER A3 SENSE AMPLIFIERS I/O GATING A4 A5 REFRESH COUNTER 2048 x 4 A6 RAS Document : ROW ADDRESS BUFFERS (11) 2048 A8 A9 A10 ROW DECODER A7 2048 x 2048 x 4 MEMORY ARRAY Vcc NO. 1 CLOCK GENERATOR Vss Rev. Page 3 VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM VIS Truth Table ADDRESSES ROW COL X X X H L ROW COL Data - Out L X ROW COL Data - In L H→L L→H ROW COL Data - Out, Data - In L H→L H L ROW COL Data - Out L H→L H L n/a COL Data - Out PAGE 1st Cycle MODE WRITE 2st Cycle L H→L L X ROW COL Data - In L H→L L X n/a COL Data - In PAGE - MODE 1st Cycle READ - WRITE 2st Cycle L H→L H→L L→H ROW COL Data - Out, Data - In L H→L H→L L→H n/a COL Data - Out, Data - In READ L→H→L L H L ROW COL Data - Out WRITE L→H→L L L X ROW COL Data - In L H X X ROW n/a High - Z H→L L H X X X High - Z FUNCTION RAS CAS WE OE STANDBY H H→X X READ L L WRITE : (EARLY WRITE) L L READ WRITE L 1st Cycle 2st Cycle PAGE MODE READ HIDDEN REFRESH RAS - ONLY REFRESH CBR REFRESH DQS Notes High - Z 1 Notes : 1. EARLY WRITE only. Document : Rev. Page 4 VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM VIS Absolute Maximum Rating Parameter Voltage on any pin relative to Vss Symbol VT Value -1.0 to + 7.0 -0.5 to + 4.6 Unit V Vcc V IOUT -1.0 to + 7.0 -0.5 to + 4.6 50 mA PD 1.0 W Operating temperature TOPT 0 to + 70 °C Storage temperature TSTG -55 to + 125 °C Supply voltage relative to Vss 5V 3.3V 5V 3.3V Short circuit output current Power dissipation Recommended DC Operating Conditions Parameter/Condition Symbol Min 4.5 5 Volt Version Typ Max 5.0 5.5 3.3 Volt Version Min Typ Max 3.15 3.3 3.6 Unit Supply Voltage Vcc V Input High Voltage, all inputs VIH 2.4 - VCC + 1.0 2.0 - VCC + 0.3 V Input Low Voltage, all inputs VIL -1.0 - 0.8 -0.3 - 0.8 V Capacitance Ta = 25°C, VCC = 5V ± 10% or 3.3V(+10%,-5%), f = 1MHz Parameter Symbol Typ Max Unit Note Input capacitance (Address) Cl1 - 5 pF 1 Input capacitance (RAS, CAS, OE, WE) Cl2 - 7 pF 1 Output capacitance CI/O 7 (Data - in, Data - out) Note : 1. Capacitance measured with effective capacitance measuring method. 2. CAS = VIH to disable Dout. pF 1,2 Document : Rev. Page 5 VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM VIS DC Characteristics; 5 - Volt verion (Ta= 0 to 70°C, VCC = + 5V±10%, Vss = 0V) VG26 (V) (S) 17400E Parameter Operating current Symbol ICC1 Low power S - version Test Conditions RAS cycling CAS cycling tRC = min. -5 Min -6 Max Min Max - 145 - TTL interface RAS, CAS = VIH Dout = high - Z - 2 - CMOS interface - RAS, CAS Unit Notes 135 mA 1, 2 2 mA 0.25 - 0.25 ≥ V CC - 0.2V mA Dout = high - Z Standby Standard Current power version ICC2 TTL interface RAS, CAS = VIH Dout = high - Z - CMOS interface - RAS, CAS 2 - 2 mA 1 - 1 ≥ V CC - 0.2V mA Dout = high - Z RAS - only refresh current ICC3 Fast page mode current ICC4 CAS - before - RAS refresh current ICC5 Self - refresh currant (S - Version) CAS - before - RAS long refresh current (S - Version) RAS cycling, CAS = VIH tRC = min. - 145 - 135 1, 2 mA - 100 - 90 tPC = min. 1,3 mA tRC = min. RAS, CAS cycling - 145 - 135 1, 2 ICC8 tRASS ≥ 100µS - 350 - 350 µA ICC9 Standby : VCC - 0.2V ≤ RAS CAS before RAS refresh : 2048 cycles/128ms RAS, RAS : 0V ≤ V IL ≤ 0.2V - 500 - 500 µA mA VCC - 0.2V ≤ V IH ≤ V IH (Max) Dout = high - Z, tRAS ≤ 300ns Document : Rev. Page 6 VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM VIS DC Characteristics ; 5 - Volt Version (cont.) (Ta = 0 to 70°C, VCC = + 5V ± 10%, Vss = 0V) Parameter lnput leakage current Output leakage current Symbol Test Conditions VG26 (V) (S) 17400E -5 -6 Min Max Min Max Unit Notes ILI 0V ≤ Vin ≤ V CC + 0.5V -5 5 -5 5 µA ILO 0V ≤ Vout ≤ VC C + 0.5V Dout = Disable -5 5 -5 5 µA Output high VOH lOH = -5mA 2.4 - 2.4 - V voltage Output low VOL lOL = + 4.2mA 0.4 0.4 V voltage Notes : 1. lCC is specified as an average current. It depends on output loading condition and cycle rate when the device is selected. lCC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. For lCC4, address can be changed once or less within one Fast page mode cycle time. Document : Rev. Page 7 VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM VIS DC Characteristics ; 3.3 - Volt Verion (Ta = 0 to 70°C, VCC = + 3.3V(+10%,-5%), Vss = 0V) VG26 (V) (S) 17400E Parameter Symbol Test Conditions -5 Min Operating current ICC1 Low power S - version RAS cycling CAS cycling tRC = min. Unit Notes -6 Max Min Max - 145 - 135 mA LVTTL interface RAS, CAS = VIH Dout = high - Z - 0.5 - 0.5 CMOS interface - mA 0.15 - 0.15 RAS, CAS ≥ VCC - 0.2V Dout = high - Z Standby Standard Current power version ICC2 mA LVTTL interface RAS, CAS = VIH Dout = high - Z - CMOS interface - 2 - 2 mA 0.5 - 0.5 RAS, CAS ≥ VCC - 0.2V Dout = high - Z RAS - only refresh current ICC3 Fast page mode current ICC4 CAS - before - RAS refresh current ICC5 Self - refresh currant (S - Version) CAS - before - RAS long refresh current (S - Version) 1, 2 RAS cycling, CAS = VIH tRC = min. mA - 145 - 135 1, 2 mA - 100 - 90 tPC = min. 1,3 mA tRC = min. RAS, CAS cycling - 145 - 135 1, 2 ICC8 t RASS ≥ 100µS - 250 - 250 µA ICC9 Standby : VCC - 0.2V ≤ RAS CAS before RAS refresh : 2048 cycles/128ms RAS, RAS : 0V ≤ V I L ≤ 0.2V VCC - 0.2V ≤ V IH ≤ V IH (Max) - 300 - 300 µA mA Dout = high - Z, t RAS ≤ 300ns Document : Rev. Page 8 VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM VIS DC Characteristics ; 3.3 - Volt Version (cont.) (Ta = 0 to 70°C, VCC = + 3.3V(+10%,-5%), VSS= 0V) Parameter Input leakage current Output leakage current Symbol Test Conditions ILI 0V ≤ Vin ≤ V CC + 0.3V ILO 0V ≤ Vout ≤ VC C + 0.3V Dout = Disable lOH = -2mA VG26 (V) (S) 17400E Unit Notes -5 -6 Min Max Min Max -5 5 -5 5 µA -5 5 -5 5 µA Output high VOH 2.4 - 2.4 - V voltage Output low VOL lOL = + 2mA 0.4 0.4 V voltage Notes : 1. lCC is specified as an average current. It depends on output loading condition and cycle rate when the device is selected. lCC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. For lCC4, address can be changed once or less within one Fast page mode cycle time. Document : Rev. Page 9 VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM VIS AC Characteristics (Ta = 0 to + 70°C, VCC = 5V ± 10% or 3.3V ± 10%, V SS = 0V) * 1, * 2, * 3, * 4 Test conditions • Output load : two TTL Loads and 50pF(VCC = 5.0V ± 10%) one TTL Load and 30pF(V CC = 3.3V(+10%,-5%) • Input timing reference levels : VIH = 2.4V, VlL = 0.8V (VCC = 5.0V ± 10%); V IH = 2.0V, VlL = 0.8V (VCC=3.3V(+10%,-5%)) • Output timing reference levels : VOH = 2.0V, VOL = 0.8V (VCC = 5V ± 10%, 3.3V(+10%,-5%)) Read, Write, Read - Modify - Write and Refresh Cycles (Common Parameters) VG26 (V) (S) 17400E -5 Parameter Symbol Min -6 Max Min Unit Max Notes Random read or write cycle time tRC 84 - 104 - ns RAS precharge time tRP 30 - 40 - ns CAS precharge time in normal mode tCPN 10 - 10 - ns RAS pulse width tRAS 50 10000 60 10000 ns 5 CAS pulse width tCAS 8 10000 10 10000 ns 6 Row address setup time tASR 0 - 0 - ns Row address hold time tRAH 8 - 10 - ns Column address setup time tASC 0 - 0 - ns Column address hold time tCAH 8 - 10 - ns RAS to CAS delay time tRCD 12 37 14 45 ns 8 RAS to column address delay time tRAD 10 25 12 30 ns 9 Column address to RAS lead time tRAL 25 - 30 - ns RAS hold time tRSH 8 - 10 - ns CAS hold time tCSH 38 - 60 - ns CAS to RAS precharge time tCRP 5 - 5 - ns OE to Din delay time tOED 12 - 15 - ns tT 1 50 1 50 ns Refresh period tREF - 32 - 32 ms Refresh period (S - Version) tREF - 128 - 128 ms CAS to output in Low-Z tCLZ 0 - 0 - ns CAS delay time from Din tDZC 0 - 0 - ns OE delay time from Din tDZO 0 - 0 - ns Transition time (rise and fall) Document : Rev. 7 10 11 Page 10 VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM VIS Read Cycle VG26 (V) (S) 17400E -5 Parameter Symbol Min -6 Max Min Max Unit Notes Access time from RAS tRAC - 50 - 60 ns 12 Access time from CAS tCAC - 13 - 15 ns 13,14 tAA - 25 - 30 ns 14,15 Access time from OE tOEA - 12 - 15 ns Read command setup time tRCS 0 - 0 - ns 7 Read command hold time to CAS tRCH 0 - 0 - ns 10,16 Read command hold time to RAS tRRH 10 - 10 - ns 16 Output buffer turn-off time tOFF 0 12 0 15 ns 17 Output buffer turn-off time from OE Write Cycle tOEZ 0 12 0 15 ns 17 Unit Notes 7,18 Access time from column address VG26 (V) (S) 17400E -5 Parameter Symbol Min -6 Max Min Max Write command setup time tWCS 0 - 0 - ns Write command hold time tWCH 8 - 10 - ns Write command pulse width tWP 8 - 10 - ns Write command to RAS lead time tRWL 13 - 15 - ns Write command to CAS lead time tCWL 8 - 10 - ns Data-in setup time tDS 0 - 0 - ns 19 Data-in hold time tDH 8 - 10 - ns 19 Unit Notes Read - Modigy - Write Cycle VG26 (V) (S) 17400E -5 Parameter Symbol Min -6 Max Min Max Read - modify - write cycle time tRWC 108 - 133 - ns RAS to WE delay time tRWD 64 - 77 - ns 18 CAS to WE delay time tCWD 26 - 32 - ns 18 Column address to WE delay time tAWD 39 - 47 - ns 18 OE hold time from WE tOEH 8 - 10 - ns Document : Rev. Page 11 VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM VIS Refresh Cycle VG26 (V) (S) 17400E -5 Parameter Min Symbol -6 Max Min Unit Max Notes CAS setup time (CBR refresh) tCSR 5 - 10 - ns CAS hold time (CBR refresh) tCHR 8 - 10 - ns 10 RAS precharge to CAS hold time tRPC 5 - 5 - ns 7 RAS pulse width (self refresh) tRASS 100 - 100 - µs RAS precharge time (self refresh) tRPS 90 - 110 - ns CAS hold time (CBR self refresh) tCHS -50 - -50 - ns WE setup time tWSR 0 - 0 - ns WE hold time Fast Page Mode Cycle tWHR 10 - 10 - ns VG26 (V) (S) 17400E -5 Parameter -6 Min Symbol Max Min Unit Max Notes Fast page mode cycle time tPC 20 - 25 - ns Fast page mode CAS Precharge time tCP 10 - 10 - ns Fast page mode RAS pulse width tRASP 50 105 60 105 ns 20 Access time from CAS precharge tCPA - 30 - 35 ns 10,14 30 - 35 - ns RAS hold time from CAS precharge tCPRH Fast Page Mode Read Modify Write Cycle VG26 (V) (S) 17400E -5 Parameter Symbol Min -6 Max Min Max Unit Notes 11 Fast page mode read - modify - write cycle CAS precharge to WE delay time tCPW 45 - 55 - ns Fast page mode read - modify - write cycle time tPRWC 56 - 68 - ns Document : Rev. Page 12 VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM VIS Notes : 1. AC measurements assume tT = 5ns. 2. An initial pause of 100 µs is required after power up, and it followed by a minimum of eight initialization cycles (RAS-only refresh cycle or CAS-before-RAS refresh cycle). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 4. All the V CC and V SS pins shall be supplied with the same voltage. 5. tRAS(min) = t RWD(min) + tRWL (min) + tT in read - modify-write cycle. 6. tCAS(min) = t CWD(min) + tCWL (min) + tT in read - modify-write cycle. 7. tASC(min), tRCS(min), tWCS(min) and tRPC are determined by the falling edge of CAS. 8. t RCD(max) is specified as a reference point only, and tRAC (max) can be met with the tRCD(max) limit. Otherwise, tRAC is controlled exclusively by tCAC if tRCD is greater than the specified t RCD(max) limit. 9. t RAD(max) is specified as a reference point only, and tRAC(max) can be met with the tRAD(max) limit. Otherwise, tRAC is controlled exclusively by tAA if tRAD is greater than the specified tRAD(max) limit. 10. tCRP, tCHR , tRCH, tCPA and tCPW are determined by the rising edge of CAS. 11. V IH(min) and V IL(max) are reference levels for measuring timing or input signals. Therefore, transition time is measured between VIH and VIL. 12. Assumes that t RCD ≤ tRCD(max) and tRAD ≤ tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 13. Assumes that tRCD ≥ tRCD(max) and tRAD ≤ tRAD(max). 14. Access time is determined by the maximum among tAA, tCAC, tCPA. 15. Assumes that tRCD ≤ tRCD(max) and tRAD ≥ tRAD(max). 16. Either t RCH or tRRH must be satisfied for a read cycle. 17. tOFF(max) and tOEZ(max) define the time at which the output achieves the open circuit condition ( high impedance). 18. tWCS, tRWD , tCWD, and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (min), the cycle is an early write cycle and the data output will remain open circuit (high impedance) throughout the entire cycle. If t RWD ≥ tRWD(min), tCWD ≥ tCWD(min), t AWD ≥ tAWD(min), and tCPW ≥ tCPW(min), the cycle is a read-modify-write and the data output will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of the data output (at access time) is indeterminate. 19. These parameters are referenced to CAS in an early write cycle and to WE edge in a delayed write or a read-modify-write cycle. 20. tRASP defines RAS pulse width in Fast page mode cycles. Document : Rev. Page 13 VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM VIS Timing Waveforms • Read Cycle t RC t t RP RAS RAS t CRP t CSH t RCD t RSH t T t CPN t CAS CAS t RAL t RAD t ASR ADDRESS t ASC t RAH t CAH Column Row t RRH t RCS t RCH WE OE t OEA t CAC t OEZ t OFF t AA t RAC DQ1 ~ DQ4 Note : t CLZ DOUT = don’t care = Invalid Dout Document : Rev. Page 14 VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM VIS •Early Write Cycle t RC t RAS t RP RAS t CRP t CSH t RCD t RSH t CPN t T t CAS CAS t RAD t ASR ADDRESS t RAH t RAL t ASC Row t CAH Column t RAL t WCS t WCH WE t DS DQ1 ~ DQ4 Document : t DH DIN Rev. Page 15 VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM VIS • Delayed Write Cycle t RC t t RP RAS RAS t CSH t CRP t RCD t RSH t T t CPN t CAS CAS t ASR ADDRESS Row t RAH t CAH t ASC Column t CWL t RCS t RWL t WP WE t OED OE t OEH t DS t DS DQ1 ~ DQ4 Document : OPEN t DH DIN Rev. Page 16 VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM VIS • Read - Modify - Write Cycle t RWC t t RP RAS RAS t T t RCD t CAS t CRP t CPN CAS t RAD t ASR ADDRESS t ASC t RAH Row t CAH Column t RCS t CWL t RWL t CWD t AWD t RWD t WP WE t DH t DZC t DS OPEN DQ1 ~ DQ4 DIN t OED t DZO t OEH OE t RAC t OEA t CAC t AA t OEZ DOUT DQ1 ~ DQ4 Document : Rev. Page 17 VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM VIS • Fast Page Mode Read Cycle t RP t RASP t CPRH RAS t CRP t PC t CSH t CRP t RCD t CAS t CAS t CP t RSH t CAS t CP t CPN CAS t RAD t ASR ADDRESS t RAL t ASC t RAH Row t CAH t ASC t ASC t CAH Column N Column 2 Column 1 t CAH Row t RRH t RCH t RCS WE WE t OEA OE t OEA t OEA OE t RAC t CPA t CPA t AA t OEZ t AA t OEZ t AA t OEZ t CAC t OFF t OFF t CLZ t CLZ t CLZ DQ1 ~ DQ4 t CAC t CAC t OFF DOUT N DOUT 1 DOUT 2 Document : Rev. Page 18 OPEN VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM VIS • Fast Page Mode Early Write Cycle t t RP RASP RAS tT t CSH t CAS t RCD t CRP t RSH t PC t CAS t CP t CAS t CP t CPN CAS t ASR ADDRESS Row t RAH t ASC Document : t WCH t ASC t CAH Column N t WCS t WCH t WCS t WCH t DS t DH t DS t DH WE t DS DQ1 ~ DQ4 t CAH Column 2 Column 1 t WCS WE t ASC t CAH t DH DIN 2 DIN 1 Rev. DIN N Page 19 VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM VIS • Fast Page Mode Delayed Write Cycle t RASP tCPRH t RP RAS t T t CP t CSH t RCD t CP t CRP t PC t CAS t RSH t CAS t CAS CAS t RAD t ASR t ASC t RAH ADDRESS t CAH t CAH t CAH Column 1 Column 1 Row t ASC t ASC Column 2 Column N t CWL t CWL t CWL t RWL t RCS t RCS WE t RCS WE t WP t WP t DS t DZC OPEN DQ1 ~ DQ4 t DZC t DH t DS t DZC t DS t DH OPEN DIN 1 t DZO t WP DIN N t DZO t OED t OEH OPEN DIN 2 t DZO t OED t DH t OEH t OED t OEH OE Document : Rev. Page 20 VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM VIS • Fast Page Mode Read - Modify - Write Cycle t RASP tCPRH t RP RAS t T t RCD t PRWC t CP t CAS t CRP t CP t CAS t CAS CAS t RAD t ASR t ASC t RAH ADDRESS t CAH Column 2 t CWL t RWD t AWD t CWD WE t CAH t CAH Column 1 Column 1 Row t ASC t ASC Column N t RCS t CWL t CPW t AWD t CWD t CWL t CPW t AWD t CWD t RCS t RWL WE t RCS t WP t DZC t WP t DS t WP t DS t DZC t DH OPEN DQ1 ~ DQ4 t DH OPEN DIN 1 t DZO t OEA t CPA t OEH t DH DIN N DIN 2 t DZO t OED t DZO t OED t DS t DZC t OEA t OED t CPA t OEH t OEH t OEA OE t CAC t AA t CAC t AA t OEA t CAC t AA t RAC t CLZ t OEZ t OEZ t CLZ t OEZ t CLZ DQ1 ~ DQ4 DOUT 1 Document : DOUT 2 Rev. DOUT N Page 21 VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM VIS RAS - Only Refresh Cycle t RC t RP t RAS RAS tT tCRP tRPC t CRP CAS tASR ADDRESS tRAH Row tOFF OPEN DQ1 ~ DQ4 CAS - Before - RAS Refresh Cycle tRC tRP RAS tRC tRAS tT t RAS tRP tRPC tRPC t RP tCRP t CSR t CHR tCSR t CHR tWSR tWHR tWSR tWHR CAS WE tOFF OPEN DQ1 ~ DQ4 Document : Rev. Page 22 VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM VIS CBR Self - Refesh Cycle ( S - Version Only ) t RPS t RASS RAS t RPC tCSR CAS tCHS tOFF High lmpedance DQ1 - DQ4 tWSR WE Document : tWHR OPEN Rev. Page 23 VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM VIS • Hidden Refresh Cycle t RC t RC t RC t RP tRAS (READ) tRAS t RP (REFRESH) tRAS t RP (REFRESH) RAS tT t CHR tCRP t RSH t RCD tCAS CAS t RAD t ASR ADDRESS t RAH t RAL tASC tCAH Column Row tRRH t RCS tRCH WE OE t OEZ t OEA t CAC t OFF t AA t RAC D OUT DQ1 ~ DQ4 Document : Rev. Page 24 VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM VIS Ordering information Part Number Access Time Package VG26 (V) (S) 17400FJ - 5 50 ns 300mil 26/24 - Pin VG26 (V) (S) 17400FJ - 6 60 ns Plastic SOJ VG26 (V) (S) 17400FJ - 5 • VG • VIS Memory Product • 26 • Technology •V • 3.3V version •S • Self refresh • 17400 • Device Type and Configuration •F • Revision •J • Package Type (J : SOJ , T : TSOJ II) •5 • Speed (5 : 50 ns, 6 : 60 ns) Packaging information • 300 mil, 26/24-Pin Plastic SOJ D A A1 A2 INCHES MILLIMETERS NOM. MAX. MIN. NOM. MAX. MIN. 3.25 3.51 3.76 0.128 0.138 0.148 ----2.08 ----0.082 2.54 REF. 0.100 REF. b 0.41 --- 0.51 0.016 b1 b2 0.41 0.66 0.46 --- 0.48 0.81 0.016 0.026 c c1 D E E1 E2 e R1 0.18 0.18 17.02 --0.30 --0.28 17.15 17.27 8.51 BASIC 7.49 7.62 7.75 6.78 BASIC 1.27 BASIC 0.76 --1.02 0.007 0.007 0.670 DIM --0.018 --- b 26 21 19 14 b1 c1 c E1 0.020 E BASE METAL 0.019 0.032 --0.012 0.011 --0.675 0.680 0.335 BASIC 0.295 0.300 0.305 0.267 BASIC 0.050 BASIC 0.030 --0.040 WITH PLATING 1 6 8 13 SECTION B-B CL 0.025" MIN. A2 B B A A1 NOTE: 1. CONTROLLING DIMENSION : INCHES 2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.006"(0.15mm) PER SIDE. DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION. INTERLEAD PROTRUSION SHALL NOT EXCEED 0.01"(0.25mm) PER SIDE. 3. DIMENSION b2 DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE SHOULDER WIDTH TO EXCEED b2 MAX BY MORE THAN 0.005"(0.127mm) DAMBAR INTRUSION SHALL NOT REDUCE THE SHOULDER WIDTH TO LESS THAN 0.001"(0.025mm) BELOW b2 MIN. Document : RAD R1 e b2 b 4-e 0.004" E2 SEATING PLANE 0.007" M Rev. Page 25