VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM VIS Description The device CMOS Dynamic RAM organized as 1,048,576 words x 16 bits with extended data out access mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 5V only or 3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup, portable electronic application. A new refresh feature called “self-refresh” is supported and very slow CBR cycles are being performed. lt is packaged in JEDEC standard 42-pin plastic SOJ. Features • Single 5V( ± 10 %) or 3.3V( ± 10 %) only power supply • High speed tRAC acess time: 50/60ns • Low power dissipation - Active wode : 5V version 660/605 mW (Mas) 3.3V version 432/396 mW (Mas) - Standby mode: 5V version 1.375 mW (Mas) 3.3V version 0.54 mW (Mas) • Extended - data - out(EDO) page mode access • I/O level: TTL compatible (Vcc = 5V) LVTTL compatible (Vcc = 3.3V) • 1024 refresh cycle in 16 ms(Std.) or 128 ms(S-version) • 4 refresh modes: - RAS only refresh - CAS - before - RAS refresh - Hidden refresh - Self-refresh(S-version) Document:1G5-0147 Rev.1 Page 1 VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM VIS Pin Configuration 42-Pin 400mil Plastic SOJ VCC 1 DQ1 DQ2 DQ3 DQ4 VCC 2 3 4 5 VSS DQ16 40 DQ15 39 38 DQ14 DQ13 6 37 DQ5 DQ6 7 8 36 VSS DQ12 DQ7 9 DQ8 NC NC WE 10 35 34 33 DQ11 DQ10 DQ9 32 30 NC LCAS UCAS RAS 14 15 29 28 OE A9 27 26 25 A8 A6 24 23 A5 A4 22 VSS NC NC 11 12 13 A0 A1 16 17 18 A2 19 A3 20 21 VCC VG26(V)(S)18165CJ 42 41 31 A7 Pin Description Pin Name A0-A9 Function Address inputs - Row address - Column address - Refresh address DQ1~DQ16 Data-in / data-out RAS Row address strobe UCAS, LCAS Column address strobe WE Write enable OE Output enable Vcc Power (+5 V or + 3.3V) Vss Ground Document:1G5-0147 A0-A9 A0-A9 A0-A9 Rev.1 Page 2 VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM VIS Block Diagram WE LCAS CAS UCAS CONTROL LOGIC DATA - IN BUFFER DQ1 . . DQ16 NO.2 CLOCK GENERATOR DATA - OUT BUFFER OE COLUMNADDRESS BUFFERS (10) COLUMN DECODER A0 A1 A2 1024 REFRESH CONTROLLER A3 SENSE AMPLIFIERS I/0 GATING A4 A5 REFRESH COUNTER 1024x16 A6 RAS ROW ADDRESS BUFFERS (10) 1024 A8 A9 ROW DECODER A7 1024 x 1024 x 16 MEMORY ARRAY Vcc NO.1 CLOCK GENERATOR Document:1G5-0147 Vss Rev.1 Page 3 VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM VIS TRUTH TABLE ADDRESSES FUNCTION RAS LCAS UCAS WE OE ROW COL STANDBY H H→X H→X X X X X READ : WORD L L L H L ROW COL Data-Out READ : LOWER BYTE L L H H L ROW COL Lower Byte: Data-Out Upper Byte: High-Z READ: UPPER BYTE L H L H L ROW COL Lower Byte: High-Z Upper Byte: Data-Out WRITE: WORD (EARLY WRITE) L L L L X ROW COL Data-In WRITE: LOWER BYTE (EARLY) L L H L X ROW COL Lower Byte: Data-In Upper Byte: High-Z WRITE : UPPER BYTE (EARLY) L H L L X ROW COL Lower Byte: High-Z Upper Byte: Data-In READ WRITE L L L H→L L→H ROW COL Data-Out, Data-In 1st Cycle L H→L H→L H L ROW COL Data-Out 2 2nd Cycle L H→L H→L H L n/a COL Data-Out 2 1st Cycle L H→L H→L L X ROW COL Data-In 1 2nd Cycle L H→L H→L L X n/a COL Data-In 1 1st Cycle L H→L H→L H→L L→H ROW COL Data-Out, Data-In 1,2 2nd Cycle L H→L H→L H→L L→H n/a COL Data-Out, Data-In 1,2 READ L→H→L L L H L ROW COL Data-Out WRITE L→H→L L L L X ROW COL Data-In L H H X X ROW n/a High-Z H→L L L H X X X High-Z PAGE-MODE READ PAGE-MODE WRITE PAGE-MODE READWRITE HIDDEN REFRESH RAS-ONLY REFRESH CBR REFRESH DQS Notes High-Z 2 1,3 4 Notes: 1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active). 2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active). 3. EARLY WRITE only. 4. At least one of the two CAS signals must be active (LCAS or UCAS). Document:1G5-0147 Rev.1 1,2 Page 4 VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM VIS Absolute Maximum Ratings Parameter Symbol 5V Voltage on any pin relative to Vss Value Unit -1.0 to + 7.0 V VT 3.3V -0.5 to + 4.6 -1.0 to + 7.0 5V Supply voltage relative to Vss V VCC 3.3V -0.5 to + 4.6 Short circuit output current IOUT 50 mA PD 1.0 W Operating temperature TOPT 0 to + 70 ¢J Storage temperature TSTG -55 to + 125 ¢J Power dissipation Recommended DC Operating Conditions Parameter/Condition Symbol 5 Volt Version Min Typ Supply Voltage VCC 4.5 Input High Voltage, all inputs VIH 2.4 Input Low Voltage, all inputs VIL -1.0 3.3 Volt Version Max 5.0 Min 5.5 3.0 - VCC + 1.0 2.0 - 0.8 Typ Max 3.3 -0.3 Unit 3.6 V - VCC + 0.3 V - V 0.8 Capacitance Ta = 25°C, VCC = 5V ± 10 % or 3.3V ± 10 %, f = 1MHz Parameter Symbol Typ Max Unit Note Input capacitance (Address) CI1 - 5 pF 1 Input capacitance (RAS , LCAS , UCAS, OE, WE) CI2 - 7 pF 1 Output capacitance (Data-in, Data-out) CI/O - 7 pF 1, 2 Note: 1. Capacitance measured with effective capacitance measuring method. 2. RAS, LCAS and UCAS = VIH to disable Dout. Document:1G5-0147 Rev.1 Page 5 VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM VIS DC Characteristics; 5- Volt Verion (Ta = 0 to + 70 °C, VCC= + 5V ± 10 %,VSS = 0V) Parameter Symbol Test Conditions VG26(V)(S)18165C -5 Operating current ICC1 Low power S-version Standby Current ICC2 Standard power version Unit Notes 1, 2 -6 Min Max Min Max RAS cycling LCAS / UCAS cycling tRC = min - 120 - 110 mA TTL interface RAS, LCAS / UCAS = VIH Dout = High-Z - 2 - 2 mA CMOS interface - 0.25 - 0.25 mA TTL interface RAS,LCAS / UCAS = VIH Dout = High-Z 2 - 2 mA CMOS interface 1 - 1 mA RAS, CAS ≥ Vcc -0.2V Dout = High-Z RAS, CAS ≥ Vcc -0.2V Dout = High-Z RAS-only refresh current ICC3 RAS cycling, LCAS / UCAS = VIH tRC = min - 120 - 110 mA 1, 2 EDO page mode current ICC4 tRC = min - 90 - 80 mA 1, 3 CAS-before-RAS refresh current ICC5 tRC = min RAS, LCAS / UCAS cycling - 120 - 110 mA 1, 2 Self-refresh current (S - Version) ICC8 tRAS ≥ 100µs - 350 - 350 µA CAS- before- RAS long refresh current (S-Version) ICC9 Standby: VCC- 0.2V ≤ RAS CAS before RAS refresh: 2048 cycles / 128ms RAS,LCAS / UCAS: 0V ≤ V IL ≤ 0.2V - 500 - 500 µA VCC- 0.2V ≤ V IH ≤ V IH (Max) Dout = High-Z, t RAS ≤ 300ns Document:1G5-0147 Rev.1 Page 6 VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM VIS DC Characteristics ; 5-Volt Version (Cont.) (Ta = 0 to + 70°C, VCC = + 5V ± 10 %,VSS = 0V) VG26(V)(S)18165C -5 Parameter Symbol Test Conditions Min -6 Max Min Max Unit Input leakage current ILI 0V ≤ V I N ≤ V C C + 0.5V -5 5 -5 5 µA Output leakage current ILO 0V ≤ V OUT ≤ V CC + 0.5V -5 5 -5 5 µA 2.4 - 2.4 - V - 0.4 - 0.4 V Dout = Disable Output high Voltage VOH IOH = - 5mA Output low voltage VOL IOL = + 4.2mA Notes: 1. ICC is specified as an average current. It depends on output loading condition and cycle rate when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. For ICC4, address can be changed once or less within one EDO page mode cycle time. Document:1G5-0147 Rev.1 Page 7 Notes VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM VIS DC Characteristics ; 3.3 - Volt Version (Ta = 0 to 70°C , VCC = + 3.3V ± 10 %, VSS = 0V) Parameter Symbol Test Conditions VG26(V)(S)18165C -5 Operating current Low power S-version Unit Notes 1, 2 -6 Min Max Min Max ICC1 RAS cycling LCAS / UCAS cycling tRC = min - 120 - 110 mA ICC2 LVTTL interface RAS, LCAS / UCAS = VIH Dout = High-Z - 0.5 - 0.5 mA CMOS interface - 0.15 - 0.15 mA LVTTL interface RAS, LCAS / UCAS = VIH Dout = High-Z - 2 - 2 mA CMOS interface - 0.5 - 0.5 mA RAS, CAS ≥ V C C -0.2V Dout = High-Z Standby Current Standard power version RAS, CAS ≥ V C C -0.2V Dout = High-Z RAS- only refresh current ICC3 RAS cycling LCAS / UCAS = VIH tRC = min - 120 - 110 mA 1, 2 EDO page mode current ICC4 tPC = min - 90 - 80 mA 1, 3 CAS- before- RAS refresh current ICC5 tRC = min RAS, LCAS / UCAS cycling - 120 - 110 mA 1, 2 Self- refresh current (S-Version) ICC8 t RASS ≥ 100µs - 250 - 250 µA CAS- before- RAS long refresh current (S-Version) ICC9 Standby: VCC- 0.2V ≤ RAS CAS before RAS refresh: 2048 cycles / 128ms RAS, LCAS / UCAS : 0V ≤ V IL ≤ 0.2V - 300 - 300 µA VCC- 0.2V ≤ V IH ≤ V IH (max) Dout = High-Z, tRAS ≤ 300ns Document:1G5-0147 Rev.1 Page 8 VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM VIS DC Characteristics ; 3.3 - Volt Version (Cont.) (Ta = 0 to 70°C, VCC= +3.3V ± 10 %, VSS= 0V) VG26(V)(S)18165C -5 Parameter Symbol Input leakage current ILI Output leakage current ILO Test Conditions Min Unit -6 Max Min Max 0V ≤ Vin ≤ V C C + 0.3V -5 5 -5 5 µA 0V ≤ Vout ≤ V CC + 0.3V -5 5 -5 5 µA Dout = Disable Output high Voltage VOH IOH = -2mA 2.4 - 2.4 - V Output low voltage VOL IOL = +2mA - 0.4 - 0.4 V Notes: 1. ICC is specified as an average current. It depends on output loading condition and cycle rate when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. For I CC4, address can be changed once or less within one EDO page mode cycle time. Document:1G5-0147 Rev.1 Page 9 Notes VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM VIS AC Characteristics (Ta = 0 to + 70°C, Vcc = 5V ± 10 % or 3.3V ± 10 %, Vss = 0V) *1, *2, *3, *4, *5 Test conditions • Output load: two TTL Loads and 50pF (VCC = 5.0V ± 10 %) one TTL Load and 50pF (VCC = 3.3V ± 10 %) • Input timing reference levels: VIH = 2.4V, VIL = 0.8V (VCC = 5.0V ± 10 %); VIH = 2.0V, VIL = 0.8V (VCC = 3.3V ± 10 %) • Output timing reference levels: VOH = 2.0V, VOL = 0.8V (VCC = 5V ± 10 %, 3.3V ± 10 %) Read, Write, Read- Modify- Write and Refresh Cycles (Common Parameters) VG26(V)(S) 18165C -5 Parameter Symbol Min Unit Notes -6 Max Min Max Random read or write cycle time tRC 84 - 104 - ns RAS precharge time tRP 30 - 40 - ns tCPN 10 - 10 - ns RAS pulse width tRAS 50 10000 60 10000 ns 6 LCAS / UCAS pulse width tCAS 8 10000 10 10000 ns 7 Row address setup time tASR 0 - 0 - ns Row address hold time tRAH 8 - 10 - ns Column address setup time tASC 0 - 0 - ns Column address hold time tCAH 8 - 10 - ns RAS to LCAS / UCAS delay time tRCD 12 37 14 45 ns 9 RAS to column address delay time tRAD 10 25 12 30 ns 10 Column address to RAS lead time tRAL 25 - 30 - ns RAS hold time tRSH 8 - 10 - ns LCAS / UCAS hold time tCSH 38 - 40 - ns LCAS / UCAS to RAS precharge time tCRP 5 - 5 - ns OE to Din delay time tOED 12 - 15 - ns tT 1 50 1 50 ns Refresh period tREF - 16 - 16 ms Refresh period (S- Version) tREF - 128 - 128 ms LCAS / UCAS to output in Low- Z tCLZ 0 - 0 - ns LCAS / UCAS delay time from Din tDZC 0 - 0 - ns OE delay time from Din tDZO 0 - 0 - ns LCAS / UCAS precharge time in normal mode Transition time (rise and fall) Document:1G5-0147 Rev.1 8 11 12 Page 10 VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM VIS Read Cycle VG26(V)(S)18165C -5 Parameter Min Symbol Unit Notes -6 Max Min Max Access time from RAS tRAC - 50 - 60 ns 13 Access time from LCAS / UCAS tCAC - 13 - 15 ns 14, 15 tAA - 25 - 30 ns 15, 16 Access time from OE tOEA - 12 - 15 ns Read command setup time tRCS 0 - 0 - ns 8 Read command hold time to LCAS / UCAS tRCH 0 - 0 - ns 11, 17 Read command hold time to RAS tRRH 10 - 10 - ns 17 Output buffer turn-off time tOFF 0 12 0 15 ns 18 Output buffer turn-off time from OE tOEZ 0 12 0 15 ns 18 Unit Notes 8, 19 Access time from column address Write Cycle VG26(V)(S)18165C -5 Parameter Symbol Min -6 Max Min Max Write command setup time tWCS 0 - 0 - ns Write command hold time tWCH 8 - 10 - ns Write command pulse width tWP 8 - 10 - ns Write command to RAS lead time tRWL 13 - 15 - ns Write command to LCAS / UCAS lead time tCWL 8 - 10 - ns 20 Data-in setup time tDS 0 - 0 - ns 21 Data-in hold time tDH 8 - 10 - ns 21 tWED 10 - 10 - ns WE to Data-in delay Read- Modify- Write Cycle VG26(V)(S) 18165C -5 Parameter Symbol Min Unit Notes -6 Max Min Max Read-modify- write cycle time tRWC 108 - 133 - ns RAS to WE delay time tRWD 64 - 77 - ns 19 LCAS / UCAS to WE dealy time tCWD 26 - 32 - ns 19 Column address to WE delay time tAWD 39 - 47 - ns 19 OE hold time from WE tOEH 8 - 10 - ns Document:1G5-0147 Rev.1 Page 11 VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM VIS Refresh Cycle VG26(V)(S)18165C -5 Parameter -6 Min Symbol Max Min Max Unit Notes LCAS / UCAS setup time (CBR refresh) tCSR 5 - 5 - ns LCAS / UCAS hold time (CBR refresh) tCHR 8 - 10 - ns 11 RAS precharge to CAS hold time tRPC 5 - 5 - ns 8 RAS pulse width (self refresh) tRASS 100 - 100 - µs RAS precharge time (self refresh) tRPS 90 - 110 - ns LCAS / UCAS hold time (CBR self tCHS -50 - -50 - ns WE setup time tWSR 0 - 0 - ns WE hold time tWHR 10 - 10 - ns refresh) EDO Page Mode Cycle VG26(V)(S)18165C -5 Parameter Symbol -6 Min Max Min Max Unit Notes EDO page mode cycle time tPC 20 - 25 - ns EDO page mode LCAS / UCAS precharge time tCP 10 - 10 - ns EDO page mode RAS pulse width tRASP 50 105 60 105 ns 22 Access time from LCAS / UCAS precharge tCPA - 30 - 35 ns 11, 15 RAS hold time from LCAS / UCAS precharge tCPRH 30 - 35 - ns OE high hold time from LCAS / UCAS high tOEHC 5 - 5 - ns OE high pulse width tOEP 10 - 10 - ns Data output hold time after LCAS / UCAS low tCOH 5 - 5 - ns Output disable delay from WE tWHZ 3 10 3 10 ns WE pulse width for output disable when LCAS / UCAS high tWPZ 7 - 7 - ns Document:1G5-0147 Rev.1 Page 12 VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM VIS EDO Page Mode Read Modify Write Cycle VG26(V)(S)18165C -5 Parameter Symbol Min -6 Max Min Max Unit Notes 11 EDO page mode read- modify- write cycle LCAS / UCAS precharge to WE delay time tCPW 45 - 55 - ns EDO page mode read- modify- write cycle time tPRWC 56 - 68 - ns Document:1G5-0147 Rev.1 Page 13 VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM VIS Notes : 1. AC measurements assume t T = 2ns. 2. An initial pause of 100 µs is required after power up, and it followed by a minimum of eight initialization cycles (RAS - only refresh cycle or CAS - before - RAS refresh cycle). If the internal refresh counter is used, a minimun of eight CAS - before - RAS refresh cycles are required. 3. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 4. All the VCC and VSS pins shall be supplied with the same voltages. 5. When both LCAS and UCAS go low at the same time, all 16-bits data are witten into the device. LCAS and UCAS cannot be staggered within the same write/read cycles. 6. tRAS(min) = tRWD(min)+t RWL(min)+tT in read-modify-write cycle. 7. tCAS (min) = tCWD(min)+tCWL(min)+tT in read-modify-write cycle. 8. tASC(min), tRCS (min), tWCS(min), and tRPC are determined by the falling edge of CAS . 9. t RCD(max) is specified as a reference point only, and tRAC (max) can be met with the tRCD(max) limit. Otherwise, tRAC is controlled exclusively by tCAC if tRCD is greater than the specified tRCD(max) limit. 10. t RAD(max) is specified as a reference point only, and tRAC(max) can be met with the tRAD(max) limit. Otherwise, tRAC is controlled exclusively by tAA if tRAD is greater than the specified tRAD(max) limit. 11. tCRP, tCHR , tRCH, tCPA and tCPW are determined by the rising edge of CAS . 12. V IH(min) and VIL(max) are reference levels for measuring timing or input signals. Therefore, transition time is measured between VIH and VIL. ≤ 13. Assumes that t RCD tRCD(max) and tRAD ≤ tRAD(max). If t RCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 14. Assumes that tRCD ≥ t RCD (max) and tRAD ≤ t RAD (max). 15. Access time is determined by the maximum of tAA , tCAC, tCPA. 16. Assumes that t RCD ≤ tRCD (max) and t RAD ≥ tRAD (max). 17. Either tRCH or tRRH must be satisfied for a read cycle. 18. tOFF(max) and tOEZ(max) define the time at which the output achieves the open circuit condition (high impedance). t OFF is determined by the later rising edge of RAS or CAS. 19. tWCS, tRWD, tCWD, and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ t WCS (min), the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tRWD tCWD ≥ t CWD (min), t AWD ≥ t AWD (min) and tCPW ≥ tRWD (min), ≥ tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of the data output (at access time) is indeterminate. 20. tCWL shall be satisfied by both LCAS and UCAS. 21. These parameters are referenced to LCAS or LCAS separately in an early write cycle and to WE edge in a delayed write or a read-modify-write cycle. 22. tRASP defines RAS pulse width in EDO page mode cycles. Document:1G5-0147 Rev.1 Page 14 VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM VIS Timing Waveforms • Word Read Cycle t RC t RAS t RP RAS t CRP t CSH t RCD t RSH t T t CPN t CAS UCAS LCAS t RAL t RAD t ASR ADDRESS t ASC t RAH t CAH Column Row t RRH t RCH t RCS WE OE t OEA t CAC t OEZ t OFF t AA t RAC DQ1~DQ16 Document:1G5-0147 t CLZ Rev.1 DOUT Page 15 VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM VIS • Byte Read Cycle t RC t t RP RAS RAS t CSH t CRP t RCD t RSH t T t CAS UCAS (or LCAS) LCAS (or UCAS) t RAL t RAD t ASR ADDRESS t ASC t RAH t CAH Column Row tRRH t RCH t RCS WE OE t OEA t CAC t OEZ t OFF t AA t RAC DQ9~DQ16 (or DQ1~DQ8) DQ1~DQ8 (or DQ9~DQ16) Document:1G5-0147 DOUT t CLZ High-Z Rev.1 Page 16 VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM VIS • Word Early Write Cycle t RC t t RP RAS RAS t CSH t CRP t RCD t RSH t T t CAS UCAS LCAS t RAL t RAD t RAH t ASR ADDRESS t ASC Row t CAH Column t WCS t WCH WE t DH t DS DQ1~DQ16 Document:1G5-0147 DIN Rev.1 Page 17 VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM VIS • Byte Early Write Cycle t RC t t RP RAS RAS t CSH t CRP t RCD t RSH t T t CAS LCAS (or UCAS) LCAS (or UCAS) t RAL t RAD t ASR ADDRESS t RAH t ASC Row t CAH Column t WCH t WCS WE t DH t DS DQ9~DQ16 DIN DQ1~DQ8 Document:1G5-0147 Rev.1 Page 18 VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM VIS • Word Delayed Write Cycle t RC t t RP RAS RAS t CSH t CRP t RCD t RSH t T t CPN t CAS UCAS LCAS t ASR ADDRESS t RAH t ASC Row t CAH Column t CWL t RWL t RCS t WP WE t OEH t OED OE t DS DQ1~DQ16 Document:1G5-0147 OPEN t DH DIN Rev.1 Page 19 VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM VIS • Byte Delayed Write Cycle t RC t t RP RAS RAS t CSH t CRP t RCD t RSH t T t CAS LCAS (or UCAS) LCAS (or UCAS) t ASR ADDRESS t RAH t ASC Row t CAH Column tCWL t RCS t RWL t WP WE t OEH tOED OE t DS DQ9~DQ16 (or DQ1~DQ8) OPEN t DH DIN DQ1~DQ8 (or DQ9~DQ16) Document:1G5-0147 Rev.1 Page 20 VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM VIS • Word Read-Modify-Write Cycle t RWC t t RP RAS RAS t T t RCD t CRP t CPN t CAS UCAS LCAS t RAD t ASR ADDRESS t RAH t ASC Row t CAH Column t CWD t RCS t CWL t AWD t RWL t RWD t WP WE t DH t DS OPEN DQ1~DQ16 D in t OED t OEH OE t OEA t CAC t OEZ t AA t RAC DOUT DQ1~DQ16 Document:1G5-0147 Rev.1 Page 21 VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM VIS • EDO Page Mode Word Read-Modify-Write Cycle t RASP tCPRH t RP RAS t T t RCD UCAS LCAS t PRWC t CP t CAS t CAS t RAD t ASR t ASC t RAH ADDRESS Column N Column 2 t CWL t RWD t AWD t CWD WE t CAH t CAH Column 1 Column 1 Row t CWL t CPW t AWD t CWD t RCS t CAS t RAL t ASC t ASC t CAH t CRP t CP t t CWL CPW t AWD t CWD t RWL WE t RCS tWP t WP tDS tWP tDS t DS t DH OPEN DQ1~DQ16 Din 1 t DH OPEN Din 2 t DH OPEN Din N t DZO t OED t OED t OEH t OEH t OED t OEH OE t OEA t OEA t CAC t CAC t RAC t AA t CPA t AA t CPA t AA tOEZ t OEA t CAC t OEZ t OEZ DQ1~DQ16 DOUT 2 DOUT 1 Document:1G5-0147 Rev.1 DOUT N Page 22 VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM VIS • EDO Page Mode Word Read-Early-Write Cycle t t RP RASP t CPRH RAS t CRP t PC t CSH t RCD t CRP t CAS t RSH t CAS t CP t CAS t CP t CPN UCAS LCAS t CAL t CSH t RAD t ASR ADDRESS t RAL t ASC t RAH Row t CAH t ASC Column 1 t CAH Column N Column 2 t RCH t RCS WE t ASC t CAH Row t WCS t WCH WE tOEA t WED OE OE tRAC t AA t CPA tAA tWHZ tCAC tCAC t DH tDS tCOH DQ1~DQ16 OPEN Data Output 1 Data Output 2 Data Intput N Document:1G5-0147 Rev.1 Page 23 VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM VIS • Read Cycle with WE Controlled Disable RAS t CSH t RCD t T t CAS UCAS LCAS t RAD t ASR ADDRESS t CAH t ASC t RAH Row Column t RCH t RCS t WPZ WE t WHZ t OED t DS OE tOEA tCAC tOEZ tAA tRAC DQ1~DQ16 DOUT tCLZ Document:1G5-0147 Rev.1 Page 24 VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM VIS RAS - Only Refresh Cycle t RC tRP t RAS RAS tT tCRP tRPC t CRP UCAS LCAS tASR ADDRESS tRAH Row tOFF OPEN DQ1~DQ16 CAS-Before-RAS Refresh Cycle tRC tRP tRC tRAS RAS tT t RAS tRP tRPC tRPC t RP tCRP t CSR t CHR tCSR tWSR tWHR tWSR tCHR tWHR UCAS LCAS WE tOFF OPEN DQ1~DQ16 Document:1G5-0147 Rev.1 Page 25 VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM VIS • Hidden Refresh Cycle tRC tRC tRC tRP tRAS (READ) tRAS tRP (REFRESH) tRAS tRP (REFRESH) RAS tT t CHR tCRP t RSH tRCD tCAS UCAS LCAS t RAD t ASR ADDRESS t RAH t RAL tASC tCAH Column Row tRRH t RCS tRCH WE tORD OE t OEZ t OEA t CAC t OFF t AA t OFF t RAC D OUT DQ1~DQ16 Document:1G5-0147 Rev.1 Page 26 VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM VIS Ordering information Part Number Access time Package VG26(V)(S)18165CJ-5 50 ns 400mil 42-Pin VG26(V)(S)18165CJ-6 60 ns Plastic SOJ VG26(V)(S)18165CJ-5 • VG • VIS Memory Product • 26 • Technology •V • 3.3V Version •S • Self refresh • 18165 • Device Type and Configuation •C • Revision •J • Package Type (J : SOJ, T : TSOP II) •5 • Speed (5 : 50 ns, 6 : 60 ns) Document:1G5-0147 Rev.1 Page 27