VML VG36643241BT-10

VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Description
The device is CMOS Synchronous Dynamic RAM organized as 524,288 - word x 32 - bit x 4 bank, and 1,048,576 - word x 32 - bit x 2 - bank, respectively. lt is fabricated with an advanced
submicron CMOS technology and designed to operate from a singly 3.3V only power supply. It is
packaged in JEDEC standard pinout and standard plastic TSOP package.
Features
• Single 3.3V ( ± 0.3V ) power supply
• High speed clock cycle time : 8/10 for LVTTL
• High speed clock cycle time : 8/10 for SSTL - 3
• Fully synchronous with all signals referenced to a positive clock edge
• Programmable CAS Iatency (2,3)
• Programmable burst length (1,2,4,8,& Full page)
• Programmable wrap sequence (Sequential/Interleave)
• Automatic precharge and controlled precharge
• Auto refresh and self refresh modes
• Dual Internal banks controlled by A11 (Bank select) for VG36643211(2)
• Quad Internal banks controlled by A11 & A12 (Bank select) for VG36643241(2)
• Each Banks can operate simultaneously and independently
• LVTTL compatible I/O interface for VG36643211 and VG36643241
• SSTL - 3 compatible I/O interface for VG36643212 and VG36643242
• Random column access in every cycle
• x32 organization
• Input/Output controlled by DQM0 ~ 3
• 4,096 refresh cycles/64ms
• Burst termination by burst stop and precharge command
• Burst read/single write option
Document : 1G5-0099
Rev.1
Page 1
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Pin Configuration
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDD
DQM0
WE
CAS
RAS
CS
NC
A11/BA
NC
A10/AP
A0
A1
A2
DQM2
VDD
NC
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSS
DQM1
NC (VREF)
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
VSS
NC
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS
Pin Description
VG36643211 (2)
Pin Name
Function
Pin Name
A0 - A11
Address inputs
- Row address
A0 - A10
- Column address A0 - A8
A11 : Bank select
DQ0 ~ DQ31
Data - in/data - out
CLK
Clock input
RAS
Row address strobe
CKE
Clock enable
CAS
Column address strobe
WE
Write enable
VDDQ
Supply voltage for DQ
VSS
Ground
VSSQ
Ground for DQ
VDD
Power ( + 3.3V)
(VREF)
Reference Voltage, SSTL - 3 only
Document : 1G5-0099
DQM0 ~ 3
Function
CS
Rev.1
DQ Mask enable
Chip select
Page 2
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Pin Configuration
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDD
DQM0
WE
CAS
RAS
CS
NC
A12/BA0
A11/BA1
A10/AP
A0
A1
A2
DQM2
VDD
NC
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSS
DQM1
NC (VREF)
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
VSS
NC
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS
Pin Description
VG36643241 (2)
Pin Name
Function
Pin Name
A0 - A12
Address inputs
- Row address
A0 - A10
- Column address A0 - A7
A11 & A12 : Bank select
DQM0 ~ 3
DQ0 ~ DQ31
Data - in/data - out
CLK
Clock input
RAS
Row address strobe
CKE
Clock enable
CAS
Column address strobe
WE
Write enable
VDDQ
Supply voltage for DQ
VSS
Ground
VSSQ
Ground for DQ
VDD
Power ( + 3.3V)
(VREF)
Reference Voltage, SSTL - 3 only
Document : 1G5-0099
CS
Rev.1
Function
DQ Mask enable
Chip select
Page 3
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Block Diagram
CKE
Clock
Generator
Address
Mode
Register
(Bank D)
(Bank C)
Bank B
Row
Address
Buffer
&
Refresh
Counter
Row Decoder
CLK
Bank A
Data Control Circuit
Input & Output
Buffer
CAS
WE
DQM
Column Decoder &
Latch Circuit
Column
Address
Buffer
&
Burst
Counter
Latch Circuit
RAS
Control Logic
CS
Command Decoder
Sense Amplifier
Note: Bank C and Bank D are for VG36643241(2) only
Document : 1G5-0099
Rev.1
Page 4
DQ
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Absolute Maximum D.C. Ratings
Parameter
Voltage on any pin relative to Vss
Symbol
Value
Unit
VIN, VOUT
-0.5 to + 4.6
V
Supply voltage relative to Vss
VDD, VDDQ
-0.5 to + 4.6
V
IOUT
50
mA
PD
1.0
W
Operating temperature
TOPT
0 to + 70
°C
Storage temperature
TSTG
-55 to + 125
°C
Short circuit output current
Power dissipation
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Maximum A.C. Operating Requirements for LVTTL Compatible
Parameter
Symbol
Min
Max
Unit
Notes
Input High Voltage
VIH
2.0
VDDQ + 2.0
V
2
Input Low Voltage
VIL
VSSQ -2.0
0.8
V
2
Typ
Max
Unit
3.3
3.6
V
Recommended DC Operating Conditions for LVTTL Compatible
Parameter
Symbol
Min
Supply Voltage
VDD, VDDQ
3.0
Input High Voltage, all inputs
VIH
2.0
-
VDD + 0.3
V
Input Low Voltage, all inputs
VIL
-0.3
-
0.8
V
Typ
Max
Unit
3.3
3.6
V
Recommended DC Operating Conditions for SSTL - 3 Interface
Parameter
Symbol
Min
Supply Voltage
VDD, VDDQ
3.0
Supply Voltage (Ground)
VSS, VSSQ
0
-
0
V
VREF
1.3
1.5
1.7
V
VTT
VREF -005
VREF
VREF + 0.05
V
Input High Voltage, all inputs
VIH(dc)
VREF + 0.2
-
VDD + 0.3
V
Input Low Voltage, all inputs
VIH(dc)
-0.3
-
VREF -0.2
V
Reference Voltage
Termination Voltage
Capacitance
(Ta = 25°C, f = 1MHZ)
Parameter
Symbol
Typ
Max
Unit
Notes
Input capacitance (Address)
CI1
-
4
pF
1
Input capacitance (all input pins
except address pins & data pins.)
CI2
-
4
pF
1
Data input/output capacitance
CI/O
-
5
pF
1
Notes : 1. Capacitance measured with effective capacitance measuring method.
2. The overshoot and undershoot voltage duration is ≤ 3ns with no input clamp diodes.
Document : 1G5-0099
Rev.1
Page 5
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
VG36648041(2)B
Parameter
Symbol
Test Conditions
-8H
-8L
-10
Unit Notes
Min Max Min Max Min Max
CL = 3
100
100
90 mA
1
Operating current
ICC1
Burst length = 1
One bank active
CL = 2
95
95
85
tRC ≥ V
tRC(MIN.), Io = 0mA
CKE
Precharge standby
ICC 2P
current in power
ICC 2PS
down mode
Precharge standby
ICC 2N
current in Non - power
down mode
ICC 2NS
≤ VIH(MAX.) tCK = 15ns
≤ VIH(MAX.) tCK = ∞
3
3
3
2
2
2
20
20
20
6
6
6
≤ VIL(MAX.), tCK = 15ns
≤ VIL(MAX.), tCK = ∞
5
5
5
4
4
4
≥ V IH(MIN.), tCK = 15ns
CS ≥ V IH(MIN.)
CKE
25
25
25
10
10
10
CL = 3
160
160
135
CL = 2
145
125
105
CL = 3
CL = 2
130
125
2
130
125
2
CKE
CKE
≥ V IH(MIN.) tCK = 15ns
CKE
CS ≥ V IH(MIN.)Input signals are
CKE
CKE
mA
mA
changed one
time during 2 CLK cycles.
CKE ≥ VVIH(MIN.) , tCK = ∞
CKE
CLK ≤ VIL(MAX.)
Input signals are stable.
Active standby
current in power
down mode
Active standby
current in Nonpower
down mode
ICC 3P
CKE
ICC 3PS
CKE
ICC 3N
CKE
CKE
mA
mA
Input signals are changed
one time during 2CLKs.
ICC 3NS
≥ V IH(MIN.) tCK =
CLE ≤ VIL(MAX.)
CKE
CKE
∞
Input signals are stable.
Operating current
ICC4
(Burst mode)
Refresh current
ICC5
Selfrefresh current
ICC6
lnput Ieakege current ILI
tCK
CKE
≥ VtCK(MIN.)
Io = 0mA
All banks Active
tRC = tRC(MIN.)
≤ 0.2V
Vin ≥ V
0, Vin ≤ VDD + 0.3V
CKE
CKE
mA
2
110
105
2
mA
3,6
mA
-5
5
-5
5
-5
5
uA
-5
5
-5
5
-5
5
uA
0.4
V
4
V
4
V
5
Pins not under test = 0V
≥ V0, Vout ≤ VDD (MAX)
Output Ieakege
current
ILO
Vout
CKE
Output Low Voltage
VOL
DQ# in H - Z., Dout disabled
lOL = 2mA
Output High Voltage
VOH
lOH = -2mA
Output Low Voltage
VOL
lOL = 16mA
Output High Voltage
VOH
lOH = -16mA
0.4
2.4
0.4
2.4
VTT
+ 0.8
2.4
VTT
+ 0.8
VTT
+ 0.8
VTT
VTT
VTT
V
5
+ 0.8
+ 0.8
+ 0.8
Notes : 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open.
In addition to this, ICC1 is measured on condition that addresses are changed only one time duringtCK(MIN.).
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open.
In addition to this, ICC4 is measured on condition that addresses are changed only one time during t CK(MIN.).
3. ICC5 is measured on condition that addresses are changed only one time during tCK(MIN.).
4. For LVTTL compatible, VG3664321(4)1.
5. For SSTL - 3 interface, VG3664321(4)2.
6. Refresh on every 15.6 µ s.
Document : 1G5-0099
Rev.1
Page 6
VIS
Preliminary
A. C Characteristics : (Ta = 0 to 70°C VDD = 3.3V
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
± 0.3VSS = 0V)
Test Conditions for LVTTL Compatible :
AC input Levels (VIH/VIL)
2.0/0.8V
Input rise and fall time
1ns
Input timing reference level/
Output timing reference level
Output load condition
1.4V
50pF
AC Test Load Circuits (for LVTTL interface) :
VDDQ
1.4V
50
VDDQ
VOUT
Z = 50
Ω
Ω
Device
Under
Test
50PF
Test Conditions for SSTL - 3 Interface
Input Hihg (min)/Input low (max) Voltage
VREF + 0.4V/ Input Reference Voltage
(VREF)
VREF - 0.4V
Timing Reference Levels of Output Signals 0.45 x VDDQ Input Signal MAX. Slew Rate
Input Signal MAX. Peak to Peak Swing
2.0V
Output Circuit
Min. Required output pull - up under AC
test load
VTT + 0.8V
0.45 x VDDQ
Min. Required output pull down under AC test load
1V/ns
See Figure
Below
VTT - 0.8V
AC Test Load Circuits (for SSTL - 3 interface) :
VDDQ
VDDQ
VREF
0.45 * VDDQ
VTT = 0.45 * VDDQ
RT2 = 50 Ohms
VOUT
VIN
RS = 25Ohms
Device
Under
Test
Z = 50 Ohms
VREF = 0.45 * VDD
RT1 = 50 Ohms
CLOAD = 30 pF
VTT = 0.45 * VDDQ
VSS
Document : 1G5-0099
Rev.1
Page 7
VIS
Preliminary
A.C Characteristics : (Ta = 0 to 70°C VDD = 3.3V
Parameter
± 0.3V, VSS = 0V)
CAS
Latency symbol
CLK cycle time
Max
Min
Max
Min
Max
8
10
3
3
2
1
2
1
2
1
2
3
3
2
1
2
1
2
1
2
3
3
3
1
3
1
3
1
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data input hold time
tDH
1
1
1
ns
Output data hold time
CLK to output in low - Z
CLK to output in Hi - Z
tOH
tLZ
tHZ
3
0
3
0
3
0
ns
ns
ns
CLK to output in Hi - Z without load
tOHN
1
1
2
ns
Row active to active delay
RAS to CAS delay
Row precharge time
ROW active time
ROW cycle time
Last data in to burst stop
tRRD
tRCD
tRP
tRAS
tRC
tBDL
16
20
20
48
70
1
16
20
20
48
70
1
20
26
26
60
90
1
ns
ns
ns
ns
ns
CLK
Data - in to ACT(REF) command
Data - in to precharge
Transition time
tDAL
tDPL
tT(1)
tT(2)
tRSC
tSRX
tREF
1+ t RP
8
1
0.2
2
1
CLK high pulse width
CLK low pulse width
CKE setup time
CKE hold time
Address setup time
Address hold time
Command setup time
Command hold time
Data input setup time
Mode reg. set cycle
Self refresh exit time
Refresh time
3
2
8
12
Unit
-10
tck3
tck2
tAc3
tAc2
tCH
tCL
tCKS
tCKH
tAS
tAH
tCMS
tCMH
tDS
CLK to valid output delay
3
2
3
2
VG3664321 (4) 1 (2) B
-8L
-8H
Min
(1)
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
6
6
10
5
Rev.1
6
6
6
6
1+ tRP
8
1
0.2
2
1
64
Notes : (1) The input clock should be stable and continuous. (jitter
Document : 1G5-0099
6
6
6
6
120K
10
15
120K
10
5
64
6
6
1+ tRP
10
1
0.2
2
1
120K
10
5
64
CLK
ns
ns
CLK
CLK
ms
≤ 7% * tCK)
Page 8
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Basic Features and Function description
1. simplified State diagram
Self
Refresh
LF
SE
Mode
Register
Set
try
en
LF
SE
MRS
it
ex
AUTO
Refresh
REF
IDLE
E
CK
ACT
CK
E
Power
Down
CKE
ROW
ACTIVE
y
Au Write
to p
red with
har
ge
re
co
ve
r
e
rit
W
CKE
WRITE
Read (write recovery)
CKE
e re
READ
SUSPEND
Read with
Auto Precharge
)
cov
ery)
CKE
CKE
READA
SUSPEND
n)
(P r
ech
arg
e
READ A
PR
E
tio
ina
Precharge
CKE
CKE
ith e
te w arg
Wri Prech
uto
(writA
m
ter
POWER
ON
READ
ter
min
atio
n
WRITE A
CKE
R
Auto ead w
Pre ith
cha
rge
rge
cha
P re
E(
PR
CKE
Read
Write
Write with
Auto Precharge
WRITE A
SUSPEND
PRE
WRITE
SUSPEND
ad
Re
Write (Write recovery)
h
wit rge
ad cha
Re Pre
to
Au
W
rit
e
T
BS
BS
T
CKE
Active
Power
Down
Precharge
Automatic sequence
Manual input
Note: After the AUTO refresh operation, precharge operation is
performed automatically and enter the IDLE state
Document : 1G5-0099
Rev.1
Page 9
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
2.Truth Table
2.1 Command Truth Table
FUNCTION
Device deselect
No operation
Mode register set
Bank activate
Read
Read with auto precharge
Write
Write with auto precharge
Precharge select bank
Precharge all banks
Burst stop
CBR (Auto) refresh
Self refresh
Symbol
DESL
NOP
MRS
ACT
READ
READA
WRIT
WRITA
PRE
PALL
BST
REF
SELF
CKE
n-1
n
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
H
L
CS
H
L
L
L
L
L
L
L
L
L
L
L
L
RAS
X
H
L
L
H
H
H
H
L
L
H
L
L
CAS
X
H
L
H
L
L
L
L
H
H
H
L
L
BA(1)
X
X
L
V
V
V
V
V
V
X
X
X
X
WE
X
H
L
H
H
H
L
L
L
L
L
H
H
A10
X
X
L
V
L
H
L
H
L
H
X
X
X
A9 - A0
X
X
V
V
V
V
V
V
X
X
X
X
X
Notes : (1) Bank address. lt would be different from organizations.
2.2 DQM Truth Table
FUNCTION
Data write/output enable
Data mask/output disable
DQ24 ~ DQ31 write enable/output enable
DQ16 ~ DQ23 write enable/output enable
DQ8 ~ DQ7 write enable/output enable
DQ0 ~ DQ7 write enable/output enable
DQ24 ~ DQ31 write enable/output enable
DQ16 ~ DQ23 write enable/output enable
DQ8 ~ DQ15 write enable/output enable
DQ0 ~ DQ7 write enable/output enable
CKE
n-1
n-1
H
X
H
X
H
X
H
X
H
X
H
X
H
X
H
X
H
X
H
X
Symbol
ENB
MASK
ENB3
ENB2
ENB1
ENB0
MASK3
MASK2
MASK1
MASK0
DQM
3
2
1
0
X
X
L
X
X
X
H
X
X
X
L
X
X
X
H
L
H
L
X
X
X
H
X
X
X
X
L
X
X
X
H
X
X
RAS
X
X
X
L
L
H
X
X
X
CAS
X
X
X
L
L
H
X
X
X
2.3 CKE Truth Table
Current State
Activating
Any
Clock suspend
Idle
Idle
Self refresh
Function
Clock suspend mode entry
Clock suspend
Clock suspend mode exit
CBR refresh command
Self refresh entry
Self refresh exit
Idle
Power down
Power down entry
Power down exit
CKE
n-1
H
L
L
H
H
L
L
H
L
Symbol
REF
SELF
n
L
L
H
H
L
H
H
L
H
CS
X
X
X
L
L
L
H
X
X
Add
WE ress
X
X
X
X
X
X
H
X
H
X
H
X
X
X
X
X
X
X
H : High level, L : Low level
X : High or Low level (Don’t care), V : Valid Data input
Document : 1G5-0099
Rev.1
Page 10
VIS
Preliminary
2.4 Operative Command Table Notes 1
RAS CAS WE
Address
Idle
H
X
X
X X
L
H
H
X X
L
H
L
H BA, CA, A10
L
H
L
L BA, CA, A10
L
L
H
H BR, RA
L
L
H
L BA, A10
L
L
L
H X
L
L
L
L Op - Code
Row active
H
X
X
X X
L
H
H
X X
L
H
L
H BA, CA, A10
L
H
L
L BA, CA, A10
L
L
H
H BA, RA
L
L
H
L BA, A10
L
L
L
H X
L
L
L
L Op - Code
Read
H
X
X
X X
Current state CS
Write
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
(1/3)
Command
Action
Notes
DESL
Nop or Power down
2
NOP or BST
Nop or Power down
2
READ/READA ILLEGAL
3
WRIT/WRITA
ILLEGAL
3
ACT
Row active
PRE/PALL
Nop
REF/SELF
Refresh or Self refresh
MPS
Mode register access
DESL
Nop
NOP or BST
Nop
4
READ/READA Begin read : Determine AP
5
WRIT/WRITA
Begin write : Determine AP
5
ACT
ILLEGAL
3
PRE/PALL
Precharge
6
REF/SELF
ILLEGAL
MRS
ILLEGAL
DESL
Continue burst to end
L
H
H
H
X
NOP
Continue burst to end
L
H
H
L
X
BST
Burst stop
→ Row active
→ Row active
→ Row active
L
H
L
H
BA, CA, A10
READ/READA Term burst, new read : Determine AP
7
L
H
L
L
BA, CA, A10
WRIT/WRITA
Term burst, start write : Determine AP
7,8
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
Term burst, precharging
L
L
L
H
X
REF/SELF
ILLEGAL
L
L
L
L
Op - Code
MRS
ILLEGAL
H
X
X
X
X
DESL
Continue burst to end
L
H
H
H
X
NOP
Continue burst to end
L
H
H
L
X
BST
Burst stop
L
H
L
H
BA, CA, A10
READ/READA Term burst, start read : Determine AP
7,8
L
H
L
L
BA, CA, A10
WRIT/WRITA
Term burst, new write : Determine AP
7
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
Term burst, precharging
9
L
L
L
H
X
REF/SELF
ILLEGAL
L
L
L
L
Op - Code
MRS
ILLEGAL
Document : 1G5-0099
Rev.1
→ write recovering
→ write recovering
→ Row active
Page 11
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
(2/3)
Current state
Read with auto
precharge
Write with auto
precharge
Precharging
Row activating
CS RAS CA WE
Address
Command
Action
H
X
X
X X
DESL
Continue burst to end
L
H
H
H X
NOP
L
H
H
L
BST
Continue burst to end
ILLEGAL
L
H
L
H BA, CA, A10
L
H
L
L
L
L
H
H BA, RA
L
L
H
L
L
L
L
H X
X
BA, CA, A10
BA, A10
Op - Code
→
→
No
Precharging
Precharging
READ/READA ILLEGAL
11
WRIT/WRITA
ILLEGAL
11
ACT
ILLEGAL
3,11
PRE/PALL
ILLEGAL
3,11
PEF/SELF
ILLEGAL
L
L
L
L
MRS
ILLEGAL
H
X
X
X X
DESL
Continue burst to end → write
recovering with auto precharge
L
H
H
H X
NOP
Continue burst to end → write
recovering with auto precharge
L
H
H
L
BST
ILLEGAL
L
H
L
H BA, CA, A10
READ/READA ILLEGAL
11
L
H
L
L
WRIT/WRITA
11
X
BA, CA, A10
ILLEGAL
L
L
H
H BA, RA
ACT
ILLEGAL
3,11
L
L
H
L
PRE/PALL
ILLEGAL
3,11
BA, A10
L
L
L
H X
REF/SELF
ILLEGAL
L
L
L
L
MRS
ILLEGAL
H
X
X
X X
DESL
Nop
L
H
H
H X
NOP
Nop
L
H
H
L
BST
Nop
Op - code
X
→ Enter idle after tRP
→ Enter idle after tRP
→ Enter idle after tRP
L
H
L
H BA, CA, A10
READ/READA ILLEGAL
3
L
H
L
L
WRIT/WRITA
ILLEGAL
3
L
L
H
H BA, RA
ACT
ILLEGAL
3
L
L
H
L
PRE/PALL
Nop
BA, CA, A10
BA, A10
→
Enter idle after tRP
L
L
L
H X
REF/SELF
ILLEGAL
L
L
L
L
MRS
ILLEGAL
H
X
X
X X
DESL
Nop
L
H
H
H X
NOP
Nop
L
H
H
L
BST
Nop
Op - Code
X
→
→
→
Enter row active after t RCD
Enter row active after t RCD
Enter row active after t RCD
L
H
L
H BA, CA, A10
READ/READA ILLEGAL
3
L
H
L
L
WRIT/WRITA
ILLEGAL
3
L
L
H
H BA, RA
ACT
ILLEGAL
3,9
3
BA, CA, A10
L
L
H
L
PRE/PALL
ILLEGAL
L
L
L
H X
REF/SELF
ILLEGAL
L
L
L
L
MRS
ILLEGAL
Document : 1G5-0099
BA, A10
Op - Code
Rev.1
Page 12
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
(3/3)
Current state
Write
recovering
Write
recovering
with auto
precharge
Auto
Refreshing
Mode register
accessing
CS
RAS
CA
WE
Address
Command
Action
Notes
H
X
X
X
X
DESL
Nop
L
H
H
H
X
NOP
Nop
→
→
L
H
H
L
X
BST
Nop
→
L
H
L
H
BA, CA, A10
READ/READA
Start read, Determine AP
Enter row active after tDPL
Enter row active after tDPL
Enter row active after tDPL
8
L
H
L
L
BA, CA, A10
WRIT/WRITA
New write, Determine AP
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
3
L
L
L
H
X
PEF/SELF
ILLEGAL
L
L
L
L
Op - Code
MRS
ILLEGAL
H
X
X
X
X
DESL
Nop
L
H
H
H
X
NOP
Nop
→
→
L
H
H
L
X
BST
Nop
→
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3,8,11
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3,11
L
L
H
H
BA, RA
ACT
ILLEGAL
3,11
L
L
H
L
BA, A10
REF/PALL
ILLEGAL
3
Enter precharge after tDPL
Enter precharge after tDPL
Enter precharge after tDPL
L
L
L
H
X
REF/SELF
ILLEGAL
L
L
L
L
Op - Code
MRS
ILLEGAL
H
X
X
X
X
DESL
Nop Enter idle after tRC
L
H
H
X
X
NOP/BST
Nop Enter idle after tRC
L
H
L
X
X
READ/WRIT
ILLEGAL
L
L
H
X
X
ACT/PRE/PALL
ILLEGAL
L
L
L
X
X
REF/SELF/MRS ILLEGAL
H
X
X
X
X
DESL
Nop
L
H
H
H
X
NOP
Nop
L
H
H
L
X
BST
ILLEGAL
L
H
L
X
X
READ/WRITE
ILLEGAL
L
L
X
X
X
→
→
Enter idle after 2 Clocks
Enter idle after 2 Clocks
ACT/PRE/PALL/ ILLEGAL
REF/SELF/MRS
Note 1. All entries assume that CKE was active (High level) during the preceding clock cycle.
2. If both banks are idle, and CKE is inactive (Low level), the device will enter Power down mode.
All input buffers except CKE will be disabled.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address
(BA), depending on the state of that bank.
4. If both banks are idle, and CKE is inactive (Low level), the device will enter Self refresh mode.All
input buffers except CKE will be disabled.
5. Illegal if tRCD is not satisfied.
6. Illegal if tRAS is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Must mask preceding data which don’t satisfy tDPL.
10. Illegal if tRRD is not satisfied.
11. Illegal for single bank, but legnl for other banks in mulfi - bank deuleo.
Document : 1G5-0099
Rev.1
Page 13
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
2.5 Command Truth Table for CKE Note 1
Current state
Self refresh
(S.R.)
Self refresh
recovery
Power down
(P.D.)
Both banks idle
Any state other
than listed
above
CKE
n-1
CKE
n
CS
RAS
CAS
WE
Address
H
L
L
L
L
L
H
X
H
H
H
H
L
H
X
H
L
L
L
X
H
X
X
H
H
L
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INVALID, CLK (n - 1)would exit S.R.
S.R. Recovery
2
S.R. Recovery
2
ILLEGAL
ILLEGAL
Maintain S.R.
Idle after tRC
Idle after tRC
H
H
L
H
H
X
X
H
H
H
H
H
H
L
L
H
L
L
H
H
H
L
L
L
L
H
L
X
H
L
H
L
L
H
L
L
L
X
X
X
X
X
H
H
L
X
H
H
L
X
X
X
X
X
X
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
L
H
X
X
H
H
L
L
H
X
H
H
H
H
L
L
L
L
L
L
H
L
H
L
H
X
X
X
H
L
L
H
X
X
H
L
L
L
H
X
H
H
L
L
L
L
L
L
L
L
H
L
L
H
X
H
X
X
X
X
X
X
X
X
Action
Notes
ILLEGAL
ILLEGAL
Begin clock suspend next cycle
Begin clock suspend next cycle
ILLEGAL
ILLEGAL
Exit clock suspend next cycle
Maintain clock suspend
INVALID, CLK (n - 1) would exit P.D.
X
EXIT P.D. → Idle
X
Maintain power down mode
Refer to operations in Operative
Command Table
Refer to operations in Operative
Command Table
Refer to operation in Operative
Command Table
X
Auto Refresh
Op - Code Refer to operations in Operative
Command Table
Refer to operations in Operative
Command Table
Refer to operations in Operative
Command Table
Refer to operations in Operative
Command Table
X
Self refresh
Op - Code Refer to operations in Operative
Command Table
X
X
Power down
Refer to operations in Operative
Command Table
Begin clock suspend next cycle
Exit clock suspend next cycle
Maintain clock suspend
5
5
2
2
3
3
H
L
X
X
X
X
X
4
L
H
X
X
X
X
X
L
L
X
X
X
X
X
Note 1. H : Hight level, L : low level, X : High or low level (Don't care).
2. CKE Low to High transition will re - enable CLK and other inputs asynchronously. A minimum setup time
must be satisfied before any command other than EXIT.
3. Power down and Self refresh can be entered only from the both banks idle state.
4. Must be legal command as defined in Operative Command Table.
5. Illegal if tSREX is not satisfied.
Document : 1G5-0099
Rev.1
Page 14
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
5.Mode Register (Address Input for Mode Set)
13 12 11
0 0 0
10
0
9
0
8
0
1
13 12 11
x
x x
10
x
9
1
8
0
7
0
6
13 12
x x
10
x
9
0
8
0
7
0
6
11
x
7
6
5
3
4
2
Reserved
5
4
LTMODE
5
4
LTMODE
3
WT
2
3
WT
2
1
0
JEDEC Standard Test Set
1
BL
0
1
BL
0
Burst Read and Single Write (for Write Through Cache)
Burst Read and Burst Write
X = Don’t care
Bits2 - 0 WT = 0 WT = 1
1
000
1
001
2
2
010
011
4
4
8
8
Burst length
Wrap type
100
R
R
101
R
R
110
R
R
111
Full page
R
0
1
Sequential
Interleave
Bits6 - 4 CAS Iatency
R
000
001
Latency
mode
R
010
2
011
3
100
R
101
R
110
R
111
R
Remark R : Reserved
Document : 1G5-0099
Rev.1
Page 15
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
5.1 Burst Length and Sequence
(Burst of Two)
Starting Address
(column address A0, binary)
0
1
Sequential Addressing
Sequence (decimal)
0, 1
1, 0
Interleave Addressing Sequence (decimal)
(Burst of Four)
Starting Address
(column address A1 - A0, binary)
00
01
10
11
Sequential Addressing
Sequence (decimal)
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
Interleave Addressing Sequence (decimal)
(Burst of Eight)
Starting Address
(column address A2 - A0, binary)
000
001
010
011
100
101
110
111
Sequential Addressing
Sequence (decimal)
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1 ,2
4, 5, 6, 7, 0, 1, 2, 3
5, 6 ,7, 0, 1, 2, 3, 4
6, 7 ,0 ,1 ,2 ,3 ,4 ,5
7, 0, 1, 2, 3, 4, 5, 6
Interleave Addressing Sequence(decimal)
0, 1
1, 0
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
Full page burst is an extension of the above tables of sequential addressing, with the length
being 256 for 4B 2M x 32, and 512 for 2B 2M x 32.
Document : 1G5-0099
Rev.1
Page 16
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
6.Address Bits of Bank-Select and Precharge
6.1 Qual banks controlled by A11 (for VG36643211/VG36643212)
Row
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
(Activate command)
Row A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
(Activate command)
0
1
A10
0
0
1
Select Bank A “Activate” command
Select Bank B “Activate” command
A11
0
1
X
Result
Precharge Bank A
Precharge Bank B
Precharge All Banks
X : Don’t care
0 disables Auto - Precharge (End of Burst)
1 Enables Auto - Precharge (End of Burst)
Co1. A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
(CAS strobes)
Document : 1G5-0099
Rev.1
0
enables Read / Write commands for Bank B
1
enables Read / Write commands for Bank B
Page 17
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
6.2 Quad banks controlled by A11 & A12 (for VG36643241 / VG36643242)
Row A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
(Activate command)
Row A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
(Precharge command)
A11
0
A12
0
0
1
1
0
1
1
A10
0
0
0
0
1
A11
0
0
1
1
x
Result
Select Bank A
“Activate” command
Select Bank B
“Activate” command
Select Bank C
“Activate” command
Select Bank D
“Activate” command
A12
0
1
0
1
x
Result
Precharge Bank A
Precharge Bank B
Precharge Bank C
Precharge Bank D
Precharge AII Banks
X : Don’t care
0
1
Col. A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
(CAS strobes)
Document : 1G5-0099
Rev.1
Disables Auto - Precharge (End of Burst)
Enables Auto - Precharge (End of Burst)
A11
0
A12
0
0
1
1
0
1
1
Result
Enables Read / Write
commants for Baml A
Enables Read / Write
commants for Baml B
Enables Read / Write
commants for Baml C
Enables Read / Write
commants for Baml D
Page 18
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
7.PRECHARGE
The precharge command can be asserted anytime after tRAS(min) is satisfied.
Soon after the precharge command is asserted, the precharge operation is performed and the
synchronous DRAM enters the idle state after t RP(min.) is satisfied. The parameter tRP is the time
required to perform the precharge.
The earliest timing in a read cycle that a precharge command can be asserted without losing
any data in the burst is as follows.
PRECHARGE
T0
T1
T3
T2
T4
T6
T5
Burst length = 4
T7
CLK
Command
Read
PRE
CAS latency = 2
DQ
Q0
Command
Q1
Read
Q2
Hi - Z_
Q3
PRE
CAS latency = 3
DQ
Q1
Q0
CAS latency = 2 : One clock earlier than the last output data.
3 : Two clocks earlier than the last output data.
4 : Three clocks earlier than the last output data.
Q2
Q3
Hi - Z
(tRAS is satisfied)
In order to write all data to the memory cell correctly, the asynchronous parameter ”tDPL” must
be satisfied. The tDPL(min.) specification defines the earliest time that a precharge command can be
asserted. The minimum number of clocks are calculated by dividing t DPL(min.) by the clock cycle
time.
In summary, the precharge command can be asserted relative to reference clock that indicates the last data word is valid. In following table, minus means clocks before the reference; plus
means time after the reference.
CAS latency
Read
Write
Document : 1G5-0099
2
-1
+ tDPL(min.)
3
-2
+ tDPL(min.)
Rev.1
Page 19
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
8.Auto Precharge
During a read or write command cycle, A10 controls whether auto precharge is selected.
If A10 is high in the read or write command (Read with Auto precharge command or Write with
Auto precharge command), auto precharge is selected and precharging begins automatically
after the burst access.
In the write cycle, tDAL(min.) must be satisfied before asserting the next activate command
to the bank being precharged.
When using auto precharge in the read cycle, knowing when the precharge starts is
important because the next activate command to the bank being precharged cannot be executed until the precharge cycle ends. Once auto precharge has started, an activate command
to the bank can be asserted after tRP has been satisfied.
A Read or Write command without auto - precharge can be terminated in the midst of a
burst operation. However, a Read or Write command with auto - precharge can not be interrupted by the same bank commands before the entire burst operation is completed. Therefore
use of the same bank Read, Write, Precharge or Burst Stop command is prohibited during a
read or write cycle with auto - precharge. It should be noted that the device will not respond to
the Auto - Precharge command if the device is programmed for full page burst read or write
cycles.
The timing when the auto precharge cycle begins depends both on both the CAS Iatency
programmed into the mode register and whether the cycle is read or write.
8.1 Read with Auto Precharge
During a READA cycle, the auto precharge begins one clock earlier (CL = 2) or two
clocks earlier (CL = 3) than the last word output.
READ with AUTO PRECHARGE
Burst length = 4
T0
T1
T4
T3
T2
T6
T5
T7
CLK
Command
Auto precharge starts
READA B
CAS latency = 2
DQ
QB0
QB1
QB2
Hi - Z
QB3
Auto precharge starts
Command
READA B
CAS latency = 3
DQ
QB0
QB1
QB2
QB3
Hi - Z
Remark READA means READ with AUTO PRECHARGE
Document : 1G5-0099
Rev.1
Page 20
T8
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
8.2 Write with Auto Precharge
During a write cycle, the auto precharge starts at the timing that is equal to the value
of tDPL(min.) after the last data word input to the device.
WRITE with AUTO PRECHRGE
Burst length = 4
T0
T1
T3
T2
T4
T5
T6
T7
CLK
Command
AUTO PRECHARGE starts
WRITA B
tDPL
CAS latency = 2
DQ
DB0
DB2
DB1
Hi - Z_
DB3
AUTO PRECHARGE starts
Command
WRITA B
tDPL
CAS latency = 3
DQ
DB0
DB2
DB1
Hi - Z
DB3
Remark WRITA means WRITE with Auto precharge
In summary, the auto precharge cycle begins relative to a reference clock
that indicates the last data word is valid.
In the table below, minus means clocks before the reference; plus means
clocks after the reference.
Document : 1G5-0099
CAS latency
2
Read
-1
Write
+ tDPL(min.)
3
-2
+ tDPL(min.)
Rev.1
Page 21
T8
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
8.3 Multidank Operation - Read with Auto Precharge
During a READA cycle interrupted by a Read. Write command of
another banks, the auto - precharge scheduled time would not be changed.
Multibank Operation
Burst lengh=8
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11 T12 T13 T14
CLK
Auto precharge bank A starts
Command
READA A
Read B
CAS latency=2
Hi-Z
DQ
QA0
QA1
QB0
QB1
QB2
QB3
QB4
QB5
QB6
QB7
Auto precharge bank A starts
Command
READA A
Read B
CAS latency=3
DQ
Hi-Z
QA0
QA1
QB0
QB1
QB2
QB3
QB4
QB5
QB6
QB7
similiar top. 21
Document : 1G5-0099
Rev.1
Page 22
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
8.3 Multidank Operation - Write with Auto Precharge
During a WRITEA cycle interrupted by a Read, Write command of another banks, the
auto - precharge scheduled time would not be changed.
Multidank Operation
Burst length = 8
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
Auto precharge bank A starts
Command
WRITA A
Read B
CAS latency=2
DQ
DA0
DB0
DA1
DB1
DB2
DB3
DB4
DB5
Hi-Z
Auto precharge bank A starts
Command
WRITA A
Read B
CAS latency=3
DQ
DA0
DB0
DA1
DB1
DB2
DB3
DB4
Hi-Z
Multibank Operation
Burst length = 8
T0
T1
T2
T3
T4
T5
T6
T7
CLK
Command
T8
T9
T10
T11
Auto precharge bank A starts
WRITA A
Write B
CAS latency=2
DQ
DA0
DA1
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Hi-Z
Auto precharge bank A starts
Command
Write B
WRITA A
CAS latency=3
DQ
DA0
Document : 1G5-0099
DA1
DB0
DB1
DB2
DB3
Rev.1
DB4
DB5
DB6
DB7
Hi-Z
Page 23
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
9.READ/WRITE Command Interval
9.1 Read to Read command interval
During a read cycle when a new read command is asserted, it will be effective after the CAS
latency, even if the previous read operation has not completed. READ will be interrupted by another
READ.
Each read command can be asserted in every clock without any restriction.
READ to READ Command Interval
Burst lengh=4, CAS latency=2
T0
T1
T3
T2
T4
T6
T5
T7
T8
CLK
Read B
Read A
Command
DQ
QA0
QB0
QB1
QB2
Hi-Z_
QB3
1 cycle
9.2 WRITE to WRITE Command Interval
During a write cycle, when a new Write command is asserted, the previous burst will terminated
and the new burst will begin with a new write command. WRITE will be interrupted by another
WRITE.
Each write command can be asserted in every clock without any restriction.
WRITE to WRITE Command Interval
Burst lengh=4, CAS latency=2
T0
T1
T3
T2
T4
T5
T6
T7
CLK
Command
Write A
Write B
DQ
QA0
QB0
QB1
QB2
QB3
Hi-Z_
1 cycle
Document : 1G5-0099
Rev.1
Page 24
T8
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
9.3 Write to Read Command lnterval
The write command to read command to read command interval is also a minimum of 1 cycle. Only the
write data before the read command will be written. The data bus must be Hi - Z at least one cycle prior to
the first DOUT.
Burst length = 4
T0
T1
T2
T3
T4
T6
T5
T7
T8
CLK
1 cycle
Command
WRITE A
Read B
CAS latency=2
DQ
Command
Hi-Z
DA0
Write A
QB0
QB1
QB2
QB3
Read B
CAS latency=3
DQ
DA0
Hi-Z
QB0
QB1
QB2
QB3
9.4 Read to Write command lnterval
During READ cycle, READ can be interrupted by WRITE. When the CAS latency is 3
and the burst length is Full page, the burst read cannot be interrupted by WRITE (A Burst
Stop command (BST) or a - Precharge command can interrupt).
In case CAS latency is 2, the read and write command interval is 1 cycle minimum.
The data bus must be Hi - Z using DQM before WRITE and DQM must be High at least 3
clocks prior to the Write command. There is a restriction to avoid data conflict.
In case CAS latency is 3 (bust length is not Full page), READ can be interrupted by
WRITE command. The minimum command interval is [burst length + 1] cycles. DQM
must be High at least 3 clocks prior to the Write command.
Document : 1G5-0099
Rev.1
Page 25
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
READ to WRITE Command Interval
T0
T1
T3
T2
T4
T6
T5
T7
CAS latency = 2
T8
CLK
Read
command
Write
DQM
Hi-Z
D0
DQ
D1
D2
D3
1 cycle
T0
T1
T3
T2
T4
Burst length = 8, CAS latency = 2
T9
T8
T6
T5
T7
CLK
Command
Write
Read
DQM
Q0
DQ
Q2
Q1
D0
D2
D1
Hi-Z is
necessary
example: Burst length = 4, CAS latency = 3
T0
T1
T2
T3
T4
T6
T5
T8
T7
CLK
Command
Read
Write
DQM
DQ
Q2
Hi-Z is
D0
D1
D2
necessary
The minimum command interval = (4+1) cycles
Document : 1G5-0099
Rev.1
Page 26
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
10. Burst Termination
There are two methods to terminate a burst operation other than using a read or a write
command. Ond is the burst stop command and the other is the precharge command.
10.1 Burst Stop Command
During a read burst, when the burst stop command is asserted, the burst read data are
terminated and the data bus goes to high - impedance after the CAS latency from the burst
stop command.
During a write burst, when the burst stop command is asserted, any data provided at
that cycle will not be written. The burst write is effectively terminated and no further data
can be written until a new write command is asserted.
Burst Termination
T0
T1
T3
T2
T4
T5
Burst length = X, CAS Intency=2,3
T7
T6
CLK
BST
Read
Command
Q0
CAS latency=2
DQ
CAS latency=3
Q1
Q2
Q0
Q1
Hi-Z
Hi-Z
Q2
DQ
Remark BST : Burst stop command
T0
T1
T3
T2
T4
T5
Burst length = X, CAS latency=2,3
T7
T6
CLK
Command
BST
Write
CAS latency=2,3
Q0
Q0
Q1
Q2
Hi-Z_
DQ
Remark BST : Burst stop command
Document : 1G5-0099
Rev.1
Page 27
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
10.2 Precharge Termination
10.2.1
During READ cycle, the burst read operation is terminated by a precharge command. When the precharge command is asserted, the burst read operation is terminated and precharge starts.
The same bank can be activated again after tRP from the precharge command.
When CAS latency is 2, the read data will remain valid until one clock after the
precharge command.
When CAS latency is 3, the read data will remain valid until two clocks after the
precharge command.
Precharge Termination in READ Cycle
T0
T1
T3
T2
T4
T6
T5
T7
Burst length = X
T8
CLK
Command
Read
PRE
ACT
CAS latency=2
Q0
DQ
Q1
Q2
Hi-Z
Q3
tRP
command
Read
PRE
ACT
CAS latency=3
DQ
Q0
Q1
Q3
Q2
Hi-Z
tRP
Document : 1G5-0099
Rev.1
Page 28
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
10.2.2 Precharge Termination in WRITE Cycle
During WRITE cycle, the burst write operation is terminated by a precharge
command. When the precharge command is asserted, the burst write operation is
terminated and precharge starts.
The same bank can be activated again after tRP from the precharge command.
The DQM must be high to mask invalid data in.
When CAS latency is 2, the write data written prior to the precharge command
will be correctly stored. However, invalid data may be written at the same clock as
the precharge command. To prevent this from happening, DQM must be high at the
same clock as the precharge command. This will mask the invalid data.
When CAS latency is 3, the write data written prior to the precharge command
will be correctly stored. However, invalid data may be written at the same clock as
the precharge command. To prevent this from happening, DQM must be high at the
same clock as the precharge command. This will mask the invalid data.
T0
T1
T3
T2
T4
T6
T5
T7
Burst length = X
T8
CLK
Command
Write
PRE
ACT
CAS latency = 2
DQM
DQ
D0
D1
D2
D3
Hi - Z
D4
tRP
command
Write
PRE
ACT
CAS latency = 3
DQM
DQ
D0
D1
D2
D3
D4
Hi - Z
tRP
Document : 1G5-0099
Rev.1
Page 29
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Timing Diagram
Document : 1G5-0099
Rev.1
Page 30
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Mode Register Set
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
CKE
t
RSC
CS
RAS
CAS
WE
BS
A10
Address Key
ADD
DQM
t
DQ
RP
Hi-Z
Precharge
Command
All Banks
Document : 1G5-0099
Mode Register
Set Command
Rev.1
Command
Page 31
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
AC Parameters for Write Timing (1 of 2)
Burst Length = 4, CAS Latency = 2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
t
CL
t
CH
CKE
Begin Auto Precharge Begin Auto Precharge
Bank A
Bank B (Bank D)
t
CMS
t
CMH
t
CKS
t
CKH
CS
RAS
CAS
WE
BS
A10
t
t
AS
AH
ADD
DQM
t
RCD
DQ
t
RRD
t
DS
t
DAL
t
RC
t
DH
t
DPL
t
RP
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3
Activate
Write with
Command Auto Precharge
Command
Bank A
Bank A
Document : 1G5-0099
Write with
Activate
Command Auto Precharge
Command
Bank B
(Bank D)
Bank B
(Bank D)
Activate
Command
Bank A
Rev.1
Write with
Auto Precharge
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank B
(Bank D)
Page 32
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
AC Parameters for Write Timing (2 of 2)
Burst Length = 4, CAS Latency = 3
T0 T1 T2 T3
CLK
CKE
t
CL
t
CH
T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
t
CK3
t
CMS
t
CKS
Begin Auto Precharge
Bank A
Begin Auto Precharge
Bank B (Bank D)
t
CKH
t
CMH
CS
RAS
CAS
WE
BS
A10
tAS
tAH
ADD
DQM
tRCD
DQ
t
DAL
t
RRD
tDS
tRC
QAa0 QAa1 QAa2 QAa3
Activate
Command
Bank A
Document : 1G5-0099
Write with
Auto Precharge
Command
Bank A
Activate
Command
Bank B
(Bank D)
t
DH
QBa0 QBa1 QBa2 QBa3
Write with
Auto Precharge
Command
Bank B
(Bank D)
Rev.1
Activate
Command
Bank A
t
DPL
t
RP
QAb0 QAb1 QAb2 QAb3
Write without
Auto Precharge
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Page 33
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
AC Parameters for Read Timing (1 of 2)
Burst Length = 2, CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
CLK
tCH tCL
tCK2
Begin Auto
Precharge
Bank B (Bank D)
tCMS
t
CMH
CKE
tCKS
t
CKH
CS
RAS
CAS
WE
BS
A10
tAS
tAH
ADD
tRRD
tRAS
tRC
DQM
t
AC2
tLZ
t
RCD
DQ
Hi-Z
QAa0
Activate
Command
Bank A
Document : 1G5-0099
tAC2
tOH
Read
Command
Bank A
Activate
Command
Bank B
Rev.1
tHZ
tOH
QAa1
tRP
tHZ
QBa0
QBa1
Activate
Read with
Precharge
Command
Command
Auto Precharge
Bank A
Bank
B
(Bank
D)
Bank B (Bank D)
Page 34
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
AC Parameters for Read Timing (2 of 2)
Burst Length = 2, CAS Latency = 3
T0
CLK
t
CH tCL
CKE
tCKS
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12 T13 T14 T15
t
CK3
Begin Auto
Precharge
Bank B (Bank D)
t
CMS
t
CMH
t
CKH
CS
RAS
CAS
WE
BS
A10
t
AH
t
AS
ADD
t
RRD
t
RAS
t
RP
t
RC
DQM
tAC3
tLZ
t
RCD
DQ
tAC3
tOH
tHZ
tOH
Hi-Z
QAa0
Activate
Command
Bank A
Document : 1G5-0099
Read
Command
Bank A
Activate
Command
Bank B
(Bank D)
Rev.1
QAa1
Read with
Auto Precharge
Command
Bank B (Bank D)
t
QBa0
Precharge
Command
Bank A
HZ
QBa1
Activate
Command
Bank A
Page 35
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Power on Sequence and Auto Refresh (CBR)
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High level
is required
t
RSC
Minimum of 2 Refresh Cycles are required
CS
RAS
CAS
WE
BS
A10
Address Key
ADD
DQM
High Level is Necessary
t
t
RP
RC
DQ
Precharge 1st Auto
Command Refresh
Inputs
All Banks Command
must
be stable
for 100us
Document : 1G5-0099
2nd Auto
Refresh
Command
Rev.1
Mode
Command
Register
Set Command
Page 36
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Clock Suspension During Burst Read (Using CKE) (1 of 2)
Burst Length = 4, CAS Latency = 2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
CKE
CS
RAS
CAS
WE
BS
A10
RAa
ADD
RAa
CAa
DQM
DQ
t
HZ
Hi-Z
QAa0
Activate
Command
Bank A
Document : 1G5-0099
Read
Command
Bank A
QAa1
Clock
Suspended
1 Cycle
QAa2
QAa3
Clock
Suspended
2 Cycle
Rev.1
Clock
Suspended
3 Cycle
Page 37
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Clock Suspension During Burst Read (Using CKE) (2 of 2)
Burst Length = 4, CAS Latency = 3
T0 T1 T2 T3 T4 T5 T6 T7
CLK
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK3
CKE
CS
RAS
CAS
WE
BS
A10
RAa
ADD
RAa
CAa
DQM
t
HZ
DQ
Hi-Z
QAa0
Activate
Command
Bank A
QAa1
QAa3
Read
Command
Bank A
Clock
Suspended
1 Cycle
Document : 1G5-0099
QAa2
Clock
Suspended
2 Cycle
Rev.1
Clock
Suspended
3 Cycle
Page 38
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Clock Suspension During burst Write (Using CKE) (1 of 2)
Burst Length = 4, CAS Latency = 2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
CKE
CS
RAS
CAS
WE
BS
A10
RAa
ADD
RAa
CAa
DQM
DQ
Hi-Z
DAa0
Activate
Command
Bank A
Document : 1G5-0099
DAa1
Clock
Suspended
Write 1 Cycle
Command
Bank A
DAa2
Clock
Suspended
2 Cycle
DAa3
Clock
Suspended
3 Cycle
Rev.1
Page 39
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Clock suspension during Burst write (Using CKE) (2 of 2)
Burst Length = 4, CAS Latency = 3
T0 T1 T2 T3 T4 T5 T6 T7
CLK
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK3
CKE
CS
RAS
CAS
WE
BS
A10
RAa
ADD
RAa
CAa
DQM
t
DQ
Hi-Z
DAa0
Activate
Command
Bank A
DAa1
DAa3
Write
Command
Bank A
Clock
Clock
Suspended Suspended
1 Cycle
1 Cycle
Document : 1G5-0099
DAa2
Clock
Suspended
1 Cycle
Rev.1
Page 40
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Power Down Mode and Clock Mask
Burst Length = 4, CAS Latency = 2
CLK can be Stopped *
T0 T1 T2 T3 T4 T5 T6 T7
CLK
t
CK2
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CKH
t
CKS
t
CKS
CKE
VALID
CS
RAS
CAS
WE
BS
A10
RAa
ADD
RAa
CAa
DQM
DQ
t
HZ
Hi-Z
QAa0 QAa1
Activate
Command
Bank A
ACTIVE
STANDBY
Power Down
Mode Entry
Document : 1G5-0099
QAa2
Precharge
Command
Read
Command
Bank A
Power Down
Mode Exit
QAa3
Clock Mask
Start
Rev.1
Clock Mask
End
Power Down
Mode Entry
Precharge
Standby
Power
Down
Mode
Exit
Command
Page 41
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Auto Refresh (CBR)
Burst Length = 4, CAS Latency = 2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK2
CKE
CS
RAS
CAS
WE
BS
A10
RAa
ADD
RAa
tRP
tRC
CAa
tRC
DQM
DQ
Hi-Z
Q0
Precharge CBR Refresh
Command
Command
All Banks
Document : 1G5-0099
CBR Refresh
Command
Rev.1
Activate
Read
Command Command
Page 42
Q1
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Self Refresh (Entry and Exit)
CLK can be Stopped *
T0 T1 T2 T3 T4 T5 T6 T7
CLK
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
SRX
t
SRX
t
CKS
t
CKS
CKE
CS
RAS
CAS
WE
BS
A10
ADD
t
RC
t
RC
DQM
DQ
Hi-Z
All Banks
must be idle
Document : 1G5-0099
Self refresh
Entry
Self Refresh
Exit
Self Refresh
Exit
Self Refresh
Exit
Rev.1
Activate
Command
Page 43
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Random Column Read (Page Within same Bank)(1 of 2)
Burst Length = 4, CAS Latency = 2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
CKE
CS
RAS
CAS
WE
BS
A10
RAa
ADD
RAa
RAd
RAa
CAa
CAb
CAc
RAd
CAd
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QAb0 QAb1 QAc0 QAc1 QAc2 QAc3
Precharge
Command
Bank A
Document : 1G5-0099
Read
Command
Bank A
Read
Read
Command Command
Bank A
Bank A
Rev.1
QAd0 QAd1 QAd2 QAd3
Precharge Activate
Read
Command Command Command
Bank A
Bank A
Bank A
Page 44
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Random Column Read (Page Within same Bank)(2 of 2)
Burst Length = 4, CAS Latency = 3
T0 T1 T2 T3 T4 T5 T6 T7
CLK
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK3
CKE
CS
RAS
CAS
WE
BS
A10
RAa
ADD
RAa
RAd
CAa
CAb
CAc
RAd
CAd
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QAb0 QAb1 QAc0 QAc1 QAc2 QAc3
Activate
Command
Bank A
Document : 1G5-0099
Read
Command
Bank A
Read
Read
Command Command
Bank A
Bank A
Rev.1
Precharge
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Page 45
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Random Column Write (Page Within same Bank) (1 of 2)
Burst Length = 4, CAS Latency = 2
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
CS
RAS
CAS
WE
BS
A10
Ra
ADD
Ra
Rd
Cb
Ca
Cc
Rd
Cd
DQM
DQ
Hi-Z
Da0
Activate
Command
Bank B
(Bank D)
Document : 1G5-0099
Da1
Write
Command
Bank B
(Bank D)
Da2
Da3
Db0
Db1
Dc0
Dc1
Dc2
Write
Write
Command Command
Bank
B
Bank B
(Bank D) (Bank D)
Rev.1
Dc3
Dd0
Dd1
Dd2
Dd3
Precharge Activate
Write
Command Command Command
Bank B
Bank B
Bank B
(Bank D)
(Bank D) (Bank D)
Page 46
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Random Column Write (Page Within same Bank) (2 of 2)
Burst Length = 4, CAS Latency = 3
T0 T1 T2 T3 T4 T5 T6 T7
CLK
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK3
CKE
CS
RAS
CAS
WE
BS
A10
Ra
ADD
Ra
Rd
Cb
Ca
Cc
Cd
Rd
DQM
DQ
Hi-Z
Da0
Activate
Command
Bank B
(Bank D)
Document : 1G5-0099
Da1
Write
Command
Bank B
(Bank D)
Da2
Da3
Db0
Db1
Dc0
Dc1
Write
Write
Command Command
Bank B
Bank B
(Bank D) (Bank D)
Rev.1
Dc2
Dd0
Dc3
Precharge
Command
Bank B
(Bank D)
Activate
Command
Bank B
(Bank D)
Dd1
Write
Command
Bank B
(Bank D)
Page 47
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Random Row Read (Interleaving Banks) (1 of 2)
Burst Length = 8, CAS Latency = 2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
CKE
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
High
CS
RAS
CAS
WE
BS
A10
ADD
t
RCD
t
AC2
t
RP
DQM
DQ
Hi-Z
Activate
Command
Bank B
(Bank D)
QBb0 QBb1
QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7
Read
Command
Bank B
(Bank D)
Activate
Read
Command
Command
Bank A
Bank A
Active
Command
Bank B
(Bank D)
Read
Command
Bank B
(Bank D)
Precharge
Command
Bank B
(Bank D)
Document : 1G5-0099
Rev.1
Page 48
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Random Row Read (Interleaving Banks) (2 of 2)
Burst Length = 8, CAS Latency = 3
T0 T1 T2 T3 T4 T5 T6 T7
CLK
CKE
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK3
High
CS
RAS
CAS
WE
BS
A10
ADD
t
t
RCD
t
AC3
RP
DQM
DQ
Hi-Z
QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QBb0
Activate
Command
Bank B
(Bank D)
Document : 1G5-0099
Read
Command
Bank B
(Bank D)
Activate
Command
Bank A
Read
Command
Bank A
Rev.1
Precharge
Command
Bank B
(Bank D)
Activate
Command
Bank B
(Bank D)
Read
Precharge
Command Command
Bank B
Bank A
(Bank D)
Page 49
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Random Row Write (Interleaving Banks) (1 of 2)
Burst Length = 8, CAS Latency = 2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
CKE
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
High
CS
RAS
CAS
WE
BS
A10
ADD
t
RCD
DQM
DQ
Hi-Z
Activate
Command
Bank A
t
DPL
t
RP
t
DPL
QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QAb0 QAb1 QAb2 QAb3 QAb4
Write
Command
Bank A
Document : 1G5-0099
Activate
Command
Bank B
(Bank D)
Precharge Active
Command Command
Bank A
Bank A
Write
Command
Bank B
(Bank D)
Rev.1
Write
Command
Bank A
Precharge
Command
Bank B
(Bank D)
Page 50
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Random Row Write (Interleaving Banks) (2 of 2)
Burst Length = 8, CAS Latency = 3
T0 T1 T2 T3 T4 T5 T6 T7
CLK
CKE
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK3
High
CS
RAS
CAS
WE
BS
A10
ADD
RBa
t
RCD
DQM
DQ
Hi-Z
Activate
Command
Bank A
Document : 1G5-0099
t
DPL
t
DPL
t
RP
QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBb7 QAb0 QAb1 QAb2 QAb3
Write
Command
Bank A
Activate
Command
Bank B
(Bank D)
Write
Command
Bank B
(Bank D)
Rev.1
Precharge
Command
Bank A
Activate
Command
Bank A
Precharge
Write
Command Command
Bank B
Bank A
(Bank D)
Page 51
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Read and Write Cycle (1 of 2)
Burst Length = 4, CAS Latency = 2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
CKE
CS
RAS
CAS
WE
BS
A10
RAa
ADD
RAa
CAb
CAa
CAc
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3
Write
Activate
Command Command
Bank A
Bank A
Document : 1G5-0099
DAb0 DAb1
Write
Command
Bank A
DAb3
The Write Data
is Masked with a
Zero Clock
latency
Rev.1
QAc0 QAc1
Read
Command
Bank A
QAc3
The Read Data
is Masked with
Two Clocks
Latency
Page 52
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Read and Write Cycle (2 of 2)
Burst Length = 4, CAS Latency = 3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK3
CKE
CS
RAS
CAS
WE
BS
A10
RAa
ADD
RAa
CAa
CAb
CAc
DQM
DQ
Hi-Z
DAb0 DAb1
QAa0 QAa1 QAa2 QAa3
Activate
Command
Bank A
Read
Command
Bank A
DAb3
Write
The Write Data Read
Command is Masked with a Command
Bank A
Bank A
Zero Clock
latency
Document : 1G5-0099
Rev.1
QAc0 QAc1
QAc3
The Read Data
is Masked with
Two Clock
Latency
Page 53
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Interleaved Column Read Cycle (1 of 2)
Burst Length = 4, CAS Latency = 2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
CS
RAS
CAS
WE
BS
A10
Ra
ADD
Ra
Cb
t
DQM
DQ
Ra
RCD
Ra
Ca
Cb
Cc
Cb
Cd
t
AC2
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBb0 QBb1 QBc0 QBc1 QAb0 QAb1 QBd0 QBd1 QBd2 QBd3
Activate
Command
Bank A
Read
Read
Activate
Read
Read
Read
Command Command Command Command Command Command
Bank A
Bank A
Bank B
Bank B
Bank B
Bank B
(Bank D) (Bank D) (Bank D) (Bank D)
Precharge
Command
Bank A
Read
Command
Bank B
(Bank D)
Document : 1G5-0099
Rev.1
Precharge
Command
Bank B
(Bank D)
Page 54
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Interleaved Column Read Cycle (2 of 2)
Burst Length = 4, CAS Latency = 3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK3
CKE
CS
RAS
CAS
WE
BS
A10
Ra
ADD
Ra
DQM
DQ
Ra
Ca
Ca
Ra
t
RCD
t
RRD
Cb
Cc
Cb
t
AC3
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBb0 QBb1 QBc0 QBc1 QAb0 QAb1 QAb2 QAb3
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
(Bank D)
Document : 1G5-0099
Read
Read
Read
Read
Precharge Precharge
Command Command Command Command Command Command
Bank A
Bank B
Bank B Bank B
Bank B
Bank A
(Bank D) (Bank D) (Bank D)
(Bank D)
Rev.1
Page 55
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Interleaved Column Write Cycle (1 of 2)
Burst Length = 4, CAS Latency = 2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
CS
RAS
CAS
WE
BS
A10
Ra
ADD
Ra
Ra
Ca
Ra
Ca
Cb
Cc
Cb
t
RCD
Cb
t
RP
t
DPL
DQM
t
DQ
RRD
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBb0 QBb1 QBc0 QBc1 QAb0 QAb1 QBd0 QBd1 QBd2 QBd3
Activate
Write
Write
Write
Write
Write
Activate
Command Command Command Command Command Command Command
Bank
B
Bank
B
Bank A
Bank
A
Bank
B
Bank B
Bank A
(Bank D) (Bank D) (Bank D)
(Bank D)
Document : 1G5-0099
Rev.1
Precharge
Command
Bank A
Write
Command
Bank B
(Bank D)
Precharge
Command
Bank B
(Bank D)
Page 56
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Interleaved Column Write Cycle (2 of 2)
Burst Length = 4, CAS Latency = 3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK3
CKE
CS
RAS
CAS
WE
BS
A10
Ra
ADD
Ra
Ra
Ca
Ra
Ca
Cb
Cc
Cb
t
RCD
Cd
t
DPL
t
DPL
DQM
t
DQ
t
RP
RRD
Hi-Z
DAa0 DAa1 DAa2 DAa3 DBa0 DBa1 DBb0 DBb1 DBc0 DBc1 DAb0 DAb1 DAd0 QAd1 QAd2 QAd3
Activate
Command
Bank A
Write
Command
Bank A
Activate
Command
Bank B
(Bank D)
Document : 1G5-0099
Write
Write
Write
Write
Command Command Command Command
Bank A
Bank B
Bank B Bank B
(Bank D) (Bank D) (Bank D)
Precharge
Command
Bank A
Precharge
Command
Bank B
(Bank D)
Write
Command
Bank B
(Bank D)
Rev.1
Page 57
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Auto Precharge after Read Burst (1 of 2)
Burst Length = 4, CAS Latency = 2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK2
High
Start Auto Precharge
Bank A
Start Auto Precharge
Bank B (Bank D)
Start Auto Precharge
Bank B (Bank D)
CS
RAS
CAS
WE
BS
A10
Ra
ADD
Ra
Ra
Ca
Ra
Rb
Ca
Cb
Rb
Rc
Cb
Rc
Cc
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QAc2
Activate
Read
Activate
Read with
Command Command Command Auto Precharge
Command
Bank B
Bank A
Bank A
(Bank D)
Bank B
(Bank D)
Document : 1G5-0099
Read with
Auto Precharge
Command
Bank A
Rev.1
Activate
Command
Bank B
(Bank D)
Activate
Command
Bank A
Read with
Auto Precharge
Command
Bank B
(Bank D)
Read with
Auto Precharge
Command
Bank A
Page 58
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Auto Precharge after Read Burst (2 of 2)
Burst Length = 4, CAS Latency = 3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK3
High
Start Auto Precharge
Bank B (Bank D)
Start Auto Precharge Start Auto Precharge
Bank B (Bank D)
Bank A
CS
RAS
CAS
WE
BS
A10
RAa
ADD
RAa
RBa
CAa
RBa
RBb
CBa
CAb
RBb
CBb
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
(Bank D))
Document : 1G5-0099
Read with
Auto Precharge
Command
Bank B
(Bank D)
Read with
Auto Precharge
Command
Bank A
Rev.1
Activate
Command
Bank B
(Bank D)
QBb0 QBb1 QBb2
Read with
Auto Precharge
Command
Bank B (Bank D)
Page 59
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Auto Precharge after Write Burst (1 of 2)
Burst Length = 4, CAS Latency = 2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK2
High
Start Auto Precharge
Bank B
Start Auto Precharge
Bank A
Start Auto Precharge
Bank B
CS
RAS
CAS
WE
BS
A10
RAa
ADD
RAa
RBa
CAa
RBa
RBb
CBa
CAb
RBb
RAc
CBb
RAc
CAc
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QAc2 QAc3
Activate
Write
Write with
Activate
Command Command Command Auto Precharge
Command
Bank A
Bank B
Bank A
Bank B
(Bank D)
(Bank D)
Document : 1G5-0099
Activate
Write with
Activate
Command
Auto Precharge Command
Bank A
Command
Bank B
Write with
Bank A
(Bank D) Write with
Auto Precharge
Auto Precharge
Bank A
Command
Bank B
(Bank D)
Rev.1
Start Auto
Precharge
Bank A
Page 60
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Auto Precharge after Write Burst (2 of 2)
Burst Length = 4, CAS Latency = 3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK3
High
Start Auto Precharge Start Auto Precharge
Bank A
Bank B (Bank D)
Start Auto Precharge
Bank B (Bank D)
CS
RAS
CAS
WE
BS
A10
Ra
ADD
Ra
Ra
Ca
Ra
Rb
Ca
Rb
Cb
Cb
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3
Activate
Command
Bank A
Document : 1G5-0099
Activate
Command
Bank B
Write (Bank D)
Command
Bank A
Write with
Auto Precharge
Command
Bank B
(Bank D)
Write with
Auto Precharge
Command
Bank A
Rev.1
Activate
Command
Bank B
(Bank D)
QBb0 QBb1 QBb2 QBb3
Write with
Auto precharge
Command
Bank B
(Bank D)
Page 61
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Full Page Read Cycle (1 of 2)
Burst Length = Full Page, CAS Latency = 2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
CKE
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
High
CS
RAS
CAS
WE
BS
A10
Ra
ADD
Ra
Rb
Ra
Ca
Ca
Ra
Rb
t
RP
DQM
DQ
Hi-Z
QAa
Activate
Command
Bank A
Read
Command
Bank A
Document : 1G5-0099
QAa+1 QAa+2 QAa-2 QAa-1
Activate
Command
Bank B
(Bank D)
QAa
QAa+1 QBa
Read
Command
Bank B
(Bank D)
The burst counter wraps
from the highest order
page address back to zero
during this time interval
QBa+1 QBa+2 QBa+3 QBa+4 QBa+51QBa+6
Full page burst operation does not
terminate when the burst length is
satisfied; the burst counter
increments and continues bursting
beginning with the starting address
Rev.1
Precharge
Command
Bank B
(Bank D)
Burst Stop
Command
Activate
Command
Bank B
(Bank D)
Page 62
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Full Page Read Cycle (2 of 2)
Burst Length = Full Page, CAS Latency = 3
T0 T1 T2 T3 T4 T5 T6 T7
CLK
CKE
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK3
High
CS
RAS
CAS
WE
BS
A10
Ra
ADD
Ra
Rb
Ra
Ca
Ca
Ra
Rb
t
RP
DQM
DQ
Hi-Z
QAa
Activate
Command
Bank A
Document : 1G5-0099
Read
Command
Bank A
Activate
Command
Bank B
(Bank D)
QAa+1 QAa+2 QAa-2 QAa-1
QAa
QAa+1 QBa0
QBa+1 QBa+2 QBa+3 QBa+4 QBa+5
Full page burst operation
Read
does not teminate when
Command
the burst length is satisfied;
Bank B
the burst counter increments
(Bank D) and continues bursting
The burst counter wraps beginning with the starting
from the highest order
address
page address back to zero
during this time interval
Rev.1
Precharge
Command
Bank B
(Bank D)
Burst Stop
Command
Activate
Command
Bank B
(Bank D)
Page 63
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Full Page Write Cycle (1 of 2)
Burst Length = Full Page, CAS Latency = 2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
CKE
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
High
CS
RAS
CAS
WE
A11(BS)
A10
Ra
A0~A9
Ra
Rb
Ra
Ca
Rb
Ca
Ra
DDM
DQ
t
BDL
Hi-Z
QAa
Activate
Command
Bank A
QAa+1 QAa+2 QAa+3 QAa-1
Write
Command
Bank A
QAa
QAa+1
Activate
Command
Bank B
(Bank D)
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Document : 1G5-0099
QBa
QBa+1 QBa+2 DQBa+3QBa+4 QBa+5 QBa+6
Write
Data is ignored
Command
Precharge
Bank B
Command
(Bank D)
Bank B
Full page burst operation
(Bank D)
does not terminate when
Burst Stop
the burst length is satisfied;
Command
the burst counter increments
and continues bursting
beginning with the starting
address
Rev.1
Activate
Command
Bank B
(Bank D)
Page 64
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Full Page Write Cycle (2 of 2)
Burst Length = Full Page, CAS Latency = 3
T0 T1 T2 T3 T4 T5 T6 T7
CLK
CKE
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK3
High
CS
RAS
CAS
WE
A11(BS)
A10
Ra
A0~A9
Ra
Rb
Ra
Ca
Rb
Ca
Ra
DDM
DQ
tBDL
Data is ignored.
Hi-Z
DAa
Activate
Command
Bank A
Document : 1G5-0099
DAa+1 DAa+2 DAa+3 DAa-1
Write
Command
Bank A
DAa
DAa+1
Activate
Command
Bank B
(Bank D)
The burst counter wraps
from the highest order
page address back to zero
during this time interval
DBa
DBa+1 DBa+2 DBa+3 DBa+4 DBa+5
Write
Command
Bank B
(Bank D)
Full page burst operation
does not terminate when
the burst length is satisfied;
the burst counter increments
and continues bursting
beginning with the starting
address
Rev.1
Precharge
Command
Bank B
(Bank D)
Burst Stop
Command
Activate
Command
Bank B
(Bank D)
Page 65
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Byte Write Operation
Burst Length = 4, CAS Latency = 2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
CKE
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
High
CS
RAS
CAS
WE
BS
A10
RAa
ADD
RAa
CAa
CAz
CAb
DQM
DQ
DQ0 ~ DQ7
DQ8 ~ DQ15
Hi-Z
Hi-Z
Activate
Command
Bank A
Read
Command
Bank A
Document : 1G5-0099
Upper Byte
is masked
Lower Byte
is masked
Write
Command
Bank A
Read
Write Upper
Command
is masked
Bank A
Rev.1
Lower Byte
is masked
Lower Byte
is masked
Page 66
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Burst Read and Single Write Operation
Burst Length = 4, CAS Latency = 2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
CKE
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
High
CS
RAS
CAS
WE
BS
A10
RAa
ADD
RAa
CAa
CAb
CAc
CAd
CAe
DQM
DQ
DQ0 ~ DQ7
DQ8 ~ DQ15
Hi-Z
Hi-Z
Activate
Command
Bank A
Read
Command
Bank A
Document : 1G5-0099
Read
Single Write Single Write
Command
Command
Command
Bank A
Bank A
Bank A
Rev.1
Lower Byte
is masked
Upper Byte
is masked
Single Write
Command
Bank A
Lower Byte
is masked
Page 67
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Full Page Random Column Read
Burst Length = Full Page, CAS Latency = 2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
CKE
CS
RAS
CAS
WE
BS
A10
Ra
Ra
ADD
Ra
Ra
Rb
Ca
Ca
Cb
Cc
Cb
Cc
Rb
t
RP
DQM
DQ
Hi-Z
QAa0 QBa0
Activate
Command
Bank A
Document : 1G5-0099
QAb0
QAb1
Read
Read
Activate
Command
Command
Command
Bank B
Bank B
Bank B
(Bank D)
(Bank D)
(Bank D)
Read
Read
Command
Command
Bank A
Bank A
QBb0
QBb1
Read
Command
Bank A
QAc0
QAc1
Read
Command
Bank B
(Bank D)
QAc2
QBc0
QBc1
QBc2
Precharge
Command Bank B (Bank D)
(Precharge Termination)
Activate
Command
Bank B
(Bank D)
Rev.1
Page 68
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Full Page Random Column Write
Burst Length = Full Page, CAS Latency = 2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
CKE
CS
RAS
CAS
WE
BS
A10
Ra
Ra
ADD
Ra
Ra
Rb
Ca
Ca
Cb
Cc
Cb
Cc
Rb
t
RP
DQM
DQ
Hi-Z
QAa0
Activate
Command
Bank A
Document : 1G5-0099
QBa0
QAb0
QAb1
Write
Activate
Command
Command
Bank B
Bank B
(Bank D)
(Bank D)
Write
Write
Command
Command
Bank A
Bank A
QBb0
QBb1
Write
Command
Bank B
(Bank D)
QAc0
QAc1
Write
Command
Bank A
Rev.1
QAc2
QBc0
QBc1
QBc2
Write
Precharge
Command Command Bank B (Bank D)
Bank B
(Precharge Termination)
(Bank D)
Activate
Command
Write Data
Bank B
is masked
(Bank D)
Page 69
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Precharge Termination of a Burst (1 of 2)
Burst Length = 4,8 or Full Page, CAS Latency = 2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
CKE
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
High
CS
RAS
CAS
WE
BS
A10
RAa
ADD
RAa
RAb
CAa
RAb
t
DPL
t
RAc
CAb
RAc
t
RP
CAc
RP
DQM
DQ
Hi-Z
QAa0 QAa1
Activate
Command
Bank A
Write
Command
Bank A
QAa2
QAa3
Precharge
Command
Bank A
QAb0
Activate
Command
Bank A
Read
Command
Bank A
Precharge Termination
of a Write Burst.Write
data is masked.
Document : 1G5-0099
QAc1
QAc2
Precharge
Command
Bank A
Activate
Command
Bank A
QAb0
Read
Command
Bank A
QAc1
QAc2
Precharge
Command
Bank A
Precharge Termination
of a Read Burst.
Rev.1
Page 70
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Precharge Termination of a Burst (2 of 2)
Burst Length=4,8 or Full Page, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7
CLK
CKE
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK3
High
CS
RAS
CAS
WE
BS
A10
RAa
ADD
RAa
RAb
CAa
RAb
t DPL
t
DQM
DQ
t
RAc
CAb
t
RP
RAc
t
RAS
RP
RCD
Hi-Z
DAa0
Activate
Command
Bank A
Write
Command
Bank A
Precharge
Command
Bank A
Write Data
is masked
Document : 1G5-0099
QAb0
DAa1
Activate
Command
Bank A
Read
Command
Bank A
Precharge Termination
of a Write Burst.
QAb1
QAb2
Precharge
Command
Bank A
QAb3
Activate
Command
Bank A
Precharge Termination
of a Read Burst.
Rev.1
Page 71
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Ordering information
Part Number
Cycle time
Package
VG36643241BT-7
7ns
400mil
VG36643241BT-8
8ns
44-Pin
VG36643241BT-10
10ns
Plastic TSOP
VG36643211BT-8
• VG
• VIS Memory Product
• 36
• Technology/Design Rule
• 64
• 64Mb
• 32
•1
• Device Configuration, 32 : x32
• Device Internal Banks, 1 : 2banks, 4 : 4banks
•1
• Interface Type, 1 : LVTTL, 2 : SSTL-3
•B
• Mask/Design Version
•T
• Package Type, T : TSOP
•8
• Cycle time, 10 : 10ns, 8 : 8ns, 7 : 7ns
Packaging Information
• 400mil, 86-Pin Plastic TSOP
DIM
INCHES
MILLIMETERS
RAD R1
MIN.
NOM.
MAX.
MIN.
NOM.
MAX.
A
---
---
1.20
---
---
0.047
A1
0.05
---
0.15
0.002
---
0.006
A2
0.95
1.00
1.05
0.037
0.039
0.041
b
0.17
---
0.27
0.007
b1
0.17
0.20
0.23
0.007
c
0.12
---
0.21
(0.005)
---
0.008
--0.008
0.12
0.125
0.16
(0.005)
0.005
0.006
22.09
22.22
22.35
0.870
0.875
0.880
A1
0¢X~8¢X
DETAIL A
E1
b
11.56
11.76
11.96
0.455
0.463
0.471
E1
10.03
10.16
10.29
0.395
0.400
0.405
L
0.40
0.50
0.60
0.016
0.020
0.024
R
0.12
---
0.25
0.005
---
0.010
R1
0.12
---
---
0.005
---
---
0.61 REF.
B
L
0.020 BASIC
E
ZD
b1
1
c1
43
D
SECTION B-B
c
BASE METAL
0.024 REF.
WITH PLATING
ZD
DETAIL A
NOTE:
1. CONTROLLING DIMENSION : MILLIMETERS
2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION.
A
MOLD PROTRUSION SHALL NOT EXCEED 0.15mm(0.006") PER SIDE.
DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION.
INTERLEAD PROTRUSION SHALL NOT EXCEED 0.25mm(0.01") PER SIDE.
e
b
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSIONS/INTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD TO
BE WIDER THAN THE MAX b DIMENSION BY MORE THAN 0.13mm.
DAMBAR INTRUSION SHALL NOT CAUSE THE LEAD TO BE NARROWER
E
SEATING PLANE
0.100(0.004")
THAN THE MIN b DIMENSION BY MORE THAN 0.07mm.
Document : 1G5-0099
c
B
0.009
D
0.50 BASIC
A2
44
0.011
c1
e
RAD R
86
Rev.1
Page 72