Preliminary W27C4096 256K × 16 ELECTRICALLY ERASABLE EPROM GENERAL DESCRIPTION The W27C4096 is a high speed, low power Electrically Erasable and Programmable Read Only Memory organized as 262144 × 16 bits that operates on a single 5 volt power supply. The W27C4096 provides an electrical chip erase function. FEATURES • High speed access time: • • • • • +14V erase/+12V programming voltage • Fully static operation • All inputs and outputs directly TTL/CMOS 120/150 nS (max.) Read operating current: 30 mA (max.) Erase/Programming operating current 30 mA (max.) Standby current: 100 µA (max.) Single 5V power supply compatible • Three-state outputs • Available packages: 40-pin 600 mil DIP, TSOP and 44-pin PLCC PIN CONFIGURATIONS VPP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CE Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 GND Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 OE BLOCK DIAGRAM VDD A17 A16 A15 A14 A13 A12 A11 A10 A9 GND A8 A7 A6 A5 A4 A3 A2 A1 A0 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 40-pin DIP Q0 CE OUTPUT BUFFER CONTROL . . Q15 OE A0 . . CORE ARRAY DECODER A17 Q 1 3 Q 1 4 Q 1 5 / C E V p p N C 6 5 4 3 2 1 CE Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 A 1 6 A 1 5 A 1 4 44 43 42 41 40 C C VCC 39 A13 8 38 A12 9 37 A11 Q9 10 36 A10 35 A9 Q12 7 Q11 Q10 Q8 11 GND 12 NC 13 33 NC Q7 14 32 A8 Q6 15 31 A7 Q5 16 30 A6 Q4 17 29 A5 44-pin PLCC 18 Q 3 A9 A10 A11 A12 A13 A14 A15 A16 A17 VCC VPP A 1 7 V 19 Q 2 20 21 Q 1 Q 0 22 / O E 34 23 24 25 N C A 0 A 1 26 27 A 2 A 3 28 GND VPP GND PIN DESCRIPTION SYMBOL A 4 40 1 2 3 39 38 4 5 37 36 35 34 6 7 8 9 10 11 12 13 14 15 16 17 40-pin TSOP 33 32 31 30 29 28 27 26 25 18 24 23 19 22 20 21 GND A8 A7 A6 A5 A4 A3 A2 A1 A0 OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 A0−A17 Address Inputs Q0−Q15 Data Inputs/Outputs CE Chip Enable OE VPP Output Enable VCC Power Supply GND Ground NC -1- DESCRIPTION Program/Erase Supply Voltage No Connection Publication Release Date: March 1999 Revision A1 Preliminary W27C4096 FUNCTIONAL DESCRIPTION Read Mode Like conventional UVEPROMs, the W27C4096 has two control functions, both of which produce data at the outputs. CE is for power control and chip select. OE controls the output buffer to gate data to the output pins. When addresses are stable, the address access time (TACC) is equal to the delay from CE to output (TCE), and data are available at the outputs TOE after the falling edge of OE, if TACC and TCE timings are met. Erase Mode The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs, which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an hour), the W27C4096 uses electrical erasure. Generally, the chip can be erased within 100 mS by using an EPROM writer with a special erase algorithm. Erase mode is entered when VPP is raised to VPE (14V), VCC = VCE (5V), CE low, OE high, A9 = VPE (14V), A0 low, and all other address pins low and data input pins high. Erase Verify Mode After an erase operation, all of the words in the chip must be verified to check whether they have been successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase margin. This mode will be entered after the erase operation if VPP = VPE (14V), CE high, and OE low. Program Mode Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only way to change cell data from "1" to "0." The program mode is entered when VPP is raised to VPP (12V), VCC = VCP (5V), CE low, OE high, the address pins equal the desired address, and the input pins equal the desired inputs. Program Verify Mode All of the words in the chip must be verified to check whether they have been successfully programmed with the desired data or not. Hence, after each word is programmed, a program verify operation should be performed. The program verify mode automatically ensures a substantial program margin. This mode will be entered after the program operation if VPP = VPP (12V), CE high, OE low and VCC = VCP (5V). Erase/Program Inhibit Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different data. When CE high , VPP = VPP/VPE (12V/14V), and VCC = 5V, erasing or programming of nontarget chips is inhibited, so that except for the CE and VPP, and VCC, the W27C4096 may have common inputs. -2- Preliminary W27C4096 Standby Mode The standby mode significantly reduces VCC current. This mode is entered when CE high , VPP = 5V, and VCC = 5V. In standby mode, all outputs are in a high impedance state, independent of OE. Two-line Output Control Since EPROMs are often used in large memory arrays, the W27C4096 provides two control inputs for multiple memory connections. Two-line control provides for lowest possible memory power dissipation and ensures that data bus contention will not occur. System Considerations EPROM power switching characteristics require careful device decoupling. System designers are interested in three supply current issues: standby current levels (ISB), active current levels (ICC), and transient current peaks produced by the falling and rising edges of CE. Transient current magnitudes depend on the device output's capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 µ F ceramic capacitor connected between its VCC and GND. This high frequency, low inherentinductance capacitor should be placed as close as possible to the device. Additionally, for every eight devices, a 4.7 µF electrolytic capacitor should be placed at the array's power supply connection between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances. TABLE OF OPERATING MODES (VPP = 12V, VPE = 14V, VHH = 12V, VCP = 5V, X = VIH or VIL) MODE PINS CE OE A0 A9 VCC VPP Read VIL VIL X X VCC VCC DOUT Output Disable VIL VIH X X VCC VCC High Z Standby (TTL) VIH X X X VCC VCC High Z VCC ±0.3V X X X VCC VCC High Z Program VIL VIH X X VCP VPP DIN Program Verify VIH VIL X X VCP VPP DOUT Program Inhibit VIH X X X VCP VPP High Z Erase VIL VIH VIL VPE VCE VPE DIH Erase Verify VIH VIL X X VCE VPE DOUT Erase Inhibit VIH X X X VCE VPE High Z Product Identifier-manufacturer VIL VIL VIL VHH VCC VCC 00DA (Hex) Product Identifier-device VIL VIL VIH VHH VCC VCC 000D (Hex) Standby (CMOS) -3- OUTPUTS Publication Release Date: March 1999 Revision A1 Preliminary W27C4096 DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER RATING UNIT Ambient Temperature with Power Applied -55 to +125 °C Storage Temperature -65 to +125 °C -0.5 to VCC +0.5 V Voltage on VPP Pin with Respect to Ground -0.5 to +14.5 V Voltage on A9 Pin with Respect to Ground -0.5 to +14.5 V Voltage on VCC Pin with Respect to Ground -0.5 to +7 V Voltage on all pins with Respect to Ground Except VPP, A9 and VCC pins Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. DC Erase Characteristics (TA = 25° C ±5° C, VCC = 5.0V ± 5%, VHH = 14V) PARAMETER SYM. CONDITIONS LIMITS UNIT MIN. TYP. MAX. -10 - 10 µA Input Load Current ILI VIN = VIL or VIH VCC Erase Current ICP CE = VIL - - 30 mA VPP Erase Current IPP CE = VIL - - 30 mA Input Low Voltage VIL - -0.3 - 0.8 V Input High Voltage VIH - 2.4 - 5.5 V Output Low Voltage (Verify) VOL IOL = 2.1 mA - - 0.45 V Output High Voltage (Verify) VOH IOH = -0.4 mA 2.4 - - - A9 Erase Voltage VID - 13.75 14 14.25 V VPP Erase Voltage VPE - 13.75 14 14.25 V VCC Supply Voltage (Erase) VCE - 4.5 5.0 5.5 V Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. CAPACITANCE (VCC = 5V, TA = 25° C, f = 1 MHz) PARAMETER SYMBOL CONDITIONS Input Capacitance CIN Output Capacitance COUT -4- MAX. UNIT VIN = 0V 6 pF VOUT = 0V 12 pF Preliminary W27C4096 AC CHARACTERISTICS AC Test Conditions PARAMETER CONDITIONS Input Pulse Levels 0.45V to 2.4V Input Rise and Fall Times 10 nS Input and Output Timing Reference Level 0.8V/2.0V Output Load CL = 100 pF, IOH/IOL = -0.4 mA/2.1 mA AC Test Load and Waveform +1.3V (IN914) 3.3K ohm DOUT 100 pF (Including Jig and Scope) Input Output Test Points 2.4V 0.45V Test Points 2.0V 2.0V 0.8V 0.8V -5- Publication Release Date: March 1999 Revision A1 Preliminary W27C4096 READ OPERATION DC CHARACTERISTICS (VCC = 5.0V ±5%, TA = 0 to 50° C) PARAMETER SYM. CONDITIONS LIMITS UNIT MIN. TYP. MAX. Input Load Current ILI VIN = 0V to VCC -5 - 5 µA Output Leakage Current ILO VOUT = 0V to VCC -10 - 10 µA VCC Standby Current ISB CE = VIH - - 1.0 mA ISB1 CE = VCC ±0.2V - 5 100 µA VCC Operating Current ICC CE = VIL IOUT = 0 mA, f = 5 MHz - - 30 mA VPP Operating Current IPP VPP = VCC - - 10 µA Input Low Voltage VIL - -0.3 - 0.8 V Input High Voltage VIH - 2.2 - VCC +0.5 V Output Low Voltage VOL IOL = 2.1 mA - - 0.4 V Output High Voltage VOH IOH = -0.4 mA 2.4 - - V VPP Operating Voltage VPP VCC -0.7 - VCC V - READ OPERATION AC CHARACTERISTICS (VCC = 5.0V ±5%, TA = 0 to 50° C) PARAMETER SYM. W27C4096-12 W27C4096-15 MIN. MAX. MIN. MAX. UNIT Read Cycle Time TRC 120 - 150 - nS Chip Enable Access Time TCE - 120 - 150 nS Address Access Time TACC - 120 - 150 nS Output Enable Access Time TOE - 50 - 70 nS OE High to High-Z Output TDF - 30 - 30 nS Output Hold from Address Change TOH 0 - 0 - nS Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. -6- Preliminary W27C4096 DC PROGRAMMING CHARACTERISTICS (VCC = 5.0V ±5%, TA = 25° C ±5° C) PARAMETER SYM. CONDITIONS LIMITS UNIT MIN. TYP. MAX. -10 - 10 µA Input Load Current ILI VIN = VIL or VIH VCC Program Current ICP CE = VIL - - 30 mA VPP Program Current IPP CE = VIL - - 30 mA Input Low Voltage VIL - -0.3 - 0.8 V Input High Voltage VIH - 2.4 - 5.5 V Output Low Voltage (Verify) VOL IOL = 2.1 mA - - 0.45 V Output High Voltage (Verify) VOH IOH = -0.4 mA 2.4 - - V A9 Silicon I.D. Voltage VID - 11.5 12.0 12.5 V VPP Program Voltage VPP - 11.75 12.0 12.25 V VCC Supply Voltage (Program) VCP - 4.5 5.0 5.5 V AC PROGRAMMING/ERASE CHARACTERISTICS (VCC = 5.0V ±5%, TA = 25° C ±5° C) PARAMETER SYM. LIMITS UNIT MIN. TYP. MAX. VPP Setup Time TVPS 2.0 - - µS Address Setup Time TAS 2.0 - - µS Data Setup Time TDS 2.0 - - µS CE Program Pulse Width TPWP 95 100 105 µS CE Erase Pulse Width TPWE 95 100 105 mS Data Hold Time TDH 2.0 - - µS OE Setup Time TOES 2.0 - - µS Data Valid from OE TOEV - - 150 nS OE High to Output High Z TDFP 0 - 130 nS Address Hold Time TAH 0 - - µS Address Hold Time after CE High (Erase) TAHC 2.0 - - µS Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. -7- Publication Release Date: March 1999 Revision A1 Preliminary W27C4096 TIMING WAVEFORMS AC Read Waveform VIH Address Valid Address VIL VIH CE VIL TCE VIH OE TDF VIL TOE TOH T ACC High Z Outputs Valid Output High Z Erase Waveform Read Manufacturer Read Device SID SID A9 = 12.0V A0= VIH Others = V IL VIH Address Chip Erase A9 = 14.0V Others = V IL Address Stable A0 = VIL Others = VIL VIL TACC Data TACC TAS TARC Address Stable Address Stable TACC TDFP DOUT Data All One 000D 00DA Blank Check Read Verify Erase Verify TDS DOUT DOUT TAH TAHC 14.0V 5V 5.0V TVPS VPP VIH CE TCE VIL TOE TOE TPWE TOES TOE VIH OE VIL TOEV -8- Preliminary W27C4096 Timing Waveforms, continued Programming Waveform Program Verify Program Read Verify VIH Address Stable Address Address Stable Address Valid VIL TDFP TAS Data Data In Stable T DS DOUT TACC DOUT DOUT TAH TDH 12.0V VPP 5.0V 5V TVPS VIH CE VIL VIH OE VIL TOE TPWP TOES TOEV -9- Publication Release Date: March 1999 Revision A1 Preliminary W27C4096 SMART PROGRAMMING ALGORITHM Start Address = First Location Vcc = 5V Vpp = 12V X=0 Program One 100 µS Pulse Increment X Yes X = 25? No Fail Verify One Word Verify One Word Pass Increment Address No Fail Pass Last Address? Yes Vcc = 5V Vpp = 5V Compare All Words to Original Data Fail Pass Fail Device Pass Device - 10 - Preliminary W27C4096 SMART ERASE ALGORITHM Start X=0 Vcc = 5V Vpp = 14V A9 = 14V; A0 = V IL Chip Erase 100 mS Pulse Address = First Location Increment X No Erase Verify Fail X = 20? Pass Increment Address No Yes Last Address? Yes Vcc = 5V Vpp = 5V Compare All Words to FFFF (HEX) Fail Pass Pass Device Fail Device - 11 - Publication Release Date: March 1999 Revision A1 Preliminary W27C4096 ORDERING INFORMATION PART NO. ACCESS TIME (nS) POWER SUPPLY CURRENT MAX. (mA) STANDBY VCC CURRENT MAX. (µA) PACKAGE W27C4096-12 120 30 100 600 mil DIP W27C4096T-12 120 30 100 40-pin TSOP W27C4096P-12 120 30 100 44-pin PLCC W27C4096-15 150 30 100 600 mil DIP W27C4096T-15 150 30 100 40-pin TSOP W27C4096P-15 150 30 100 44-pin PLCC Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. - 12 - Preliminary W27C4096 PACKAGE DIMENSIONS 40-pin PDIP Dimension in inches Symbol A A1 A2 B B1 c D E E1 e1 L D 40 21 E1 0.155 0.160 3.81 3.94 4.06 0.016 0.018 0.022 0.41 0.46 0.56 0.048 0.050 0.054 1.22 1.27 1.37 0.008 0.010 0.014 0.20 0.25 0.36 2.055 2.070 52.20 52.58 0.600 0.610 14.99 15.24 15.49 0.540 0.545 0.550 13.72 13.84 13.97 0.090 0.100 0.110 2.29 2.54 2.79 0.120 0.130 0.140 3.05 3.30 3.56 15 0 0.670 16.00 16.51 17.02 0.590 0 c A1 Base Plane Seating Plane L B e1 eA a B1 0.630 0.650 15 0.090 2.29 1. Dimensions D Max & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimensions D & E1 include mold mismatch and . parting line. are determined at the mold 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec. E S A A2 0.25 0.150 Notes: 20 1 5.33 0.210 0.010 a eA S Dimension in mm Min. Nom. Max. Min. Nom. Max. 40-pin TSOP HD Dimension in Inches Symbol D c e E 0.10(0.004) b A θ A2 A1 L L1 Nom. Max. A A1 A2 b c 1 M Min. Y Nom. Max. 0.047 1.20 0.002 0.006 0.05 0.037 0.039 0.15 0.041 0.95 1.00 0.007 0.009 0.011 0.17 0.22 0.27 0.004 0.006 0.008 0.10 0.15 0.20 D 0.72 E HD e L L1 0.390 0.394 0.398 Y θ Dimension in mm Min. 0.724 0.728 18.3 0.780 0.787 0.795 18.4 18.5 9.90 10 10.10 19.8 20.0 0.020 0.50 0.031 0 3 20.2 0.50 0.020 0.024 0.028 0.000 1.05 0.60 0.70 0.8 0.004 0.00 5 0 0.10 3 5 Controlling dimension: Millimeters - 13 - Publication Release Date: March 1999 Revision A1 Preliminary W27C4096 Package Dimensions, continued 44-pin PLCC HD D 6 1 44 Dimension in inches 40 Symbol 7 39 E HE 17 GE 29 18 28 c A A1 A2 b1 b c D E e GD GE HD HE L y Min. Nom. Max. Dimension in mm Min. Nom. Max. 0.185 4.70 0.020 0.51 0.145 0.150 0.155 3.68 3.81 3.94 0.026 0.028 0.032 0.66 0.71 0.81 0.016 0.018 0.022 0.41 0.46 0.56 0.008 0.010 0.014 0.20 0.25 0.36 0.648 0.653 0.658 16.46 16.59 16.71 0.648 0.653 0.658 16.46 16.59 16.71 0.050 BSC 1.27 BSC 0.590 0.610 0.630 14.99 15.49 16.00 0.590 0.610 0.630 14.99 15.49 16.00 0.680 0.690 0.700 17.27 17.53 17.78 0.680 0.690 0.700 17.27 17.53 17.78 0.090 0.100 0.110 2.29 2.54 0.004 Notes: L 1. Dimension D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection spec. A2 A θ e b b1 Seating Plane A1 y GD - 14 - 2.79 0.10 Preliminary W27C4096 VERSION HISTORY VERSION DATE A1 Mar. 1999 PAGE DESCRIPTION Initial Issued Headquarters Winbond Electronics (H.K.) Ltd. No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-7197006 Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 Note: All data and specifications are subject to change without notice. - 15 - Publication Release Date: March 1999 Revision A1