W83194BR-138 200MHZ CLOCK FOR SOLANO CHIPSET 1.0 GENERAL DESCRIPTION The W83194BR-138 is a Clock Synthesizer for Intel 815 Solano chipset. W83194BR-138 provides all clocks required for high-speed RISC or CISC microprocessor and also provides 64 different frequencies of CPU, SDRAM, PCI, 3V66, IOAPIC clocks frequency setting. All clocks are externally selectable with smooth transitions. The W83194BR-138 provides I2C serial bus interface to program the registers to enable or disable each clock outputs and provides 0.25% and 0.5% center type spread spectrum to reduce EMI. The W83194BR-138 provides stepless frequency programming by controlling the VCO freq. and the clock output divisor ratio. Also the skew of CPU, SDRAM and 3V66 clock outputs are programmable. A watch dog timer is quipped and when time out, the RESET# pin will output 4ms pulse signal. The W83194BR-138 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50± 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide better than 0.5V /ns slew rate. 2.0PRODUCT FEATURES • • • • • • • 2 CPU clocks 3 3V66 clocks 9 SDRAM clocks for 2 DIMMs 8 PCI synchronous clocks. Optional single or mixed supply: (VDDR = VDDP=VDDS = VDD48 = VDD3 = 3.3V, VDDA=VDDC=2.5V) Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns Smooth frequency switch with selections from 66.8 to 200MHz I2C 2-Wire serial interface and I2C read back 0.25% or 0.5% center type spread spectrum Programmable registers to enable/stop each output and select modes (mode as Tri-state or Normal ) 48 MHz for USB 24 MHz for super I/O • Packaged in 48-pin SSOP • • • • • -1- Publication Release Date: May 2000 Revision 0.37 W83194BR-138 PRELIMINARY 3.0 PIN CONFIGURATION REF1/*SEL24_48# VDDR Xin Xout VSS VSS 3V66-0 3V66-1 3V66-2 VDD3 VDDP PCICLK0/ FS0* PCICLK1/ FS1& VSS PCICLK2/Mode1* PCICLK3 PCICLK4 VDDP PCICLK5 PCICLK6 VSS PD*#/RESET$ SDCLK* SDATA* 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VddA IOAPIC VDDC CPUCLK0 CPUCLK1 VSS VSS SDRAM 0 SDRAM 1 SDRAM 2 VDDS SDRAM 3 SDRAM 4 SDRAM 5 VSS SDRAM 6 SDRAM 7 SDRAM_F VDDS VSS 24_48MHz/ FS2& 48MHz-1/FS3* 48MHz-0/ FS4* VDD48 *: pull up &: pull down $: open drain ^:1.5X~2X driving strength 4.0 PIN DESCRIPTION IN - Input OUT - Output I/O - Bi-directional Pin # - Active Low * - Internal 250kΩ pull-up -2- Publication Release Date: May 2000 Revision 0.37 W83194BR-138 PRELIMINARY 4.1 Crystal I/O Xin SYMBOL PIN 3 I/O IN Xout 4 OUT FUNCTION Crystal input with internal loading capacitors(36pF) and feedback resistors. Crystal output at 14.318MHz nominally with internal loading capacitors(36pF). 4.2 CPU, SDRAM, PCI, IOAPIC Clock Outputs SYMBOL CPUCLK [0:1] PIN 45,44 I/O OUT PD#/ RESET$ 22 I/OD IOAPIC 47 OUT SDRAM_F, SDRAM[0:7] PCICLK0/ *FS0 31,32,33,35,36 ,37,39,40,41 12 OUT PCICLK1/ FS1& 13 I/O PCICLK2/ Mode1* 15 I/O 16,17,19,20 7,8,9 OUT OUT PCICLK [ 3:6 ] 3V66 [0:2] I/O -3- FUNCTION Low skew (< 250ps) clock outputs for host frequencies such as CPU and Chipset. If Mode1*=1, Power Down mode when driven low. If Mode1*=0, 4ms pulse RESET# (open drain) when Watch dog timer time out Clock outputs synchronous with PCI clock and powered by VddA. SDRAM clock outputs. 3.3V 33MHz PCI clock during normal operation. Latched input for FS0 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks(Default=1). Low skew (< 250ps) PCI clock outputs. Latched input for FS1 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks(Default=0). Low skew (< 250ps) PCI clock outputs. Latched input for Mode1* pin at initial power up for the output PD#/RESET# output selection. Low skew (< 250ps) PCI clock outputs. 3.3V output clocks for the chipset. Publication Release Date: May 2000 Revision 0.37 W83194BR-138 PRELIMINARY 4.3 I2C Control Interface SYMBOL PIN I/O FUNCTION 2 *SDATA 24 I/O Serial data of I C 2-wire control interface with internal pull-up resistor. *SDCLK 23 IN Serial clock of I2C 2-wire control interface with internal pull-up resistor. 4.4 Fixed Frequency Outputs SYMBOL REF0 / *SEL24_48# PIN I/O 1 I/O FUNCTION 14.318MHz reference clock. This REF output is the stronger buffer for ISA bus loads. Latched input for SEL24_48 at initial power up for H/W selecting the output frequency of 24_48MHz (Default=1, 24MHz). 24_48MHz/FS2& 28 I/O 24MHz or 48MHz output clock. Default is 24MHz. Latched input for FS2 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks(Default=0). 48MHz_0/ FS3* 27 I/O 48MHz / Latched input for FS3 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks (Default=1). 48MHz_1/ FS4* 26 I/O 48MHz / Latched input for FS3 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks (Default=1). 4.5 Power Pins SYMBOL VddC,VddA PIN 46,48 FUNCTION Power supply for CPU & IOAPIC, 2.5V or 3.3V. Vdd48 25 Power supply for 48MHz output,3.3V. Vdd3 10 Power supply for 3V_66 output, 3.3V. VddP 11,18 VddR 2 VddS 30,38 Vss Power supply for PCICLK, 3.3V. Power supply for REF0, 3.3V. Power supply for SDRAM_F,SDRAM[0:11], nominal 3.3V. 5,6,14,21,29,34,42, Circuit Ground. 43 -4- Publication Release Date: May 2000 Revision 0.37 W83194BR-138 PRELIMINARY 5.0 FREQUENCY SELECTION BY HARDWARE FS4 FS3 FS2 FS1 FS0 CPU(MHz) SDRAM (MHz) 3V66(MHz) PCI(MHz) IOAPIC (MHz) 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 66.67 66.87 68.67 100.00 100.31 103.00 66.67 66.87 68.67 33.33 33.44 34.33 16.67 16.72 17.17 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 0 1 0 1 0 1 71.34 100.00 100.30 103.00 107.00 133.33 133.73 107.00 100.00 100.30 103.00 107.00 133.33 133.73 71.34 66.67 66.87 68.67 71.33 66.67 66.87 35.67 33.33 33.43 34.33 35.67 33.33 33.43 17.83 16.67 16.72 17.17 17.83 16.67 16.72 0 0 1 1 0 0 1 1 0 1 137.33 120.00 137.33 120.00 68.67 60.00 34.33 30.00 17.17 15.00 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 133.33 133.73 137.33 120.00 136.00 140.00 142.67 145.33 100.00 100.30 103.00 90.00 136.00 140.00 142.67 145.33 66.67 66.87 68.67 60.00 68.00 70.00 71.33 72.67 33.33 33.43 34.33 30.00 34.00 35.00 35.67 36.33 16.67 16.72 17.17 15.00 17.00 17.50 17.83 18.17 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 1 136.00 140.00 142.67 145.33 146.67 153.33 102.00 105.00 107.00 109.00 146.67 153.33 68.00 70.00 71.34 72.67 73.34 76.67 34.00 35.00 35.67 36.33 36.67 38.33 17.00 17.50 17.83 18.17 18.33 19.17 1 1 1 1 0 0 1 1 0 1 160.00 166.67 160.00 166.67 80.00 83.34 40.00 41.67 20.00 20.83 1 1 1 1 1 1 0 0 0 1 146.67 160.00 110.00 120.00 73.34 80.00 36.67 40.00 18.33 20.00 1 1 1 1 1 1 1 1 0 1 166.67 200.00 125.00 200.00 83.34 100.00 41.67 50.00 20.83 25.00 -5- Publication Release Date: May 2000 Revision 0.37 W83194BR-138 PRELIMINARY 5.0 SERIAL CONTROL 0REGISTERS The Pin column lists the affected pin number and the @PowerUp column gives the state at true power up. Registers are set to the values shown only on true power up. "Command Code" byte and "Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. After that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and acknowledged. Frequency Table Setting by I2C (SEL5 ~ SEL0) SSEL5 SSEL4 SSEL3 SSEL2 SSEL1 SSEL0 CPU(MHz) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 66.67 66.87 68.67 71.34 100.00 100.30 103.00 107.00 133.33 133.73 137.33 120.00 133.33 133.73 137.33 120.00 136.00 140.00 142.67 145.33 136.00 140.00 142.67 145.33 146.67 153.33 160.00 166.67 146.67 160.00 166.67 200.00 -6- SDRAM (MHz) 100.00 100.31 103.00 107.00 100.00 100.30 103.00 107.00 133.33 133.73 137.33 120.00 100.00 100.30 103.00 90.00 136.00 140.00 142.67 145.33 102.00 105.00 107.00 109.00 146.67 153.33 160.00 166.67 110.00 120.00 125.00 200.00 3V66(MHz) PCI(MHz) 66.67 66.87 68.67 71.34 66.67 66.87 68.67 71.33 66.67 66.87 68.67 60.00 66.67 66.87 68.67 60.00 68.00 70.00 71.33 72.67 68.00 70.00 71.34 72.67 73.34 76.67 80.00 83.34 73.34 80.00 83.34 100.00 33.33 33.44 34.33 35.67 33.33 33.43 34.33 35.67 33.33 33.43 34.33 30.00 33.33 33.43 34.33 30.00 34.00 35.00 35.67 36.33 34.00 35.00 35.67 36.33 36.67 38.33 40.00 41.67 36.67 40.00 41.67 50.00 IOAPIC (MHz) 16.67 16.72 17.17 17.83 16.67 16.72 17.17 17.83 16.67 16.72 17.17 15.00 16.67 16.72 17.17 15.00 17.00 17.50 17.83 18.17 17.00 17.50 17.83 18.17 18.33 19.17 20.00 20.83 18.33 20.00 20.83 25.00 Publication Release Date: May 2000 Revision 0.37 W83194BR-138 PRELIMINARY SSEL5 SSEL4 SSEL3 SSEL2 SSEL1 SSEL0 CPU(MHz) SDRAM (MHz) 3V66(MHz) PCI(MHz) IOAPIC (MHz) 1 0 0 0 0 0 136.00 102.00 68.00 34.00 17.00 1 0 0 0 0 1 138.00 138.00 69.00 34.50 17.25 1 0 0 0 1 0 139.00 104.25 69.50 34.75 17.38 1 0 0 0 1 1 141.00 141.00 70.50 35.25 17.63 1 0 0 1 0 0 142.00 142.00 71.00 35.50 17.75 1 0 0 1 0 1 142.00 106.50 71.00 35.50 17.75 1 0 0 1 1 0 143.00 143.00 71.50 35.75 17.88 1 0 0 1 1 1 143.00 107.25 71.50 35.75 17.88 1 0 1 0 0 0 144.00 144.00 72.00 36.00 18.00 1 0 1 0 0 1 144.00 108.00 72.00 36.00 18.00 1 0 1 0 1 0 146.00 146.00 73.00 36.50 18.25 1 0 1 0 1 1 146.00 109.50 73.00 36.50 18.25 1 0 1 1 0 0 147.00 147.00 73.50 36.75 18.38 1 0 1 1 0 1 147.00 110.25 73.50 36.75 18.38 1 0 1 1 1 0 148.00 148.00 74.00 37.00 18.50 1 0 1 1 1 1 148.00 111.00 74.00 37.00 18.50 1 1 0 0 0 0 149.00 111.75 74.50 37.25 18.63 1 1 0 0 0 1 152.00 152.00 76.00 38.00 19.00 1 1 0 0 1 0 153.00 114.75 76.50 38.25 19.13 1 1 0 0 1 1 156.00 156.00 78.00 39.00 19.50 1 1 0 1 0 0 157.00 117.75 78.50 39.25 19.63 1 1 0 1 0 1 158.00 158.00 79.00 39.50 19.75 1 1 0 1 1 0 159.00 119.25 79.50 39.75 19.88 1 1 0 1 1 1 160.00 160.00 80.00 40.00 20.00 1 1 1 0 0 0 162.00 121.50 81.00 40.50 20.25 1 1 1 0 0 1 164.00 123.00 82.00 41.00 20.50 1 1 1 0 1 0 170.00 170.00 85.00 42.50 21.25 1 1 1 0 1 1 175.00 116.67 58.33 29.17 14.58 1 1 1 1 0 0 180.00 120.00 60.00 30.00 15.00 1 1 1 1 0 1 185.00 123.33 61.67 30.83 15.42 1 1 1 1 1 0 190.00 126.67 63.33 31.67 15.83 1 1 1 1 1 1 200.40 133.60 66.80 33.40 16.70 -7- Publication Release Date: May 2000 Revision 0.37 W83194BR-138 PRELIMINARY 5.1 Register 0: CPU Frequency Select Register Bit @PowerUp Pin 7 6 5 4 3 0 0 0 0 0 - 2 1 0 0 - 0 0 - Description SSEL3 (Frequency table selection by software via I2C ) SSEL2 ( Frequency table selection by software via I2C) SSEL1 ( Frequency table selection by software via I2C) SSEL0 ( Frequency table selection by software via I2C) 0 = Selection by hardware 1 = Selection by software I2C - Bit (2, 7:4) SSEL4 (Frequency table selection by software via I2C ) SSEL5 (Frequency table selection by software via I2C ) 0 = Running 1 = Tristate all outputs 5.2 Register 1 : CPU Clock Register (1 = Active, 0 = Inactive) Bit @PowerUp Pin escription 7 X - FS0# 6 X - FS1# 5 X - FS2# 4 X - FS3# 3 X - FS4# 2 0 - 1 0 - 0 1 - 1 = ±0.25% Center type Spread Spectrum Modulation 0 = ±0.5% Center type Spread Spectrum Modulation 0 = Normal 1 = Spread Spectrum enabled 1 = Center type Spread Spectrum Modulation 0 = Down type Spread Spectrum Modulation 5.3 Register 2: SDRAM Clock Register (1 = Active, 0 = Inactive) Bit @PowerUp Pin Description 7 1 SDRAM7 (Active / Inactive) 6 1 SDRAM6 (Active / Inactive) 5 1 SDRAM5 (Active / Inactive) 4 1 SDRAM4 (Active / Inactive) 3 1 SDRAM3 (Active / Inactive) 2 1 SDRAM2 (Active / Inactive) 1 1 SDRAM1 (Active / Inactive) 0 1 SDRAM0 (Active / Inactive) -8- Publication Release Date: May 2000 Revision 0.37 W83194BR-138 PRELIMINARY 5.4 Register 3: PCI Clock Register (1 = Active, 0 = Inactive) Bit @PowerUp Pin Description 7 1 31 SDRAM_F (Active / Inactive) 6 1 20 PCICLK6 (Active / Inactive) 5 1 19 PCICLK5 (Active / Inactive) 4 1 17 PCICLK4 (Active / Inactive) 3 1 16 PCICLK3 (Active / Inactive) 2 1 15 PCICLK2 (Active / Inactive) 1 1 13 PCICLK1 (Active / Inactive) 0 1 12 PCICLK0 (Active / Inactive) 5.5 Register 4: Additional Register (1 = Active, 0 = Inactive) Bit @PowerUp Pin 7 1 9 3V66_2(Active / Inactive) 6 1 8 3V66_1(Active / Inactive) 5 1 4 1 7 28 3V66_0(Active / Inactive) 24_48MHz(Active / Inactive) 3 1 47 IOAPIC(Active / Inactive) 2 1 27 48MHz_0(Active / Inactive) 1 1 26 48MHz_1(Active / Inactive) 0 1 1 REF0 (Active / Inactive) Description 5.6 Register 5: SDRAM Clock Register (1 = Active, 0 = Inactive) Bit @PowerUp Pin Description 7 1 - CSkew2 (CPU to SDRAM skew program bit) 6 0 - CSkew1 (CPU to SDRAM skew program bit) 5 0 - CSkew0 (CPU to SDRAM skew program bit) 4 1 - CASkew2 (CPU to 3V66 skew program bit) 3 0 - CASkew1 (CPU to 3V66 skew program bit) 2 0 - CASkew0 (CPU to 3V66 skew program bit) 1 1 44 CPUCLK1(Active / Inactive) 0 1 45 CPUCLK0(Active / Inactive) -9- Publication Release Date: May 2000 Revision 0.37 W83194BR-138 PRELIMINARY 5.7 Register 6~10: Step-less M/N mode Control Registers 5.12 Register 11: Winbond Chip ID Register (Read Only) Bit @PowerUp Pin Description 7 1 - Winbond Chip ID 6 0 - Winbond Chip ID 5 0 - Winbond Chip ID 4 1 - Winbond Chip ID 3 1 - Winbond Chip ID 2 0 - Winbond Chip ID 1 0 - Winbond Chip ID 0 0 - Winbond Chip ID 5.13 Register 12: Winbond Chip ID Register (Read Only) Bit 7 6 5 @PowerUp 0 0 1 Pin - 4 3 2 1 0 1 0 0 1 0 - Bit6 DS3 0 0 0 0 0 0 0 0 1 1 Register10 Bit3-6 Bit 5 Bit 4 DS2 DS1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 x 1 x Description Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Version ID Winbond Version ID Winbond Version ID Winbond Version ID Ratio Bit 3 DS0 0 1 0 1 0 1 0 1 x x CPU 4 3 2 2 6 3 6 4 2 2 - 10 - SDRAM 4 3 3 2 4 4 3 3 2 4 3V66 6 6 6 6 6 6 6 6 4 6 Publication Release Date: May 2000 Revision 0.37 W83194BR-138 PRELIMINARY 6.0 SPECIFICATIONS 6.1 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or Vdd). Symbol Parameter Rating Vdd , VIN Voltage on any pin with respect to GND - 0.5 V to + 7.0 V TSTG Storage Temperature - 65°C to + 150°C TB Ambient Temperature - 55°C to + 125°C TA Operating Temperature 0°C to + 70°C 6.2 AC CHARACTERISTICS VddR=Vdd3=VddP=VddS=3.3V ± 5 %, VddC = VddA= 2.375V~2.9V , TA = 0°C to +70°C Parameter Symbol Output Duty Cycle Min Typ Max Units 45 50 55 % Measured at 1.5V 4 ns 15 pF Load Measured at 1.5V 15 pF Load Measured at 1.5V 1 Test Conditions CPU/SDRAM to PCI Offset tOFF Skew (CPU-CPU), (PCIPCI), (SDRAM-SDRAM) tSKEW 250 ps tCCJ ±250 ps tJA 500 ps BWJ 500 KHz 0.4 1.6 ns 15 pF Load on CPU and PCI outputs CPU/SDRAM Cycle to Cycle Jitter CPU/SDRAM Absolute Jitter Jitter Spectrum 20 dB Bandwidth from Center Output Rise (0.4V ~ 2.0V) tTLH & Fall (2.0V ~0.4V) Time tTHL Overshoot/Undershoot Vover 0.7 1.5 V 22 Ω at source of 8 inch PCB run to 15 pF load VRBE 0.7 2.1 V Ring Back must not enter this range. Beyond Power Rails Ring Back Exclusion - 11 - Publication Release Date: May 2000 Revision 0.37 W83194BR-138 PRELIMINARY 6.3 DC CHARACTERISTICS VddR=Vdd3=VddP=VddS=3.3V ± 5 %, VddC = VddA= 2.375V~2.9V , TA = 0°C to +70°C Parameter Symbol Min Input Low Voltage VIL Input High Voltage VIH Vss0.3 2.0 Input Low Current (no pull-up Resistors) Input Low Current (pull-up Resistors) Input High Current IIL -5 2.0 µA IIL -200 -100 µA IIH IDD -5 Operating Current Power Down Current Input Frequency Pin Inductance Input Capacitance Transition Time Disable/Enable Delay Clock stabilization 60 400 IDDPD Fi Lpin CIN COUT CINX TTra T TSTA Typ Max Units 0.8 Vdc Vdd +0.3 Vdc 5 µA 100 600 mA 14.318 7 5 6 13.5 22.5 3 10 3 1 - 12 - µA MHz nH pF pF pF mS nS mS Test Conditions @66M CL= 0pF Vdd=3.3V Logic Inputs Output pins capacitance X1 & X2 pins Publication Release Date: May 2000 Revision 0.37 W83194BR-138 PRELIMINARY 7.0 ORDERING INFORMATION Part Number Package Type Production Flow W83194BR-138 48 PIN SSOP Commercial, 0°C to +70°C 8.0 HOW TO READ THE TOP MARKING W83194BR-138 28051234 814GAB 1st line: Winbond logo and the type number: W83194BR-138 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 814 G B B 814: packages made in '98, week 14 G: assembly house ID; O means OSE, G means GR A: Internal use code B: IC revision All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 13 - Publication Release Date: May 2000 Revision 0.37 W83194BR-138 PRELIMINARY 9.0 PACKAGE DRAWING AND DIMENSIONS Headquarters Winbond Electronics (H.K.) Ltd. No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/ Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064 Winbond Electronics (North America) Corp. 2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale. - 14 - Publication Release Date: May 2000 Revision 0.37