TI TLV1562

TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
D
D
D
D
D
D
D
D
D
D
D
2 MSPS Max Throughput at 10 Bit (Single
Channel), ±1 LSB DNL, ±1 LSB INL MAX
3 MSPS Max Throughput at 8 Bit (Single
Channel), ±1 LSB DNL, ±1 LSB INL MAX
7 MSPS Max Throughput at 4 Bit (Single
Channel), ±0.4 LSB DNL, ±0.4 LSB INL MAX
No Missing Code for External Clock Up to
15 MHz at 5.5 V, 12 MHz at 2.7 V
ENOB 9.4 Bit, SINAD 57.8 dB, SFDR
–70.8 dB, THD –68.8 dB, at fi = 800 kHz,
10 Bit
Wide Input Bandwidth for Undersampling
(75 MHz at 1 dB, >120 MHz at –3 dB) at
Rs = 1 kΩ
Software Programmable Power Down,
(1 µA), Auto Powerdown (120 µA)
Single Wide Range Supply 2.7 VDC to
5.5 VDC
Low Supply Current 11 mA at 5.5 V, 10 MHz;
7 mA at 2.7 V, 8 MHz Operating
Simultaneous Sample and Hold:
Dual Sample and Hold Matched Channels
Multi Chip Simultaneous Sample and Hold
Capable
Programmable Conversion Modes:
Interrupt-Driven for Shorter Latency
Continuous Modes Optimized for MIPS
Sensitive DSP Solutions
D
D
D
D
Built-In Internal/System Mid-Scale Error
Calibration
Built-In Mux With 2 Differential or 4
Single-Ended Input Channels
Low Input Capacitance (10 pF Max Fixed,
1 pF Max Switching)
DSP/µ P-Compatible Parallel Interface
applications
D
D
D
D
D
D
D
D
D
D
D
D
Portable Digital Radios
Personal Communication Assistants
Cellular
Pager
Scanner
Digitizers
Process Controls
Motor Control
Remote Sensing
Automotive
Servo Controls
Cameras
DW OR PW PACKAGE
(TOP VIEW)
CSTART
(LSB) D0
D1
D2
D3
D4
BDVDD
BDGND
D5
D6
D7
D8
(MSB) D9
INT
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
RD
AP/CH1
AM/CH2
BP/CH3
BM/CH4
AVDD
VREFP
VREFM
AGND
WR
DGND
DVDD
CLKIN
CS/OE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
functional block diagram
AVDD
DVDD
BDVDD
AP/CH1
S/H
AM/CH2
M
U
X
BP/CH3
BM/CH4
Amplifier
4/8/10-Bit
Recyclic
ADC
D (0–9)
Serial/Parallel Conv
and FIFO
3-State
Buffer
S/H
VREFP
VREFMID
Control
Register
CS/OE
Interface
Timing
and
Control
INT
REF
VREFM
CLKIN
(15 MHz Max)
SysClk
OSC
(7.5 MHz Min)
CSTART
WR
RD
AGND
DGND
BDGND
description
The TLV1562 is a 10-bit CMOS low-power, high-speed programmable resolution analog-to-digital converter
based on a low-power recyclic architecture. The unique architecture delivers a throughput up to 2 MSPS (million
samples per second) at 10-bit resolution. The programmable resolution allows a higher conversion throughput
as a tradeoff of lower resolution. A high speed 3-state parallel port directly interfaces to a digital signal processor
(DSP) or microprocessor (µP) system data bus. D0 through D9 are the digital output terminals with D0 being
the least significant bit (LSB). The TLV1562 is designed to operate for a wide range of supply voltages
(2.7 V to 5.5 V) with very low power consumption (11 mA maximum at 5.5 V, 10 MHz CLKIN). The power saving
feature is further enhanced with a software power-down feature (1 µA maximum) and auto power-down (1 µA
maximum) feature.
Many programmable features make this device a flexible general-purpose data converter. The device can be
configured as either four single-ended inputs to maximize the capacity or two differential inputs to improve noise
immunity. The internal system clock (SYSCLK) may come from either an internally generated OSC or an
external clock source (CLKIN). Four different modes of conversion are available for different applications. The
interrupt driven modes are mostly suitable for asynchronous applications, while the continuous modes take
advantage of the high speed nature of a pipelined architecture. A pair of built-in sample-and-hold amplifiers
allow simultaneous sampling of two input channels. This makes the TLV1562 perfect for communication
applications. Conversion is started by the RD signal, which can also be used for reading data, to maximize the
throughput. Conversion can be started either by the RD or CSTART signal when the device is operating in the
interrupt-driven modes. The dedicated conversion start pin, CSTART, provides a mechanism to simultaneously
sample and convert multiple channels when multiple converters are used in an application.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
description (continued)
The converter incorporates a pair of differential high-impedance reference inputs that facilitate ratiometric
conversion, scaling, and isolation of analog circuitry from logic and supply noise. Other features such as low
input capacitance (10 pF) and very wide input bandwidth (75 MHz) make this device a perfect digital signal
processing (DSP) companion for mobile communication applications. A switched-capacitor design allows
low-error conversion over the full operating free-air temperature range.
The features that make this device truly a DSP friendly converter include: 1) programmable continuous
conversion modes, 2) programmable 2s complement output code format, and 3) programmable resolution. The
TLV1562 is offered in both 28-pin TSSOP and SOIC packages. The TLV1562C is characterized for operation
from 0°C to 70°C. The TLV1562I is characterized for operation over the full industrial temperature range of
–40°C to 85°C.
AVAILABLE OPTIONS
PACKAGED DEVICE
28-TSSOP
(25 MIL PITCH)
(PW)
28-SOIC
(50 MIL PITCH)
(DW)
0°C to 70°C
TLV1562CPW
TLV1562CDW
–40°C to 85°C
TLV1562IPW
TLV1562IDW
TA
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AGND
20
I
Analog ground return for the internal circuitry. Unless otherwise noted, all analog voltage measurements are with
respect to AGND.
AM/CH2
26
I
Differential channel A input minus or single-ended channel 2
AP/CH1
27
I
Differential channel A input plus or single-ended channel 1
AVDD
BDGND
23
I
Positive analog supply voltage
8
I
Digital ground return for the I/O buffers. Unless otherwise noted, all digital interface voltage measurements are with
respect to DGND.
BDVDD
BM/CH4
7
I
Positive digital supply voltage for I/O buffers
24
I
Differential channel B input minus or single-ended channel 4
BP/CH3
25
I
Differential channel B input plus or single-ended channel 3
CLKIN
16
I
External clock input. (1 MHz to 15 MHz)
CS/OE
15
I
Chip select. A high-to-low transition on this input resets the internal counters and controls and enables the output data
bus D(0–9) and control inputs (RD, WR) within a maximum setup time. A low-to-high transition disables the output
data bus D(9–0) and WR within a maximum setup time. This signal also serves as an output enable signal when the
device is programmed into both mono and dual interrupt-driven modes using CSTART as the start of conversion
signal.
1
I
Conversion start signal. A falling edge starts the sampling period and a rising edge starts the conversion. This signal
acts without CS activated. CSTART connects to DVDD via a 10-kΩ pull-up resistor if not used.
CSTART
D(0–4)
2–6
I/O
The lower bits of the 3-state parallel data bus. Bidirectional. The data bus is 3-stated except when RD or WR is low
when CS is low.
D(5–9)
9–13
I/O
The higher bits of the 3-state parallel data bus. Bidirectional. The data bus is 3-stated except when RD or WR is low
when CS is low. When the host processor writes to the converter, D(9,8) are used as an index to the internal registers.
DGND
18
I
Digital ground return for the internal digital logic circuitry
DVDD
17
I
Positive digital supply voltage
INT
14
O
Interrupt output. The falling edge of INT signals the end of conversion. This output goes from a high impedance state
to low logic level on the fifth falling edge of the system clock and remains low until reset by the rising edge of CS or
RD. INT requires connection of a 10-kΩ pull-up resistor.
RD
28
I
Processor read strobe or synchronous start of conversion/sampling. The falling edge of RD is used to 1) start the
conversion in interrupt-driven mode (if RD is programmed as the start conversion signal); 2) start both conversion
and next sampling plus release of the previous conversion data in both continuous modes. The rising edge of RD
serves as a read strobe and data is 3-stated (approximately 10 ns at 50 pF bus loading) after this edge. Connection
of a 10-kΩ pull-up resistor is optional.
VREFM
21
I
The lower voltage reference value is applied to this terminal.
VREFP
22
I
The upper reference voltage value is applied to this terminal. The maximum input voltage range is determined by the
difference between the voltage applied to this terminal and the VREFM terminal.
WR
19
I
Processor write strobe. Active low. Connection of a 10-kΩ pull-up resistor is optional.
detailed description
The TLV1562 analog-to-digital converter is based on an advanced low power recyclic architecture. Two bits of
the conversion result are presented per system clock cycle. A total of 5 system clock (SYSCLK) cycles is
required to complete the conversion. The serial conversion results are converted to a parallel word for output.
The device supports both interrupt-driven (typically found in a SAR type ADC) and continuous (natural for a
pipeline type ADC) modes of conversion. An innovative conversion scheme makes this device perfect for power
sensitive applications with uncompromised speed.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
control register
The TLV1562 is software configurable. The first two bits, MSBs (D9,8), are used to address the register set. The
rest of the 8 bits are used as data. There are two control registers, CR0 and CR1, for user configuration. All of
these register bits are written to the control register during a write cycle. A description of the control registers
and the input/output data formats are shown in Figure 1.
Input Data Format
Pin D9
Index1
Pin D8
Index0
0
CR0
Pin D7
Pin D6
Pin D5
Offset Calibration Set OMS(1,0)
0,0 = Operate with calibration
0,1 = Measure system offset
1,0 = Measure internal offset
1,1 = Operate without calibration
0
Pin D4
Conversion
Clock Select
0 = Internal
1 = External
Pin D3
Input Type:
0 = Single end
1 = Differential
Pin D2
Pin D1
Conversion Mode Select MS(1,0)
0,0 = Mono interrupt
0,1 = Dual interrupt
1,0 = Mono continuous
1,1 = Dual continuous
Pin D0
Channel Select CS(1,0)
0,0 = Ch1 or pair A
0,1 = Ch2 or pair A
1,0 = Ch3 or pair B
1,1 = Ch4 or pair B
System Offset Calibration: Short the system input to the system AGND
Internal Offset Calibration: Short the two inputs to the S/HA to AGND
0
CR1
0
Interrupt-Mode
Conversion
Started
0 = By RD
1 = By CSTART
1
Resolution Select BS(1,0)
0,0 = 10-Bit
0,1 = 4-Bit
1.0 = 8-Bit
1.1 = 12-Bit Test
0
Output Format
0 = 2’s
Complement
1 = Binary
Interrupt-Mode
Auto
Power Down
0 = Disabled
1 = Enabled
SW Power Down
0 = Normal
1 = S/W Power
Down
Reference delta should be greater than 2 V when swing is reduced.
Output Data Format
Pin D9
Pin D8
Pin D7
Pin D6
Register Index
Pin D5
Pin D4
Pin D3
Pin D2
Pin D1
Pin D0
Configuration Register Content
Configuration Result
MSB
CR1
D(5,4)
= 0,0
LSB
OD9
OD8
OD7
OD6
OD3
OD2
OD1
OD0
OD3
OD2
OD1
OD0
Z
Z
LSB
Z
Z
Z
Z
4-Bit Conversion Result
MSB
CR1
D(5,4)
= 1,0
OD4
10-Bit Conversion Result
MSB
CR1
D(5,4)
= 0,1
OD5
OD7
OD6
OD5
OD4
OD3
OD2
LSB
OD1
OD0
Z
Z
8-Bit Conversion Result
NOTE:
Z indicates bits write zero read zero back.
Figure 1. Input/Output Data Formats
NOTE:
Channel select bits CR0.(1,0), CS(1,0) are ignored when the device is in the dual (interrupt or
continuous) modes using differential inputs, since both differential input pairs are automatically
selected. CR0.0 (i.e., CS0 bit) is used to determine if channels 1 and 3 or channels 2 and 4 are
selected if single-ended input mode is used.
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TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
detailed description (continued)
Table 1. Select Input Channels
CR0.4
(INPUT TYPE)
CR0.(3,2)
(CONVERSION MODE
SELECT)
CR0.(1,0)
(CHANNEL SELECT)
0 (Single-ended)
00 or 10
0,0
CH1
Single channel
0 (Single-ended)
00 or 10
0,1
CH2
Single channel
0 (Single-ended)
00 or 10
1,0
CH3
Single channel
0 (Single-ended)
00 or 10
1,1
CH4
Single channel
1 (Differential)
00 or 10
0,X
Differential pair A
Single channel
1 (Differential)
00 or 10
1,X
Differential pair B
Single channel
0 (Single-ended)
01 or 11
X,0
Both CH1 and CH3
Dual channels
0 (Single-ended)
01 or 11
X,1
Both CH2 and CH4
Dual channels
0 (Single-ended)
01 or 11
X,0
Both CH1 and CH3
Dual channels
0 (Single-ended)
01 or 11
X,1
Both CH2 and CH4
Dual channels
1 (Differential)
01 or 11
X,X
Both differential pairs A and B
Dual channels
CHANNEL(S)
SELECTED
NOTE
configure the device
The device can be configured by writing to control registers CR0 and CR1. A read register is carried out by
auto-sequence when the device is put into the software power-down state. CR0 is read first and then CR1 at
the next two RD rising edges after the device is in the software power-down state. The falling edge of RD has
no meaning and does not trigger a conversion in the software power-down state.
VIH
CS
VIL
tw(CSH)
td(WRH-CSH)
VIH
CSTART
td(CSL-WRL)
ts(DATAIN)
VIH
WR
VIL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tw(WRL)
DATA
Configure Data
Figure 2. Configuration Cycle Timing
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
ÎÎÎÎÎ
ÎÎÎÎÎ
th(DATAIN)
VIH
VIL
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
detailed description (continued)
The following examples show how to program configuration registers CR0 and CR1 for different settings.
Example 1:
REGISTER
INDEX
COMMENT
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CR0
0
0
1
1
0
1
0
0
0
0
Mono interrupt mode, use RD, write 0D0h to ADC
CR1
0
1
0
0
0
0
0
0
0
0
Use 2s complementary output, use RD, write 104h to ADC
CR0
0
0
1
1
0
1
0
0
0
0
Mono interrupt mode, use CSTART, write 0D0h to ADC
CR1
0
1
0
1
0
0
0
0
0
0
Use 2s complementary output, write 144h to ADC
CR0
0
0
1
1
0
1
0
1
0
0
Dual interrupt mode, use CSTART only, write 0D4h to ADC
CR1
0
1
0
1
0
0
0
0
0
0
Use 2s complementary output, write 144h to ADC
CR0
0
0
1
1
0
1
1
0
0
0
Mono continuous mode, use RD only, write 0D8h to ADC
CR1
0
1
0
0
0
0
0
0
0
0
Use 2s complementary output, write 104h to ADC
CRO
0
0
1
1
0
1
1
1
0
0
Dual continuous mode, use RD only, write 0DCh to ADC
CR1
0
1
0
0
0
0
0
1
0
0
Binary output, write 104h to ADC
Example 2:
Example 3:
Example 4:
Example 5:
analog input
input types
The four analog inputs can be configured as two pairs of differential inputs or four single-ended inputs by setting
the control register 0 bit 4 input type selection (dual or single channel).
differential input (CR0.4=1)
Up to two channels are available when the TLV1562 is programmed for differential input. The output data format
is bipolar when the device is operated in differential input mode.
single-ended input (CR0.4=0)
Up to four channels are available when the TLV1562 is programmed for single-ended input. The output data
format is unipolar when the device is operated in single-ended input mode.
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TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
detailed description (continued)
input signal range
The analog input signal range for a specific supply voltage AVDD ranges from (AVDD – 1.9 V) to 0.8 V.
VSWING
3V
0.8 V
2.7
4.9
5.5
AVDD (V)
Linearity not Guaranteed
Limited by Noise
Figure 3. Analog Input Range vs AVDD
VREFCM + 0.5 × VSWING ≤ AVDD –1 V
VREFCM – 0.5 × VSWING ≥ 0.8 V
Where:
VREFCM = (VREFP + VREFM)/2 is the common mode reference voltage.
VSWING = dynamic range of the input signal,
VSWING = VINP – VINM,
And the common mode input voltage is:
VINCM = (VINP + VINM)/2,
MAX VSWING = MIN [(AVDD – 1.9 V), 3 V]
For single-ended input, the analog input range is between VREFP and VREFM. So the range of
single-ended VIN is:
3V
1V
0.8 V
if AVDD = 3 V
if AVDD = 3 V
if AVDD = 2.7 V
For differential input, the input common mode voltage VINCM can be between AVDD and AGND as long as
3 V ≥ (VINP–VINM) ≥ 0.8 V.
This means VINCM ≥ 0.4 V.
So the range of differential analog input voltage, (VINP–VINM) is:
3V
if AVDD = 3 V
1V
if AVDD = 3 V
0.8 V
if AVDD = 2.7 V
8
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TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
detailed description (continued)
equivalent input impedance
Ron(Ω)
1k
FB
Rs
Ron
Ron
Vin
0 V
Cpad = 10 pF
Buffer
0.5 k
Csample = 0.5 pF
2.7
Figure 4. Equivalent Input Circuit
5.5
VCC (V)
Figure 5. Input Mux On Resistance vs
Analog Supply Voltage
Req = Vin/Ieq = (Q/Cin)/(Q/T) = T/Cin = 1/(fs × Csample) = 1/(2 MHz × 0.5 pF) = 1 MΩ
Where fs is the sampling frequency, and fc is the conversion frequency
when the device is in one channel/continuous conversion mode,
fs = fc/5
fs = fc/10
when the device is in one channel/continuous conversion mode,
fs = Conversion trigger strobe frequency when the device is in interrupt mode (RD or CSTART)
Csample = Input capacitance = 0.5 pF
Cparasitic = Parasitic capacitance = 0.5 pF
Cpad = Input PAD capacitance = 10 pF
Ron = Mux switch on series resistance = 1 kΩ at 2.7 V
Rs = Source output resistance = 1 kΩ
input bandwidth (full power 0 dB input, BW at –1 dB)
0
Attenuation in dB
–1
–2
–3
–4
–5
10
20
30
70
90 100 110 120 130 140 150
60
80
Analog Input Frequency – MHz
BW = 1/[2 × π × (Rtotal y Cac)]
= 1/[2 × π × ((Ron + Rs) × (Csample + Cparasitic))]
= 1/[2 × π × (2K × 1 pF)]
= 79.6 MHz
(Theoretical Max)
40
50
Figure 6. Typical Analog Input Frequency Input Bandwidth
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TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
reference voltage inputs
The TLV1562 has two reference input pins: REFP and REFM. The voltage levels applied to these pins establish
the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively. The
values of VREFP, VREFM, and the analog input should not exceed the positive supply or be less than GND
consistent with the specified absolute maximum ratings. The digital output is at full scale when the input signal
is equal to or higher than VREFP and is at zero when the input signal is equal to or lower than VREFM. The
internal resistance from VREFP to VREFM may be as low as 20 kΩ (±10%).
Rs
Ron
VREFP
Cpad
= 10 pF
Cin = 1 pF
10 kΩ
VREFCM
10 kΩ
Rs
Ron
VREFM
Cpad
= 10 pF
Cin = 1 pF
The reference voltages must satisfy the following conditions:
VREFP ≤ AVDD – 1 V,
AGND + 0.9 V < VREFM and
3 V ≥ (VREFP – VREFM) ≥ 0.8 V
Figure 7. Equivalent Circuit for Reference input
10
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TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
sampling/conversion
All of the sampling, conversion, and data output in the device are started by a trigger. This trigger can be the
RD or CSTART signal depending on the mode of conversion and configuration. The falling edge of the RD signal
and the rising edge of the CSTART signal are extremely important since they are used to start the conversion.
These edges need to stay as close to the falling edges of the external clock, if they are used as SYSCLK. The
minimum setup time with respect to the rising edge of the external SYSCLK should be 5 ns minimum. When
the internal SYSCLK is used, this is not an issue, since these two edges start the internal clock automatically;
therefore, the setup time is always met.
USING EXTERNAL CLOCK
S/H Hold Time
VIH
EXTERNAL
SYSCLK
VIL
td(ECLKL-TRGL)
ts(TRGL-ECLKH)
RD
Conversion Starts
CSTART
Conversion Starts
VIH
Next Sampling Starts
VIL
VIH
Next Sampling Starts
VIL
Sampling Period
Figure 8. Conversion Trigger Timing – External Clock
USING INTERNAL CLOCK
INTERNAL
CLOCK STARTS
Conversion Starts
RD
Next Sampling Starts
VIH
VIL
td(TRGL-ICLKH)
VIH
Conversion Starts
CSTART
Next Sampling
Starts
VIL
S/H Hold Time
VIH
INTERNAL
SYSCLK
VIL
Figure 9. Conversion Trigger Timing – Internal Clock
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TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
Table 2. Conversion Trigger Edge
START OF
CONVERSION
CONVERSION
TIME
(INTERNAL CLK)
CONVERSION
TIME
(EXTERNAL CLK)
INTERRUPT
CANCELED
BY
WR ↑‡ or
2 SYSCLK from RD ↓
RD ↓
6 SYSCLK
5 SYSCLK
RD ↑
41 ns§ from INT low
CSTART†
CSTART ↓
CSTART ↑
6 SYSCLK
5 SYSCLK
RD ↓
41 ns§ from RD low
Dual
Interrupt
CSTART
CSTART ↓
CSTART ↑
12 SYSCLK
10 SYSCLK
First RD ↓
41 ns§ from RD low
Mono
Continuous
RD
WR ↑‡ or
2 SYSCLK from RD ↓
RD ↓
6 SYSCLK
5 SYSCLK
N/A
41 ns§ from RD low
Dual
Continuous
RD
WR ↑‡ or
7 SYSCLK from RD ↓
RD ↓
12 SYSCLK
10 SYSCLK
N/A
41 ns§ from RD low
CONVERSION
MODE
CONVERSION
TRIGGER
Mono
Interrupt
RD
START OF
SAMPLING
DATA OUT
† CSTART works with or without CS active.
‡ The first sampling period starts at the last RD low of the previous cycle or WR high of the configuration cycle. RD low is the falling edge of RD
and WR high is the rising edge of the WR signal. (Minimum sample/hold amp settling time = one SYSCLK, approximately 100 ns min, at Rs ≤
1 kΩ).
§ Output data enable time is dependent on bus loading and supply voltage (BDVDD). For BDVDD = 5 V, the enable time is 19 ns at 25 pF, 23 ns
at 50 pF, and 25 ns at 100 pF. For BDVDD = 2.7 V, the enable time is 37 ns at 25 pF, 41 ns at 50 pF, and 56 ns at 100 pF.
The TLV1562 provides four types of conversion modes. The two interrupt-driven conversion modes are
asynchronous and are simple one-shot conversions. The auto-powerdown conversion feature can be enabled
when interrupt-driven conversion modes are used. The other two continuous conversion modes are
synchronous with the RD signal (as a clock) from the processor and are more suitable for repetitive signal
measurement. These different modes of conversion offer a tradeoff between simplicity and speed.
12
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TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
detailed description (continued)
Table 3. Maximum Conversion Speed (for 1 LSB INL and DNL at 10 bit)
MAXIMUM CONVERSION THROUGHPUT†
CONVERSION MODE
CR0.(3,2)
RD
interrupt driven conversion mode
Mono interrupt-driven
RD with auto power down
00
CSTART
CSTART with auto power down
INTERNAL CLOCK
(8 MHz)
1.5 MSPS
1.1 MSPS
0.82 MSPS
0.68 MSPS
1.5 MSPS
1.1 MSPS
0.82 MSPS
0.68 MSPS
1.5 MSPS
0.91 MSPS
1.05 MSPS
2 MSPS§
0.83 MSPS
1.33 MSPS§
Dual continuous conversion mode
RD
11
2 MSPS¶
† Speed is calculated for 5-V with a 2-V reference
(5.5 V to 3 V, I-temperature and C-temperature: 2 MSPS at 10 bit, 3 MSPS at 8 bit, 7 MSPS at 4 bit;
3 V to 2.7 V, C-temperature: 2 MSPS at 10 bit, 2.5 MSPS at 8 bit, 7 MSPS at 4 bit;
3 V to 2.7 V, I-temperature: 1.6 MSPS at 10 bit, 2.5 MSPS at 8 bit, 7 MSPS at 4 bit).
Higher throughput is possible when the linearity requirement is relaxed.
‡ Dual interrupt mode is available to 8-bit or 10-bit resolution and single-ended input type.
§ Throughput from single selected channel.
¶ Combined throughputs from a pair of selected channels.
1.33 MSPS¶
Dual interrupt-driven
interrupt driven conversion mode‡
Mono continuous conversion mode
CSTART
EXTERNAL CLOCK
(10 MHz)
CSTART with auto power down
RD
01
10
Conversion Start
RD-Strobe
Conversion Results
Mono Interrupt Mode: 0 RD-Delay
Dual Interrupt Mode: 0~1 RD-Delay
Mono Continuous Mode : 1 RD-Delay
Dual Continuous Mode : 2~3 RD-Delay
Figure 10. Digital Delays for Different Conversion Modes
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TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
mono interrupt-driven mode (CR0.(3,2) = 0,0)
The mono interrupt-driven conversion mode provides a one-shot conversion. Sampling, conversion, and data
output are all performed in a single cycle. The analog signal is sampled 2 SYSCLKs after the falling edge of RD
(or the rising edge of WR if this is the first sample after configuration) and then converted on the falling edge
of RD. Once the data is ready, INT falls and the data is output to the bus. The rising edge of RD cancels INT
and initiates a read of the data. The data bus is 3-stated when RD goes high. It is not necessary to configure
the converter for each cycle or toggle CS between cycles.
V IH
CS
CSTART
V IL
Sample 1
Conv 1
Sample 2
Conv 2
t conv1
t conv1
t s1
t s1
V IH
t d(RDL-SAMPLE)
WR
V IL
V IH
RD
V IL
t dis(DATAOUT)
DATA
V IH
Hi–Z
Data 1
V IL
t d(RDL-CONV)
t en(DATAOUT)
t d(RDH-INTZ)
t d(CONV-INTL)
INT
(With Pullup)
V IH
t 1(APDR)
Power Down
(If Autopower Down is Set)
t 1(APDR)
t (APD)
Power Down
(If Autopower Down is Set)
Figure 11. Mono Interrupt-Driven Mode Using RD
14
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V IL
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
Conversion can also be started with CSTART. This is useful when an application requires multiple TLV1562s
for simultaneous samplings and conversions. The falling edge of CSTART starts the sampling and the rising
edge of CSTART starts the conversion. Once the data is ready INT falls. INT is terminated by the following falling
edge of RD which also outputs the data to the bus. On the rising edge of RD, the data is read and the data bus
is 3-stated.
V IH
CS
V IL
t d1(WRH–CSTARTL)
t d(RDH-CSTARTL)
t w(CSTARTL)
t d(CSL-RDL)
V IH
CSTART
V IL
V IH
WR
V IL
Sample 1
t s1
Conv 1
Sample 2
t s1
t w(RDL)
t conv1
V IH
RD
t d(INTL-CSL)
t dis(DATAOUT)
t d(CSTART-SAMPLE)
V IL
t en(DATAOUT)
V IH
Data 1
DATA
V IL
t d1(CSTARTH–CONV)
t d(CSTARTL-SAMPLE)
t d(CONV-INTL)
t d(RDH-INTZ)
(With Pullup)
V IH
INT
t 1(APDR)
t (APD)
t 1(APDR)
V IL
Power Down
(If Autopower Down is Set)
Power Down
Figure 12. Mono Interrupt-Driven Mode Using CSTART
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TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
dual interrupt-driven mode (CR0.(3,2) = 0,1)
The dual interrupt-driven conversion mode provides a similar one-shot conversion, sampling, and conversion
but also samples both selected channels simultaneously. Conversion can only be started with the CSTART
signal. The falling edge of CSTART starts the sampling of both of the input channels selected, and the rising
edge of CSTART starts the conversion. Since it takes two consecutive conversions internally, the conversion
time required is doubled (10 SYSCLK cycles). Once the data are ready, INT falls. INT is terminated by the first
falling edge of RD, which also outputs the first data to the bus. On the rising edge of RD, data is read and the
data bus is 3-stated. The second RD falling edge outputs the second data to the bus and then reads it on the
rising edge and 3-states the bus. It is not necessary to configure the converter for each cycle or toggle CS
between cycles.
NOTE:Dual interrupt mode is available to 10-bit or 8-bit resolution and single-ended input
type.
t d2(WRH–CSTARTL)
t d(INT-CSL)
t w(CSH)
V IH
CS
VIL
t w(CSTARTL)
V IH
CSTART
VIL
V IH
WR
VIL
Sample 1
Conv 1
Sample 2
t s4
t conv2
t s4
t d2(RDH–CSTARTL)
t w(RDL)
V IH
VIL
RD
Data 1A
DATA
t dis(DATAOUT)
t dis(DATAOUT)
t EN(DATAOUT)
t d2(CSTART–CONV)
t d(RDL-INTZ)
V IH
Data 1B
VIL
t en(DATAOUT)
(With Pullup)
V IH
INT
VIL
t 2(APDR)
t 2(APDR)
t (APD)
Powerdown
(If Autopowerdown Is Set)
Powerdown
Figure 13. Dual Interrupt Conversion Mode
(Conversion can only be started with CSTART for the dual interrupt mode)
16
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TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
mono continuous mode (CR0.(3,2) = 1,0)
The mono continuous mode of conversion is synchronous with the RD signal. Its cycle time is approximately
5 SYSCLK cycles when an external SYSCLK is used (6 SYSCLK cycles when an internal SYSCLK is used).
In the mono continuous mode, the TLV1562 is always sampling the input regardless of the state of other control
signals when it is not in the hold state (the first half SYSCLK cycle after each falling edge of RD). This simplifies
control of the ADC. There is no need to generate any special signal to start the sampling.
VIH
CS
VIL
VIH
WR
VIL
t d(CSL-RDL)
t c(RD)
t w(RDL)
VIH
RD
VIL
t (CONV1)
t conv1
t conv1
CONV 1
t s5
CONV 2
t d(RDL-SAMPLE)
Sample 1
Config
Hi-Z
CONV 3
t s2
t s2
Sample 2
DATA
t conv1
t s2
Sample 3
Sample 4
t dis(DATAOUT)
t dis(DATAOUT)
Data 1
Data 2
V IH
V IL
t en(DATAOUT)
t en(DATAOUT)
Figure 14. Mono Continuous Mode
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TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
dual continuous mode (CR0.(3,2) = 1,1)
When the TLV1562 operates in the dual continuous mode, it samples and then holds two preselected channels
(differential or single ended) simultaneously as RD clocks. These samples are then converted in sequence. This
is designed to optimize the DSP MIPS for communication applications. Its cycle time is approximately 10
SYSCLK cycles when an external SYSCLK is used (12 SYSCLK cycles when an internal SYSCLK is used).
When operating in the dual continuous mode, the TLV1562 is always sampling the input regardless of the state
of the other control signals when it is not in the hold state. This simplifies control of the ADC. There is no need
to generate any special signal to start the sampling. The TLV1562 goes into hold mode on the odd number
(starting from the rising edge of WR) falling edge of RD for one SYSCLK clock cycle.
A two-depth FIFO is used (only in the dual continuous mode) to ensure the output correlation. Thus on every
alternate RD edge, the result of the previous two conversions is read out. This allows a slower RD clock
frequency (slower than 1/5 of the SYSCLK frequency). Each dual continuous mode cycle (while CS remains
active low) must have an even number of RD cycles to ensure the FIFO operates properly.
VIH
CS
VIL
WR
t c(RD)
t d(RDL-SAMPLE)
RD
t s5
tconv2
t conv2
CONV 1
t s3
Sample 1
t conv2
CONV 2
t s3
Sample 2
CONV 3
t s3
Sample 3
Sample 4
t dis(DATAOUT)
DATA
GFG
D 1A
D 1B
D 2A
D 2B
t en(DATAOUT)
Figure 15. Dual Continuous Mode
system clock source
The TLV1562 uses multiple clocks for different internal tasks. SYSCLK is used for most conversion subtasks.
The source of SYSCLK is programmable via control register 0, bit 5 (CR0.5). The source of SYSCLK is changed
at the rising edge of WR of the cycle when CR0.5 is programmed.
internal oscillator (CR0.5 = 0, SYSCLK = internal OSC)
The TLV1562 has a built-in 8-MHz oscillator. When the internal OSC is selected as the source of SYSCLK, the
internal clock starts with a delay (one half of the OSC clock period max) after the falling edge of the conversion
trigger (RD or CSTART).
18
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TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
external clock input (CR0.5 = 1, SYSCLK = External Clk)
The TLV1562 is designed to operate with an external clock input (CMOS/TTL) with a frequency from 100 kHz
to 14 MHz. When an external clock is used as the source of SYSCLK, the setup time from the falling edge of
RD to the rising edge of SYSCLK, ts(TRGL-ECLKH) is 5 ns minimum. The internal OSC is shut down when the
external clock mode is selected.
host processor interface
parallel processor interface
The TLV1562 provides a generic high-speed parallel interface that is compatible with high-performance DSPs
and general-purpose microprocessors. These include D(0,9), RD, WR, and INT. RD transitions from high to low
to signal the end of acquisition. The parallel I/O has its own power supply to minimize digital noise.
output data format
The output data format is unipolar binary (1023 to 0) when the device is operated in the single-ended input mode
and is bipolar (511 to –512) when the device is operated in differential input mode. The output code format can
be either binary or 2s compliment. The output data format is controlled by CR1.2.
power down
The device offers two different power-down modes: Auto power-down mode for interrupt-driven conversions
and software power-down mode for all conversion modes. All configuration information is kept intact when the
device is in software or auto power-down mode.
auto-power down for interrupt-driven conversion modes
When auto-power down is enabled, the device turns off the analog section (the converter except for the
reference network) at the falling edge of INT and resumes after the falling edge of CS (if RD is the conversion
trigger) or CSTART (if CSTART is the conversion trigger). The reference current and I/O are kept alive to ensure
a fast recovery. Average power consumption can be reduced by accessing the converter less often. Special
requirements for using this feature are:
D
D
It is necessary to toggle CS between cycles so the converter knows when to resume.
There is an additional delay to a conversion after the device is accessed due to the auto-power-down
control. Therefore, the time between RD (or CSTART) triggers is longer (longer RD or CSTART high time).
software power down (CR.10 = 1, software power down enabled)
In addition to the auto-power-down feature, the device has a software powerdown feature to further reduce
power consumption when the device is idle. Writing a 1 to control register bit CR1.0 puts the TLV1562 into
software power-down mode in 200 ns after CS is up. The device consumes less than 1 µA when in the
power-down mode. Writing a 0 to control register bit CR1.0 wakes up the device. Conversion can start 1 µs after
the device is resumed. CS must be high when the device is in power-down mode. Software power-down
operation is slower than auto-power down but is more flexible and consumes almost no power.
POST OFFICE BOX 655303
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TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
Table 4. TLV1562 Powerdown Features
FUNCTION BLOCK/POWERDOWN MODE
DIGITAL CONTROL VOLTAGE LEVEL
SOFTWARE POWERDOWN
AUTO POWERDOWN
CMOS
TTL
CMOS
TTL
Converter analog section
Inactive
Inactive
Inactive
Inactive
Reference current (amps)
Inactive
Inactive
Active
Active
Digital I/O buffers
Estimated supply current, ICC
Power-down time
Resume time
Active
active
Active
Active
1 µA
80 µA
120 µA
200 µA
200 ns
200 ns
200 ns
200 ns
1 µs
1 µs
700 ns
700 ns
Maximum throughput†
1.2/0.7 MSPS‡ 1.2/0.7 MSPS‡
1 MSPS
1 MSPS
† Dual interrupt, 10-bit, 5-V AVDD, 10-MHz external clock, and 2 V (REFP–REFM).
‡ This assumes the TLV1562 is software powered down between every cycle. In reality this is not the case since auto-power down makes much
more sense in this case. So the realistic maximum throughput for software power down will be close to the maximum throughput without
powerdown which is 1.2 MSPS for dual-interrupt mode (and 1.5 MSPS if mono-interrupt mode is used). But this really depends on how long the
device is powered down.
mid-scale error calibration
The device has a ±5% maximum full-scale error, mid-scale error, and zero-scale error due to the gain error in
the sample and hold amplifier.
The TLV1562 is capable of calibrating the mid-scale error. There are two calibration modes: system mid-scale
error calibration and internal mid-scale error calibration as described below.
NOTE:
Set register CR0.(7,6) = 1,1 when the device is not in mid-scale error calibration mode.
These mid-scale error calibrations affect the ADCs transfer characteristics as shown in Figure 16. The absolute
error at code 512 is zero-out (this is the reference point for mid-scale error calibration). The calibration also
makes the FS error and ZS error equal.
internal mid-scale error calibration (CR0.(7,6) = 1,0)
The internal mid-scale error calibration mode is set by writing to the configuration registers with CR0.(7,6) set
to 10. The ADC analog inputs are internally shorted to mid-voltage (REFP+REFM)/2 when the mid-scale error
calibration mode is enabled. One conversion (initiated by the falling edge of RD) is performed to calculate the
offset. The result of this conversion is stored in the mid-scale error register and is subtracted from all subsequent
conversions thus removing any offset. Internal calibration removes any offsets internal to the device. Internal
mid-scale error calibration reduces the mid-scale error to ±2.5% FS single ended inputs (0.3% FS differential
inputs).
system mid-scale error calibration (CR0.(7,6) = 0,1)
System mid-scale error calibration is set by writing to the configuration registers with CR0.(7,6) set to 01. The
analog input to be calibrated is externally connected to the voltage corresponding to mid-code. For differential
operation, this is achieved by shorting the two inputs together; for a single-ended input this is achieved by
connecting the analog input to the system mid-voltage, (SYSTEM_REFP + SYSTEM_REFM)/2. One
conversion (initiated by RD falling edge) is performed to calculate the offset. The result of this conversion is
stored in the mid-scale error register and is subtracted from all subsequent conversions thus removing any
offset. System mid-scale error calibration removes the offset of not only the ADC but any offsets in the entire
analog circuitry driving the ADC input. System mid-scale error calibration reduces the mid-scale error to ±0.4%
FS single ended inputs (0.25% FS differential inputs).
20
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TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
Code Output
Full-Scale Error
(Before Calibrayion)
Full-Scale Error
(After Calibration)
Ideal Transfer Function
Full Scale
Transfer Function After
Mid-Scale Calibration
Transfer Function Before
Mid-Scale Calibration
Mid Scale
Mid-Scale Error
(Before Calibration)
Mid-Scale Error
(After Calibration)
Zero Scale
Analog Input
V-Mid (REFCM)
REFM
REFP
Zero-Scale Error
(Before Calibration)
Zero-Scale Error
(After Calibration)
Figure 16. Mid-Scale Error Calibration
resume normal conversion from mid-scale error calibration modes
A follow on write operation sets CR0.(7,6) to 00 which resumes the normal conversion mode. Typically
mid-scale error calibration needs to be performed only once after power up. If however the operation mode is
changed from single ended to differential, then preferably mid-scale error calibration should be performed
again.
The user writes a bit to enable mid-scale error calibration. Inputs to the ADC are internally shorted therefore
the offset value can be converted to a digital word. The result (a digital word representing the offset) is stored
in a latch. This offset value is then subtracted from the digital output of all conversions except when in mid-scale
error calibration mode.
system design consideration regarding to mid-scale error calibration
Mid-scale error calibration may limit the dynamic range of the ADC. If the offset is negative and has a magnitude
x, then the range of the converter codes is x to 1023. If the offset is positive and has a magnitude of x, then the
range of converter codes is 1 to 1023 –x. Thus the ADCs dynamic range is reduced by x (say x = 20 codes) on
either side of the range effectively with mid-scale error calibration. However this should not be a limitation for
most users.
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21
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
APPLICATION INFORMATION
2.7 V
10 kΩ
Address Decoder
and Control
TMS320C541
10 kΩ
10 kΩ
10 kΩ
DVDD AVDD BDVDD
CS
A15
WR
WR
A14
R/W
IS
RD
SYSCLK/5
DSPCLK
MODE
DSPINT
CSTART
MUX
CS
CH1
SIG 1
CH3
SIG 2
RD
TLV1562
CSTART
INT
INT
SYSCLK
CLKIN
10
PD(0–9)
D(0–9)
DGND AGND BDGND
Figure 17. Typical Interface to a TMS320 DSP
22
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REF
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
APPLICATION INFORMATION
WR
RD
CH0
Sig 1
CH2
Sig 2
1562 #1
CSTART
RD
WR
INT 1
10
PD(0–9)
WR
RD
C541
CS0
A0
A1
CH0
Sig 3
CH2
Sig 4
#2
CSTART
CS1
INT 2
CS2
WR
B I/O
(CSTART)
RD
#3
CH0
Sig 5
CSTART
Set #3 in Single Interrupt Mode
Set #1 and #2 in Dual Interrupt Mode (New Mode)
Select (Separate RD Cycle option in Req Z for #1, #2, #3
CS
INT 3
Figure 18. Multiple Chips Simultaneous Sampling/Conversion Application
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TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
APPLICATION INFORMATION
VIH
CS0
VIL
VIH
CS2
VIL
VIH
CS1
VIL
VIH
RD
VIL
ten(DATAOUT)
PD(0–9)
tdis(DATAOUT)
VIH
Hi-Z
D Sig1
D Sig2
D Sig3
D Sig4
D Sig5
VIL
VIH
CSTART
VIL
ts4
tconv2
Pullup
VIH
INT1
Pullup
INT2
VIL
VIH
VIL
Pullup
VIH
INT3
< = 0.2 µs × 5
0.1 µs
† If CLK = 10 MHz
Figure 19. Multiple Chips Simultaneous Sampling/Conversion Application System Timing
24
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VIL
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range: AVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
BDVDD, DVDD (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
AVDD to DVDD or BDVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –6.5 V to 6.5 V
Voltage range between AGND and DGND or BDGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 0.5 V
Digital input voltage range, CLKIN, CS, WR, RD, CSTART (see Note 2) . . . . . . . . . . . –0.3 V to DVDD +0.3 V
Digital data input voltage range (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DVDD +0.3 V
Digital data output voltage range (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DVDD +0.3 V
Analog output voltage range, INT (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.1 V to AVDD+ 0.1 V
Reference input voltage range, REFP (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.1 V to AVDD+ 0.1 V
Reference input voltage range, REFM (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 0.3 V
Peak input current (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Peak total input current (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA
Operating free-air temperature range, TA: TLV1562C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0°C to 70°C
TLV1562I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Measured with respect to AGND with REF – and GND wired together (unless otherwise noted).
2. Measured with respect to DGND.
recommended operating conditions
PARAMETERS
MIN
Supply voltage, AVDD, BDVDD, DVDD (see Note 3)
2.7
NOM
MAX
5.5
UNIT
V
Positive external reference voltage input, VREFP (see Note 4)
AGND +1.7
V
Negative external reference voltage input, VREFM (see Note 4)
AGND +0.9
AVDD – 1
AVDD – 1
V
0.8
MIN of
AVDD – 1.9
or 3
V
VREFM
VREFP
V
0.8
3
V
Common mode analog input voltage, (AINP+AINM)/ 2
AGND
V
External SYSCLK 40/60 cycle time, tc(EXTSYSCLK)
0.067
AVDD
1
Differential reference voltage input, (VREFP–VREFM) (see Note 4)
Single-ended analog input voltage, (AIN – AGND) (see Note 4)
Differential analog input voltage, (AINP–AINM)
µs
External SYSCLK pulse duraton high, twH(EXTSYSCLK)
40%
60%
tc(EXT
SYSCLK)
External SYSCLK pulse duration low, twL(EXTSYSCLK)
40%
60%
tc(EXT
SYSCLK)
High-level digital and control input voltage, VIH
2.1
Low-level digital and control input voltage, VIL
Operating free-air
free air temperature,
temperature TA
V
0.8
TLV1562C
TLV1562I
0
70
–40
85
V
°C
NOTES: 3. The absolute difference between AVDD, BDVDD and DVDD should be less than 0.5 V.
4. Analog input voltages greater than that applied to VREFP convert as all ones (111111111111), while input voltages less than that
applied to VREFM convert as all zeros (000000000000).
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
electrical characteristics over recommended operating free-air temperature range, differential
input, AVDD = DVDD =BDVDD = 3 V, VREFP – VREFM = 1 V, external SYSCLK = 10 MHz
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
Digital high-level
high level output voltage
BDVDD = 5.5 V,
BDVDD = 2.7 V,
VOL
Digital low-level
low level output voltage
BDVDD = 5.5 V,
BDVDD = 2.7 V,
IOL = 0.8 mA
IOL = 20 µA
IOZ
Off-state output current
(high-impedance state)
VO = BDVDD,
VO = BDGND,
VI = BDVDD
CS = BDVDD
IIH
IIL
High-level input current
Low-level input current
Total operating
g supply
y current,, ((from
AVDD, DVDD, and BDVDD)
IDD
Total auto-powerdown supply
y current
(from AVDD, DVDD, and BDVDD)
Total S/W powerdown supply
y current
(from AVDD, DVDD, and BDVDD)
IOH = –0.2 mA
IOH = –20 µA
CS = BDVDD
MIN
V
0.4
0.1
0.005
–1
V
µA
0.005
1
µA
–0.005
1
µA
8.5
11
5
7
85
120
mA
AVDD = 2.7 V,
CS at BDGND,
AVDD = 5.5 V,
SYSCLK = 10 MHz,
CMOS control level, Auto powerdown = 1
µA
CS at BDGND,
AVDD = 5.5 V,
SYSCLK = 10 MHz,
TTL control level, Auto powerdown = 1
200
300
CS at BDGND,
AVDD = 5.5 V,
SYSCLK = 10 MHz,
CMOS control level, S/W powerdown = 1
0.2
1
CS at BDGND,
AVDD = 5.5 V,
SYSCLK = 10 MHz,
TTL control level, S/W powerdown = 1
60
µA
80
0.25
1
Selected channel at AGND
0.25
–1
Maximum static analog reference
current into REFP
VREFP = AVDD – 1.9 V, AVDD = 5.5 V,
VREFM = AGND + 0.9 V, SYSCLK = 10 MHz
150
180
µA
Reference input impedance
VDD = 5.5 V, CS = 0,
25
30
kΩ
5
pF
SCLK = 10 MHz
Analog inputs fixed
Input capacitance
17
Input MUX ON resistance
9
0.5
1
Control inputs
20
25
VDD = 5.5 V
VDD = 2.7 V
POST OFFICE BOX 655303
0.5
1
• DALLAS, TEXAS 75265
µA
10
Analog inputs switching
† All typical values are at VDD = 5 V, TA = 25°C.
26
1
–0.005
Output capacitance
RON
UNIT
Selected channel at AVDD
Selected channel leakage current
Ci
MAX
BDVDD–0.1
VI = BDGND
CS at BDGND,
AVDD = 5.5 V,
SYSCLK = 10 MHz
CS at BDGND,
SYSCLK = 8 MHz
TYP
2.4
pF
kΩ
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
timing requirements
PARAMETER
TEST CONDITIONS
Delay time, CS↓ to WR↓, td(CSL–WRL)
MIN
TYP
2
MAX
4
UNIT
ns
Delay time, RD↑ to CSTART↓, td1(RDH – CSTARTL)
100
ns
Delay time, RD↑ to CSTART↓, td2(RDH – CSTARTL)
300
ns
Delay time, WR↑ to CSTART↓, td1(WRH – CSTARTL)
100
ns
Delay time, WR↑ to CSTART↓, td2(WRH – CSTARTL)
300
Delay time, CS↓ to RD↓, td(CSL–RDL)
ns
2
Pulse duration, CS high, tw(CSH)
Setup time, data valid to WR↑, tsu(DATAIN)
Hold time, WR↑ to data invalid, th(DATAIN)
Interrupt modes
duration RD low,
low tw(RDL)
Pulse duration,
(RDL)
Continuous modes
Pulse duration, WR low, tw(WRL)
4
ns
50
ns
5
ns
10
ns
50
ns
200
ns
50
ns
Delay time, WR↑ to CS↑, td(WRH–CSH)
4
ns
Delay time, RD↑ to CS↑, td(RDH–CSH)
4
ns
Delay time, external SYSCLK↓ to RD↓, CSTART↑, td(ECLKL–TRGL)
0
2
ns
Setup time, RD↓, CSTART↑, to external SYSCLK↑, tsu(TRGL–ECLKH)
5
6
ns
Pulse duration
duration, CSTART low,
low tw(CSTARTL)
(CSTARTL)
Auto power down = 1
800
Auto power down = 0
100
Delay time, INT↓ to CS↓, td(INTL–CSL)
ns
10
External SYSCLK, 10 bit
ns
5
5.5
4
4.5
Internal SYSCLK, 10 bit
6
External SYSCLK, 8 bit
time mono continuous/interrupt mode
Conversion time,
mode, tconv1
1
Internal SYSCLK, 8 bit
5
External SYSCLK, 4 bit
2
2.5
10
11
Internal SYSCLK, 4 bit
3
External SYSCLK, 10 bit
Internal SYSCLK, 10 bit
12
External SYSCLK, 8 bit
Conversion time,
time dual continuous/interrupt mode
mode, tconv2
2
8
Internal SYSCLK, 8 bit
9
10
External SYSCLK, 4 bit
4
5
External SYSCLK, 10 bit
5
5.5
Internal SYSCLK, 10 bit
6
External SYSCLK, 8 bit
4
Internal SYSCLK, 8 bit
5
External SYSCLK, 4 bit
2
Internal SYSCLK, 4 bit
3
Internal SYSCLK, 4 bit
Cycle time,
time continuous mode RD,
RD tc(RD)
(RD)
SYSCLK
SYSCLK
6
4.5
SYSCLK
2.5
Mono interrupt mode sampling time or first cycle (mono interrupt or
continous mode) sampling time, ts1
0.2
1000
µs
Dual interrupt mode sampling time or first cycle (dual interrupt or continuous
mode) sampling time, ts4
0.3
1000
µs
Mono continuous mode sampling time, ts2
Dual continuous mode sampling time, ts3
Continuous mode first sampling time, t(SAMPE5)
SYSCLK
7
SYSCLK
µs
0.45
Data rise time, tr(DATAOUT)
3
POST OFFICE BOX 655303
3
• DALLAS, TEXAS 75265
5
10
ns
27
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
timing requirements (continued)
MIN
TYP
MAX
Data fall time, tf(DATAOUT)
PARAMETER
TEST CONDITIONS
2
4
8
UNIT
ns
Control signal rise time, RD, RW, CSTART, CS, and DATA, tr(I/O)
2
1000
ns
Control signal fall time, RD, RW, CSTART, CS, and DATA, tf(I/O)
2
1000
ns
operating characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
fI = 800 kHz at 10 bit 2 MSPS, AVDD = 5 V, VREFP = 3.5 V
VREFM = 1.5 V, mono continuous
fI = 800 kHz at 10 bit 2.5 MSPS, AVDD = 5 V, VREFP = 3.5 V,
VREFM = 1.5 V, mono continuous
g linearityy error,, center best fit
Integral
(see Note 5)
–1.5
±0.6
±1
±0.85
±1.5
±1.5
fI = 800 kHz at 10 bit 2 MSPS, AVDD = 3 V, VREFP = 1.7 V,
VREFM = 0.9 V, mono continuous
±0.6
±1
fI = 800 kHz at 8 bit 3 MSPS, AVDD = 3 V, VREFP = 1.7 V,
VREFM = 0.9 V, mono continuous
±0.6
±1
±0.65
±1
±1
fI = 800 kHz at 4 bit 7 MSPS, AVDD = 3 V, VREFP = 1.7 V,
VREFM = 0.9 V, mono continuous
±0.2
±0.4
fI = 800 kHz at 10 bit 2 MSPS, AVDD = 5 V, VREFP = 3.5 V,
VREFM = 1.5 V, mono continuous
±0.5
±1
±0.5
1.5
fI = 800 kHz at 10 bit 2.8 MSPS, AVDD = 5 V,
VREFP = 3.5 V, VREFM = 1.5 V, mono continuous
±0.9
1.5
fI = 800 kHz at 10 bit 2 MSPS, AVDD = 3 V, VREFP = 1.7 V,
VREFM = 0.9 V, mono continuous
±0.6
±1
fI = 800 kHz at 8 bit 3 MSPS, AVDD = 3 V, VREFP = 1.7 V,
VREFM = 0.9 V, mono continuous
±0.5
±1
±0.5
1
±1
1
±0.2
±0.4
fI = 800 kHz at 10 bit 2.5 MSPS, AVDD = 5 V,
VREFP = 3.5 V, VREFM = 1.5 V, mono continuous
fI = 800 kHz at 8 bit 3.5 MSPS, AVDD = 3 V, VREFP = 1.7 V,
VREFM = 0.9 V, mono continuous
–0.85
LSB
–0.8
fI = 800 kHz at 8 bit 3.75 MSPS, AVDD = 5 V,
VREFP = 3.5 V, VREFM = 1.5 V, mono continuous
fI = 800 kHz at 4 bit 7 MSPS, AVDD = 3 V, VREFP = 1.7 V,
VREFM = 0.9 V, mono continuous
NOTE 5: Linear error is the maximum deviation from the best straight line through the A/D transfer characteristics.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
LSB
fI = 800 kHz at 8 bit 3.75 MSPS, AVDD = 5 V,
VREFP = 3.5 V, VREFM = 1.5 V, mono continuous
28
MAX
fI = 800 kHz at 10 bit 2.8 MSPS, AVDD = 5 V,
VREFP = 3.5 V, VREFM = 1.5 V, mono continuous
fI = 800 kHz at 8 bit 3.5 MSPS, AVDD = 3 V, VREFP = 1.7 V,
VREFM = 0.9 V, mono continuous
Differential linearity error
NOM
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
operating characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
MIN
NOM
UNIT
±0.4
After system calibration, single-ended input
Mid-scale error (see Note 6)
MAX
±5
Before calibration
±0.25
After system calibration, differential input
After internal calibration, single-ended input
±2.5
After internal calibration, differential input
±0.3
%FS
Offset error (see Note 6)
Before calibration
±5
%FS
Gain error (see Note 6)
Before calibration
±5
%FS
Total unadjusted error (see Note 7)
Before calibration
±5
%FS
Delay time, RD↓, CSTART↑ to external
SYSCLK↑, td(TRGL–ICLKH)
2ns
0.5 SYSCLK
Delay time, RD↓ to start of conversion
td(RDL–CONV1)
2
Internal OSC frequency
Delay time, RD↑ to INT↑, td(RDH–INTZ)
Disable time,, RD↑
↑ to data invalid,,
tdis(DATAOUT)
Enable time,, INT↓
↓ to data valid,,
ten(DATAOUT)
7.5
MHz
1-kΩ pullup resistor, 10 pF, BDVDD = 5 V, use RD
10
At 25 pF, BDVDD = 5 V
4
At 50 pF, BDVDD = 5 V
5
At 100 pF, BDVDD = 5 V
7
At 25 pF, BDVDD = 2.7 V
7
At 50 pF, BDVDD = 2.7 V
10
At 100 pF, BDVDD = 2.7 V
14
At 25 pF, BDVDD = 5 V
20
At 50 pF, BDVDD = 5 V
25
At 100 pF, BDVDD = 5 V
30
At 25 pF, BDVDD = 2.7 V
37
At 50 pF, BDVDD = 2.7 V
41
At 100 pF, BDVDD = 2.7 V
Delayy time,, mono interrupt mode power-up time, t1(APDR)
700
Auto powerdown = 0
0
Delayy time,, dual interrupt mode powerup time, t2(APD)
Auto powerdown = 1
1000
Auto powerdown = 0
0
Auto powerdown = 1
200
Auto powerdown = 0
0
Delay time, end of conversion to INT↓,
td(CONV-INTL)
Delay time, RD↓ to INT Hi-Z,
td(RDL-INTZ)
ns
ns
ns
56
Auto powerdown = 1
Delay time
time, INT↓ to powerdown,
powerdown t(APD)
ns
ns
ns
ns
5
1-kΩ pullup resistor, 10 pF, BDVDD = 5 V, Use CSTART
Delay time, CSTART↑ to start of conversion 1, td1(CSTARTH-CONV)
2
Delay time, CSTART↑ to start of conversion 2, td2(CSTARTH-CONV)
0.2
10
ns
10
ns
4
ns
1000
µs
Delay time, RD↓ to sample,
2
SYSCLK
td(RDL-SAMPLE)
NOTES: 6. Zero error is the difference between 000000000000 and the converted output for zero input voltage: full-scale error is the difference
between 111111111111 and the converted output for full-scale input voltage
7. Total unadjusted error comprises linearity, zero, and full-scale errors
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
29
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
operating characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
ac specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
10-Bit Mode
ENOB
THD
SNR
SINAD
SFDR
Effective number of bits
Total harmonic distortion
Signal to noise ratio
Signal-to-noise
Signal to noise ratio +distortion
Signal-to-noise
Spurious free dynamic range
fI = 800 kHz, at 10 bit 2 MSPS, AVDD = 5 V,
VREFP = 3.5 V, VREFM = 1.5 V, Mono continuous
8.97
9.4
fI = 800 kHz, at 10 bit 1.6 MSPS, AVDD = 3 V,
VREFP = 1.7 V, VREFM = 0.9 V, Mono continuous
8.8
8.91
Bits
fI = 800 kHz, at 10 bit 2 MSPS, AVDD = 5 V,
VREFP = 3.5 V, VREFM = 1.5 V, Mono continuous
–68.8
–64.5
fI = 800 kHz, at 10 bit 1.6 MSPS, AVDD = 3 V,
VREFP = 1.7 V, VREFM = 0.9 V, Mono continuous
–66.8
–64.5
dB
fI = 800 kHz, at 10 bit 2 MSPS, AVDD = 5 V,
VREFP = 3.5 V, VREFM = 1.5 V, Mono continuous
56.4
58.1
fI = 800 kHz, at 10 bit 1.6 MSPS, AVDD = 3 V,
VREFP = 1.7 V, VREFM = 0.9 V, Mono continuous
54.4
55.6
fI = 800 kHz, at 10 bit 2 MSPS, AVDD = 5 V,
VREFP = 3.5 V, VREFM = 1.5 V, Mono continuous
56.2
57.8
fI = 800 kHz, at 10 bit 1.6 MSPS, AVDD = 3 V,
VREFP = 1.7 V, VREFM = 0.9 V, Mono continuous
54.2
55.3
dB
dB
fI = 800 kHz, at 10 bit 2 MSPS, AVDD = 5 V,
VREFP = 3.5 V, VREFM = 1.5 V, Mono continuous
–70.3
–67.5
fI = 800 kHz, at 10 bit 1.6 MSPS, AVDD = 3 V,
VREFP = 1.7 V, VREFM = 0.9 V, Mono continuous
–69.1
–66.5
fI = 800 kHz, at 8 bit 3 MSPS, AVDD = 3 V,
VREFP = 1.7 V, VREFM = 0.9 V, Mono continuous
7.93
Bits
dB
8-Bit Mode
ENOB
Effective number of bits
THD
Total harmonic distortion
–64
dB
SNR
Signal-to-noise ratio
49.2
dB
SINAD
Signal-to-noise ratio +distortion
49
dB
SFDR
Spurious free dynamic range
–65
dB
3.97
Bits
–29
dB
4-Bit Mode
fI = 800 kHz, at 4 bit 7 MSPS, AVDD = 3 V,
VREFP = 1.7 V, VREFM = 0.9 V, Mono continuous
ENOB
Effective number of bits
THD
Total harmonic distortion
SINAD
Signal-to-noise ratio + distortion
26
dB
SINAD
Signal-to-noise ratio + distortion
24
dB
SFDR
Spurious free dynamic range
–30.5
dB
68
dB
Full-power bandwidth, –3 dB
120
MHz
Full-power bandwidth, –1 dB
75
MHz
Analog input
Cross talk rejection
30
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
INL – Integral Nonlinearity Error – LSB
TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
1
10-Bit Resolution,
VREF = 3.5 V–1.5 V,
SYSCLK = 10 MHz
0.5
0
–0.5
–1
0
511
1023
Digital Output Code
INL – Integral Nonlinearity Error – LSB
Figure 20
INTEGRAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
1
8-Bit Resolution,
VREF = 4 V–1 V,
SYSCLK = 12 MHz
0.5
0
–0.5
–1
0
127
255
Digital Output Code
Figure 21
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
31
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
INL – Integral Nonlinearity Error – LSB
TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
1
4-Bit Resolution,
VREF = 4 V–1 V,
SYSCLK = 14 MHz
0.5
0
–0.5
–1
0
7
15
Digital Output Code
DNL – Differential Nonlinearity Error – LSB
Figure 22
DIFFERENTIAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
1
10-Bit Resolution, VREF = 3.5 V–1.5 V,
SYSCLK = 10 MHz
0.5
0
–0.5
–1
0
511
Digital Output Code
Figure 23
32
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1023
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
DNL – Differential Nonlinearity Error – LSB
TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
1
8-Bit Resolution, VREF = 4 V–1 V,
SYSCLK = 12 MHz
0.5
0
–0.5
–1
0
127
255
Digital Output Code
DNL – Differential Nonlinearity Error – LSB
Figure 24
DIFFERENTIAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
1
8-Bit Resolution,
VREF = 4 V–1 V,
SYSCLK = 14 MHz
0.5
0
–0.5
–1
0
7
15
Digital Output Code
Figure 25
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
33
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
INL – Integral Nonlinearity Error – LSB
TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
1
10-Bit Resolution, AVDD = 2.7 V,
VREF = 1.7 V–0.9 V, SYSCLK = 10 MHz
0.5
0
–0.5
–1
0
511
1023
Digital Output Code
DNL – Differential Nonlinearity Error – LSB
Figure 26
DIFFERENTIAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
1
8-Bit Resolution, AVDD = 3 V,
VREF = 1.7 V–0.9 V, SYSCLK = 10 MHz
0.5
0
–0.5
–1
0
127
Digital Output Code
Figure 27
34
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TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
DNL – Differential Nonlinearity Error – LSB
TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
1
8-Bit Resolution, AVDD = 2.7 V,
VREF = 1.7 V–0.9 V, SYSCLK = 14 MHz
0.5
0
–0.5
–1
0
7
15
Digital Output Code
DNL – Differential Nonlinearity Error – LSB
Figure 28
DIFFERENTIAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
1
10-Bit Resolution, AVDD = 2.7 V, VREFP = 1.7 V,
VREFM = 0.9 V, Internal Clock
0.5
0
–0.5
–1
0
511
1023
Digital Output Code
Figure 29
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TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
DNL – Differential Nonlinearity Error – LSB
TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
1
8-Bit Resolution, AVDD = 2.7 V, REFP = 1.7 V, REFM = 0.9 V, 12 MHz
External Clock
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
0
127
255
Digital Output Code
DNL – Differential Nonlinearity Error – LSB
Figure 30
DIFFERENTIAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
1
0.8
0.6
4-Bit Resolution, AVDD = 2.7 V, REFP = 1.7 V, REFM = 0.9 V, 14 MHz
External Clock
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
0
7
Digital Output Code
Figure 31
36
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TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
TYPICAL CHARACTERISTICS
TYPICAL SUPPLY CURRENT
vs
FREQUENCY
TYPICAL POWER DOWN CURRENT
vs
TEMPERATURE
16
100
AVDD = 5.5 V at 90°C
12
80
AVDD = 5.5 V
Total Current – µ A
Typical Supply Current – mA
14
10
AVDD = 2.7 V
8
6
AVDD = 5.5 V at 25°C
AVDD = 5.5 V at 40°C
60
AVDD = 3 V at 40°C
40
4
20
2
0
0
2
4
7
10
12
15
0
20
f – Clock Frequency – MHz
T – Temperature – °C
Figure 32
Figure 33
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY
SIGNAL TO NOISE
vs
INPUT FREQUENCY
–68.5
61
–69
60
–69.5
AVDD = 5 V, VREF+ = 3.5 V, VREF = 1.5 V
–70
–70.5
AVDD = 5 V, VREF+ = 4 V, VREF = 1.5 V
–71
59
SNR – Magnitude – dB
SFDR – Magnitude – dB
AVDD = 5 V, VREF+ = 4 V, VREF = 1 V
AVDD = 5 V, VREF+ = 3.5 V, VREF = 1.5 V
58
57
56
AVDD = 3 V, VREF+ = 2 V, VREF = 1 V
55
–71.5
–72
54
AVDD = 3 V, VREF+ = 2 V, VREF = 1 V
–72.5
50 100 200 300 400 500 600 700 800 900 1000
53
50 100 200 300 400 500 600 700 800 900 1000
Analog Input Frequency – kHz
Analog Input Frequency – kHz
Figure 34
Figure 35
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2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
TYPICAL CHARACTERISTICS
SIGNAL TO NOISE HARMONIC DISTORTION
vs
INPUT FREQUENCY
EFFECTIVE NUMBER OF BITS
vs
INPUT FREQUENCY
61
59
AVDD = 5 V, VREF+ = 4 V, VREF = 1 V
9.6
AVDD = 5 V, VREF+ = 3.5 V, VREF = 1.5 V
Effective Number of Bits
SINAD – Magnitude – dB
60
9.8
AVDD = 5 V, VREF+ = 4 V, VREF = 1 V
58
57
56
AVDD = 3 V, VREF+ = 2 V, VREF = 1 V
55
AVDD = 5 V, VREF+ = 3.5 V, VREF = 1.5 V
9.4
9.2
9
AVDD = 3 V, VREF+ = 2 V, VREF = 1 V
8.8
54
8.6
53
50 100 200 300 400 500 600 700 800 900 1000
8.4
50 100 200 300 400 500 600 700 800 900 1000
Analog Input Frequency – kHz
Analog Input Frequency – kHz
Figure 36
Figure 37
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
–67
THD – Magnitude – dB
–67.5
–68
AVDD = 3 V, VREF+ = 2 V, VREF = 1 V
–68.5
–69
–69.5
AVDD = 5 V, VREF+ = 4 V, VREF = 1 V
–70
AVDD = 5 V, VREF+ = 3.5 V, VREF = 1.5 V
–70.5
50 100 200 300 400 500 600 700 800 900 1000
Analog Input Frequency – kHz
Figure 38
38
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2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
APPLICATION INFORMATION
1023
1111111111
See Notes A and B
1111111110
1022
1111111101
1021
VFT = VFS – 1/2 LSB
1000000001
513
512
1000000000
VZT = VZS + 1/2 LSB
Step
Digital Output Code
VFS
511
0111111111
VZS
0000000001
1
0000000000
0
0.0048
0.0096
2.4528
2.4576
2.4624
4.9056
4.9080
2
0.0024
0000000010
4.9104
0
4.9152
VI – Analog Input Voltage – V
NOTES: A. This curve is based on the assumption that Vref + and Vref – have been adjusted so that the voltage at the transition from digital 0
to 1 (VZT) is 0.0024 V and the transition to full scale (VFT) is 4.908 V. 1 LSB = 4.8 mV.
B. The full-scale value (VFS) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (VZS) is
the step whose nominal midstep value equals zero.
Figure 39. Ideal 12-Bit ADC Conversion Characteristics
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