WM2614 Quad 12-bit Serial Input Voltage Output DAC Production Data, June 1999, Rev 1.0 FEATURES • • • • • • DESCRIPTION Quad 12-bit DAC voltage output DAC Dual 2.7V to 5.5V supply (separate digital and analogue supplies) DNL ± 0.4 LSB, INL ± 1.5 LSB Low power consumption: 5.5mW, slow mode − 5V supply 3.3mW, slow mode − 3V supply TMS320, (Q)SPI , and Microwire compatible serial interface Programmable settling time of 4µ µ s or 12µ µ s typical APPLICATIONS • • • • • • • Battery powered test instruments Digital offset and gain adjustment Battery operated/remote industrial controls Machine and motion control devices Wireless telephone and communication systems Speech synthesis Arbitrary waveform generation ORDERING INFORMATION DEVICE TEMP. RANGE PACKAGE WM2614CDT 0° to 70°C 16-pin TSSOP WM2614IDT -40° to 85 °C 16-pin TSSOP BLOCK DIAGRAM The WM2614 is a quadruple 12-bit voltage output, resistor string, digital-to-analogue converter. Each DAC can be individually powered down under software control. A hardware controlled mode is provided that powers down all DACs. Power down reduces current consumption to 10nA. The device has been designed to interface efficiently to industry standard microprocessors and DSPs, including the TMS320 family. The WM2614 is programmed with a 16-bit serial word comprising of a DAC address, individual DAC control bits and a 12-bit value. The WM2614 has provision for two supplies: one supply for the serial interface (DVDD, DGND) and one for the DACs, reference buffers and output buffers (AVDD, AGND). This enables a typical application where the device can be controlled via a microprocessor operating on a 3V supply, with the DACs operating on a 5V supply. Alternatively, the supplies can be tied together in a single supply application. Excellent performance is delivered with a typical DNL of 0.4 LSBs. The settling time of the DAC is programmable to allow the designer to optimize speed versus power dissipation. The output stage is buffered by a x2 gain near rail-to-rail amplifier, which features a Class AB output stage. DACs A and B can have a different reference voltage to DACs C and D. The device is available in a 16-pin TSSOP package. Commercial temperature (0° to 70°C) and Industrial temperature (-40° to 85°C) variants are supported. TYPICAL PERFORMANCE AVDD (16) DVDD (1) REFINAB (15) REFINCD (10) 1 DAC A REFERENCE INPUT BUFFER AVDD = DVDD = 5V, VREF = 2.048V, Speed = Fast mode, Load = 10k/100pF 0.8 X1 DIN (4) data FS (7) SCLK (5) 16-BIT SHIFT REGISTER AND CONTROL LOGIC NCS (6) 14-BIT DATA AND CONTROL HOLDING LATCH 12-BIT DAC LATCH DAC OUTPUT BUFFER X2 0.6 (14) OUTA 0.4 0.2 2-BIT CONTROL LATCH DNL (LSB) WM2614 POWERDOWN/ SPEED CONTROL 0 -0.2 DAC B (13) OUTB -0.4 DAC C (12) OUTC -0.6 DAC D (11) OUTD POWER-ON RESET -0.8 -1 (9) AGND (8) DGND (3) NLDAC (2) NPD WOLFSON MICROELECTRONICS LTD Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: [email protected] http://www.wolfson.co.uk 0 512 1024 1536 2048 2559 3071 3583 4095 DIGITAL CODE Production Data Datasheets contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronics’ terms and conditions. 2614Mastera.doc June 18, 1999 14:36 1999 Wolfson Microelectronics Ltd. WM2614 Production Data Rev 1.0 PIN CONFIGURATION DVDD 1 16 AVDD NPD 2 15 REFINAB NLDAC 3 14 OUTA DIN 4 13 OUTB SCLK 5 12 OUTC NCS 6 11 OUTD FS 7 10 REFINCD DGND 8 9 AGND PIN DESCRIPTION PIN NO NAME TYPE 1 DVDD Supply DESCRIPTION 2 NPD Digital input Power down. Powers down all DACs overriding their individual power down settings and all output stages. This pin is active low. 3 NLDAC Digital input Load DAC. Digital input active low. NLDAC must be taken low to update the DAC latch from the holding latches. Digital supply. 4 DIN Digital input Serial data input. 5 SCLK Digital input Serial clock input. 6 NCS Digital input Chip select. This pin is active low. 7 FS Digital input Frame synchronisation for serial output data. 8 DGND Ground 9 AGND Ground 10 REFINCD Analogue input Voltage reference input for DACs C and D. 11 OUTD Analogue output DAC D output. 12 OUTC Analogue output DAC C output. 13 OUTB Analogue output DAC B output. 14 OUTA Analogue output DAC A output. 15 REFINAB Analogue input Voltage reference input for DACs A and B. 16 AVDD Supply Digital ground. Analogue ground. Analogue supply. ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. CONDITION MIN MAX Supply voltage differences, AVDD to DVDD -2.8V 2.8V Digital input voltage -0.3V DVDD + 0.3V Reference input voltage -0.3V AVDD + 0.3V WM2614CDT 0°C 70°C WM2614IDT -40°C 85°C -65°C 150°C Supply voltages, DVDD to DGND, AVDD to AGND Operating temperature range, TA Storage temperature Lead temperature 1.6mm (1/16 inch) soldering for 10 seconds WOLFSON MICROELECTRONICS LTD 7V 260°C Production Data Rev 1.0 June 1999 2 WM2614 Production Data Rev 1.0 RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL Supply voltage AVDD, DVDD TEST CONDITIONS MIN TYP 2.7 MAX UNIT 5.5 V High-level digital input voltage VIH DVDD = 2.7V to 5.5V Low-level digital input voltage VIL DVDD = 2.7V to 5.5V 0.8 V VREF See Note AVDD - 1.5 V Reference voltage to REFINAB, REFINCD 2 V Load resistance RL Load capacitance CL 100 pF fSCLK 20 MHz Serial clock rate Operating free-air temperature Note: TA 2 10 kΩ WM2614CDT 0 70 °C WM2614IDT -40 85 °C Reference voltages greater than AVDD/2 will cause output saturation for large DAC codes. WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999 3 WM2614 Production Data Rev 1.0 ELECTRICAL CHARACTERISTICS Test Conditions: RL = 10kΩ, CL = 100pF. AVDD = DVDD = 5V ± 10%, VREF = 2.048V and AVDD = DVDD = 3V ± 10%, VREF = 1.024V over recommended operating free-air temperature range (unless noted otherwise). PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Static DAC Specifications Resolution 12 bits Integral non-linearity INL See Note 1 ± 1.5 ±4 LSB Differential non-linearity DNL See Note 2 ± 0.4 ±1 LSB Zero code error ZCE See Note 3 3 ± 12 mV GE See Note 4 0.25 ± 0.6 % FSR d.c. PSRR See Note 5 0.5 mV/V Zero code error temperature coefficient See Note 6 10 ppm/°C Gain error temperature coefficient See Note 6 10 ppm/°C Gain error D.c. power supply rejection ratio DAC Output Specifications Output voltage range 0 Output load regulation 2kΩ to 10kΩ load 0.1 AVDD - 0.1 V 0.25 % See Note 7 Power Supplies Active supply current IDD No load, VIH = DVDD, VIL = 0V mA AVDD = 5V, VREF = 2.048V Slow 1.6 2.4 AVDD = 5V, VREF = 2.048V Fast 3.8 5.6 AVDD = 3V, VREF = 1.024V Slow 1.2 1.8 AVDD = 3V, VREF = 1.024V Fast 3.2 4.8 0.01 10 See Note 8 Power down supply current No load, all digital inputs 0V or DVDD µA See Note 9 Dynamic DAC Specifications Slew rate DAC code 128 to 4095, 10%-90% Slow 0.5 1.0 V/µs Fast 2.5 4.0 V/µs Slow 12.0 µs Fast 4.0 µs 10 nV-s 66 74 dB 54 66 dB See Note 10 Settling time DAC code 128 to 4095 See Note 11 Glitch energy Signal to noise ratio Code 2047 to 2048 SNR fs = 400ksps, fOUT = 1kHz, BW = 20kHz, SNRD fs = 400ksps, fOUT = 1kHz, BW = 20kHz, THD fs = 400ksps, fOUT = 1kHz, BW = 20kHz, SPFDR fs = 400ksps, fOUT = 1kHz, BW = 20kHz, See Note 12 Signal to noise and distortion ratio See Note 12 Total harmonic distortion -68 -56 dB See Note 12 Spurious free dynamic range 56 70 dB See Note 12 WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999 4 WM2614 Production Data Rev 1.0 Test Conditions: RL = 10kΩ, CL = 100pF. AVDD = DVDD = 5V ± 10%, VREF = 2.048V and AVDD = DVDD = 3V ± 10%, VREF = 1.024V over recommended operating free-air temperature range (unless noted otherwise). PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Reference Reference input resistance RREFIN 10 MΩ Reference input capacitance CREFIN 5 pF -75 dB Slow 0.5 MHz Fast 1 MHz Reference feedthrough VREF = 1VPP at 1kHz + 1.024V dc, DAC code 0 Reference input bandwidth VREF = 0.2VPP + 1.024V dc DAC code 2048 Digital Inputs High level input current IIH Input voltage = DVDD Low level input current IIL Input voltage = 0V Input capacitance CI 3 1 µA -1 µA pF Notes: 1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects of zero code and full scale errors). 2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two codes. A guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change in digital input code. 3. Zero code error is the voltage output when the DAC input code is zero. 4. Gain error is the deviation from the ideal full scale output excluding the effects of zero code error. 5. Power supply rejection ratio is measured by varying AVDD from 4.5V to 5.5V and measuring the proportion of this signal imposed on the zero code error and the gain error. 6. Zero code error and Gain error temperature coefficients are normalised to VREF. 7. Output load regulation is the difference between the output voltage at full scale with a 10kΩ load and 2kΩ load. It is expressed as a percentage of the full scale output voltage with a 10kΩ load. 8. IDD is measured while continuously writing code 2048 to the DAC. For VIH < DVDD - 0.7V and VIL > 0.7V supply current will increase. 9. Typical supply current in power down mode is 10nA. Production test limits are wider for speed of test. 10. Slew rate results are for the lower value of the rising and falling edge slew rates. 11. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling edges. Limits are ensured by design and characterisation, but are not production tested. 12. SNR, SNRD, THD and SPFDR are measured on a synthesised sinewave at frequency fOUT generated with a sampling frequency fs. WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999 5 WM2614 Production Data Rev 1.0 SERIAL INTERFACE tWL 1 SCLK 2 tSUD tSUC16CS 3 4 5 15 16 tHD D15 DIN tWH D14 D13 D12 D1 D0 tSUCSFS NCS tWHFS tSUFSCLK tSUC16FS FS Figure 1 Timing Diagram Test Conditions: RL = 10kΩ, CL = 100pF. AVDD = DVDD = 5V ± 10%, VREF = 2.048V and AVDD = DVDD = 3V ± 10%, VREF = 1.024V over recommended operating free-air temperature range (unless noted otherwise). SYMBOL TEST CONDITIONS MIN TYP MAX UNIT tSUCSFS Setup time NCS low before negative FS edge. 10 ns tSUFSCLK Setup time FS low before first negative SCLK edge. 8 ns tSUC16FS Setup time, sixteenth negative SCLK edge after FS low on which D0 is sampled before rising edge of FS. 10 ns tSUC16CS Setup time, sixteenth positive SCLK edge (first positive after D0 sampled) before NCS rising edge. If FS is used instead of the sixteenth positive edge to update the DAC, then the setup time is between the FS rising edge and the NCS rising edge. 10 ns tWHCLK Pulse duration, SCLK high. 25 ns tWLCLK Pulse duration, SCLK low. 25 ns tSUDCLK Setup time, data ready before SCLK falling edge. 8 ns tHDCLK Hold time, data held valid after SCLK falling edge. 5 ns tWHFS Pulse duration, FS high. 20 ns WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999 6 WM2614 Production Data Rev 1.0 TYPICAL PERFORMANCE GRAPHS 3 5V = VDD, V REF = 2.048V, Speed = Fast mode, Load = 10k/100pF 2 INL - LSB 1 0 -1 -2 -3 0 512 1024 1536 2048 2559 3071 3583 4095 DIGITAL CODE Figure 2 Integral Non-Linearity 0.4 0.4 AVDD = DVDD = 5V, VREF = 2V, Input Code = 0 0.35 0.35 0.3 0.3 OUTPUT VOLTAGE - V OUTPUT VOLTAGE - V AVDD = DVDD = 3V, VREF = 1V, Input Code = 0 0.25 0.2 0.15 0.25 0.2 0.15 0.1 0.1 0.05 0.05 0 0 0 1 2 3 4 5 6 7 8 9 0 10 1 2 3 4 5 6 7 8 9 ISINK - mA ISINK - mA Slow 10 Slow Fast Fast Figure Sink 3 Current AVDD = DVDD = 3V Figure 4 Sink Current AVDD = DVDD = 5V 2.06 4.1 AVDD = DVDD = 3V, VREF = 1V, Input Code = 4095 AVDD =DVDD = 5V, VREF = 2V, Input Code = 4095 4.095 2.055 OUTPUT VOLTAGE - V OUTPUT VOLTAGE - V 4.09 2.05 2.045 4.085 4.08 2.04 4.075 2.035 4.07 0 1 2 3 4 5 6 7 ISOURCE - mA 8 9 Slow 10 Fast Figure 5 Source Current AVDD = DVDD = 3V WOLFSON MICROELECTRONICS LTD 0 1 2 3 4 5 ISOURCE - mA 6 7 8 9 Slow 10 Fast Figure 6 Source Current AVDD = DVDD = 5V Production Data Rev 1.0 June 1999 7 WM2614 Production Data Rev 1.0 DEVICE DESCRIPTION GENERAL FUNCTION The device uses a resistor string network buffered with an op amp to convert 12-bit digital data to analogue voltage levels (see Block Diagram). The output voltage is determined by the reference input voltage and the input code according to the following relationship: Output voltage = 2(VREF ) INPUT 1111 1111 CODE 4096 OUTPUT 1111 2(VREF ) : 4095 4096 : 1000 0000 0001 1000 0000 0000 0111 1111 1111 0000 0000 0001 0000 0000 0000 : 2(VREF ) 2(VREF ) 2049 4096 2048 = VREF 4096 2(VREF ) 2047 4096 : 2(VREF ) 1 4096 0V Table 1 Binary Code Table (0V to 2VREFIN Output), Gain = 2 POWER ON RESET An internal power-on-reset circuit resets the DAC register to all 0s on power-up. BUFFER AMPLIFIER The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a 2kΩ load with a 100pF load capacitance. EXTERNAL REFERENCE The reference voltage input is buffered which makes the DAC input resistance independent of code. The REFIN pin has an input resistance of 10MΩ and an input capacitance of typically 5pF. The reference voltage determines the DAC full-scale output. HARDWARE CONFIGURATION OPTIONS The device has two configuration options that are controlled by device pins. DEVICE POWER DOWN The device can be powered-down by pulling pin NPD (Pin 2) high. This powers down all DACs overriding their individual power down settings. This will reduce power consumption to typically 10nA. When the power down function is released the device reverts to the DAC code set prior to power down. SIMULTANEOUS DAC UPDATE The NLDAC pin (Pin 3) can be held high to prevent serial word writes from updating the DAC latches. By writing new values to multiple DACs then pulling NLDAC low, all new DAC codes are loaded into the DAC latches simultaneously. WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999 8 WM2614 Production Data Rev 1.0 SERIAL INTERFACE Explanation of data transfer: First, the device has to be enabled with NCS set to low. Then, a falling edge of FS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK. After 16 bits have been transferred, the next rising edge on SCLK or FS causes the content of the shift register to be moved to the DAC holding latch. If NLDAC is low, the DAC latch will also updated immediately. The serial interface of the device can be used in two basic modes: • • four wire (with chip select) three wire (without chip select) Using chip select (four wire mode), it is possible to have more than one device connected to the serial port of the data source (DSP or microcontroller). If there is no need to have more than one device on the serial bus, then NCS can be tied low. SERIAL CLOCK AND UPDATE RATE Figure 1 shows the device timing. The maximum serial rate is: fSCLKmax = 1 = 20MHz tWCH min + tWCL min The digital update rate is limited to an 800ns period, or 1.25MHz frequency. However, the DAC settling time to 12 bits limits the update rate for large input step transitions. SOFTWARE CONFIGURATION OPTIONS The 16 bits of data can be transferred with the sequence shown in Table 2. D11-D0 contains the 12-bit data word. D15-D12 hold the programmable options. D15 D14 A1 A0 D13 D12 D11 D10 D9 D8 PWR SPD D7 D6 D5 D4 D3 D2 D1 D0 New DAC value (12 bits) Table 2 Register Map DAC ADDRESSING A particular DAC (A, B, C, D) within the device is selected by A1 and A0 within the input word. A1 A0 DAC ADDRESS 0 0 DAC A 0 1 DAC B 1 0 DAC C 1 1 DAC D PROGRAMMABLE SETTLING TIME Settling time is a software selectable 12µs or 4µs, typical to within ±0.5LSB of final value. This is controlled by the value of D12 and associated DAC address. A ONE defines a settling time of 4µs, a ZERO defines a settling time of 12µs for that DAC. PROGRAMMABLE POWER DOWN The power down function is controlled by D13. A ZERO configures that DAC as active, a ONE configures that DAC into power down mode. When the power down function is released the device reverts to the DAC code set prior to power down. WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999 9 WM2614 Production Data Rev 1.0 PACKAGE DIMENSIONS DT: 16 PIN TSSOP (5.0 x 4.4 x 1.0 mm) b DM013.A e 16 9 E1 E GAUGE PLANE 1 θ 8 D 0.25 c A A2 L A1 -C0.05 C Symbols A A1 A2 b c D e E E1 L θ REF: MIN ----0.05 0.80 0.19 0.09 4.90 4.30 0.45 0o SEATING PLANE Dimensions (mm) NOM --------1.00 --------5.00 0.65 BSC 6.4 BSC 4.40 0.60 ----- MAX 1.20 0.15 1.05 0.30 0.20 5.10 4.50 0.75 8o JEDEC.95, MO-153 NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MO-153, VARIATION = AB. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999 10