WM2619 12-bit Parallel Input Voltage Output DAC Production Data, June 1999, Rev 1.0 FEATURES DESCRIPTION • • • • • The WM2619 is a 12-bit voltage output, resistor string, digital-toanalogue converter. A hardware controlled power down mode is provided that reduces power consumption to 50nW. In normal operation the device dissipates 8mW at 5V or 4.3mW at 3V. • 12-bit voltage output DAC Single supply 2.7V to 5.5V operation DNL ±0.4 LSB, INL ±1.5 LSB Settling time 1µs typical Low power consumption 8mW typical in slow mode - 5V supply 4.3mW typical in fast mode - 3V supply Power down mode The device has been designed to interface efficiently to industry standard microprocessors and DSPs. Excellent performance is delivered with a typical DNL of 0.4 LSBs and a settling time of 1µs. The output stage is buffered by a x2 gain near rail-to-rail amplifier, which features a Class A output stage. The 12 data bits are double-buffered enabling the output to be asynchronously updated under hardware control. APPLICATIONS • • • • • • • Battery powered test instruments Digital offset and gain adjustment Battery operated/remote industrial controls Machine and motion control devices Wireless telephone and communication systems Speech synthesis Arbitrary waveform generation The device is available in a 20-pin TSSOP package. Commercial temperature (0° to 70°C) and Industrial temperature (-40° to 85°C) variants are supported. ORDERING INFORMATION DEVICE TEMP. RANGE PACKAGE WM2619CDT 0° to 70°C 20-pin TSSOP WM2619IDT -40° to 85°C 20-pin TSSOP BLOCK DIAGRAM TYPICAL PERFORMANCE VDD (11) 1 REFERENCE INPUT BUFFER X1 data DAC OUTPUT BUFFER 0.6 0.4 12-BIT DAC LATCH X2 (13) OUT DNL - LSB D[0-11] (19,20, 1-10) NWE (17) VDD = 5V, VREF = 2.048V, Load = 10k/100pF 0.8 REFIN(12) 12-BIT INPUT REGISTER NCS (18) 0.2 0 -0.2 -0.4 POWERDOWN CONTROL POWER-ON RESET (14) GND (16) NLDAC -0.6 WM2619 (15) NPD -0.8 -1 0 512 1024 1536 2048 2559 3071 3583 4095 DIGITAL CODE WOLFSON MICROELECTRONICS LTD Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: [email protected] http://www.wolfson.co.uk Production Data Datasheets contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronics’ Terms and conditions. Masterrev1.0a.doc June 17, 1999 10:52 1999 Wolfson Microelectronics Ltd. WM2619 Production Data PIN CONFIGURATION D2 1 20 D1 D3 2 19 D0 D4 3 18 NCS D5 4 17 NWE D6 5 16 NLDAC D7 6 15 NPD D8 7 14 GND D9 8 13 OUT D10 9 12 REFIN D11 10 11 VDD PIN DESCRIPTION PIN NO NAME TYPE 1 D2 Digital input Digital data input. 2 D3 Digital input Digital data input. 3 D4 Digital input Digital data input. 4 D5 Digital input Digital data input. 5 D6 Digital input Digital data input. 6 D7 Digital input Digital data input. 7 D8 Digital input Digital data input. 8 D9 Digital input Digital data input 9 D10 Digital input Digital data input. 10 D11 Digital input Digital data input (MSB). 11 VDD Supply 12 REFIN Analogue input 13 OUT Analogue output 14 GND Ground 15 NPD Digital input Power down. Powers down all DACs overriding their individual power down settings and all output stages. This pin is active low. 16 NLDAC Digital input Load DAC. Digital input active low. NLDAC must be taken low to update the DAC latch from the holding latches. 17 NWE Digital input Write enable (active low). 18 NCS Digital input Chip select (active low). 19 D0 Digital input Parallel data input (LSB). 20 D1 Digital input Parallel data input. WOLFSON MICROELECTRONICS LTD DESCRIPTION Positive power supply. Voltage reference input. Analogue output. Ground. Production Data Rev 1.0 June 1999 2 WM2619 Production Data ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device CONDITION MIN MAX -0.3V VDD + 0.3V -0.3V VDD + 0.3V 0°C -40°C 70°C 85°C -65°C 150°C Digital Supply voltage, VDD to GND 7V Reference input voltage Digital input voltages Operating temperature range, TA WM2619C WM2619I Storage temperature Lead temperature 1.6mm (1/16 inch) soldering for 10 seconds 260°C RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL Supply voltage VDD TEST CONDITIONS VIH VDD = 2.7V to 5.5V Low-level digital input voltage VIL VDD = 2.7V to 5.5V Reference voltage to REFIN VREF See Note RL Load capacitance CL Operating free-air temperature TA UNIT 5.5 V 0.8 V V VDD - 1.5 2 WM2619C MAX 2 0 WM2619I -40 Note: Reference input voltages greater than VDD/2 will cause output saturation for large DAC codes. WOLFSON MICROELECTRONICS LTD TYP 2.7 High-level digital input voltage Load resistance MIN 10 V kΩ 100 pF 70 °C 85 °C Production Data Rev1.0 June 1999 3 WM2619 Production Data ELECTRICAL CHARACTERISTICS Test Conditions: RL = 10kΩ, CL = 100pF. VDD = 5V ± 10%, VREF = 2.048V and VDD = 3V ± 10%, VREF = 1.024V over recommended operating free-air temperature range (unless noted otherwise) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Static DAC Specifications Resolution 12 bits Integral non-linearity INL See Note 1 ± 1.5 ±4 LSB Differential non-linearity DNL See Note 2 ± 0.4 ±1 LSB Zero code error ZCE See Note 3 3 ± 20 mV GE See Note 4 0.25 ± 0.5 % FSR d.c. PSRR See Note 5 0.5 mV/V Zero code error temperature coefficient See Note 6 3 ppm/°C Gain error temperature coefficient See Note 6 1 ppm/°C Gain error D.c. power supply rejection ratio DAC Output Specifications Output voltage range 0 Output load regulation 2kΩ to 10kΩ load See Note 7 VDD - 0.4 V 0.1 0.3 % 1.6 1.4 3.0 2.7 mA mA 0.01 10 µA Power Supplies Active supply current IDD Power down supply current No load, VIH = VDD, VIL = 0V VDD = 5V, VREF = 2.048V VDD = 3V, VREF = 1.024V See Note 8 No load, all digital inputs 0V or VDD See Note 9 Dynamic DAC Specifications Slew rate Settling time Glitch energy Signal to noise ratio Signal to noise and distortion ratio Total harmonic distortion Spurious free dynamic range SNR SNRD THD SPFDR DAC code 128 to 4095, 10%-90% See Note 10 DAC code 128 to 4095 See Note 11 8 V/µs 1 µs Code 2047 to 2048 5 nV-s 65 78 dB 58 67 dB fs = 480ksps, fOUT = 1kHz, BW = 20kHz, TA = 25°C See Note 12 fs = 480ksps, fOUT = 1kHz, BW = 20kHz, TA = 25°C See Note 12 fs = 480ksps, fOUT = 1kHz, BW = 20kHz, TA=25°C See Note 12 fs = 480ksps, fOUT = 1kHz, BW = 20kHz, TA = 25°C See Note 12 -68 60 -60 dB 72 dB Reference Reference input resistance RREFIN 10 MΩ Reference input capacitance CREFIN 5 pF -60 dB 1.4 MHz Reference feedthrough Reference input bandwidth WOLFSON MICROELECTRONICS LTD VREF = 1VPP at 1kHz + 1.024Vdc, DAC code 0 VREF = 0.2VPP + 1.024V d.c. DAC code 2048 Production Data Rev 1.0 June 1999 4 WM2619 Production Data Test Conditions: RL = 10kΩ, CL = 100pF. VDD = 5V ± 10%, VREF = 2.048V and VDD = 3V ± 10%, VREF = 1.024V over recommended operating free-air temperature range (unless noted otherwise) PARAMETER SYMBOL TEST CONDITIONS High level input current IIH Low level input current IIL Input capacitance CI MIN TYP MAX UNIT Input voltage = VDD 1 µA Input voltage = 0V -1 µA Digital Inputs 8 pF Notes: 1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects of zero code and full scale errors). 2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two codes. A guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change in digital input code. 3. Zero code error is the voltage output when the DAC input code is zero. 4. Gain error is the deviation from the ideal full scale output excluding the effects of zero code error. 5. Power supply rejection ratio is measured by varying VDD from 4.5V to 5.5V and measuring the proportion of this signal imposed on the zero code error and the gain error. 6. Zero code error and Gain error temperature coefficients are normalised to full scale voltage. 7. Output load regulation is the difference between the output voltage at full scale with a 10kΩ load and 2kΩ load. It is expressed as a percentage of the full scale output voltage with a 10kΩ load. 8. IDD is measured while continuously writing code 2048 to the DAC. For VIH < VDD - 0.7V and VIL > 0.7V supply current will increase. 9. Typical supply current in power down mode is 10nA. Production test limits are wider for speed of test. 10. Slew rate results are for the lower value of the rising and falling edge slew rates. 11. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling edges. Limits are ensured by design and characterisation, but are not production tested. 12. SNR, SNRD, THD and SPFDR are measured on a synthesised sinewave at frequency fOUT generated with a sampling frequency fs. WOLFSON MICROELECTRONICS LTD Production Data Rev1.0 June 1999 5 WM2619 Production Data SERIAL INTERFACE tSUDWE X D [0:11] tHD Data X tSUCSWE NCS tWWE NWE tSUWELD tWLD NLDAC Figure 1 Timing Diagram Test Conditions: RL = 10kΩ, CL = 100pF. VDD = 5V ± 10%, VREF = 2.048V and VDD = 3V ± 10%, VREF = 1.024V over recommended operating free-air temperature range (unless noted otherwise) SYMBOL TEST CONDITIONS MIN tSUCSWE Setup time NCS low before positive NWE edge 13 ns tSUDWE Setup time data ready before positive NWE edge 9 ns Data hold after positive NWE edge 0 ns Setup time NWE high before NLDAC low 0 ns tWWE High pulse width of NWE 10 ns tWLD Low pulse width of NLDAC 10 ns THD tSUWELD WOLFSON MICROELECTRONICS LTD TYP MAX UNIT Production Data Rev 1.0 June 1999 6 WM2619 Production Data TYPICAL PERFORMANCE GRAPHS 3 VDD = 5V, VREF = 2.048V, Load = 10k/100pF 2 INL - LSB 1 0 -1 -2 -3 0 512 1024 1536 2048 2559 3071 3583 4095 DIGITAL CODE Figure 2 Integral Non-Linearity 5 3 VDD = 5V, VREF = 2V, Input Code = 0 VDD = 3V, VREF = 1V, Input Code = 0 4.5 2.5 4 2 OUTPUT VOLTAGE - V OUTPUT VOLTAGE - V 3.5 1.5 3 2.5 2 1 1.5 1 0.5 0.5 0 0 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 ISINK - mA Figure 3 Sink Current VDD = 3V 6 7 8 9 10 Figure 4 Sink Current VDD = 5V 2.065 4.105 VDD = 3V, VREF = 1V, Input Code = 4095 VDD = 5V, VREF = 2V, Input Code = 4095 2.06 4.1 2.055 4.095 OUTPUT VOLTAGE - V OUTPUT VOLTAGE - V 5 ISINK - mA 2.05 2.045 2.04 4.09 4.085 4.08 2.035 4.075 2.03 4.07 2.025 4.065 0 1 2 3 4 5 6 7 8 ISOURCE - mA Figure 5 Source Current VDD = 3V WOLFSON MICROELECTRONICS LTD 9 10 0 2 4 6 8 10 ISOURCE - mA Figure 6 Source Current VDD = 5V Production Data Rev1.0 June 1999 7 WM2619 Production Data DEVICE DESCRIPTION GENERAL FUNCTION The device uses a resistor string network buffered with an op amp to convert 12-bit digital data to analogue voltage levels (see Block Diagram). The output voltage is determined by the reference input voltage and the input code according to the following relationship: Output voltage = 2(VREF ) INPUT CODE 4096 OUTPUT 1111 1111 1111 1000 : 0000 0001 1000 0000 0000 0111 1111 1111 0000 : 0000 0001 0000 0000 0000 2(VREF ) 4095 4096 : 2(VREF ) 2(VREF ) 2049 4096 2048 = VREF 4096 2(VREF ) 2047 4096 : 2(VREF ) 1 4096 0V Table 1 Binary Code Table (0V to 2VREFIN Output), Gain = 2 POWER ON RESET An internal power-on-reset circuit resets the DAC register to all 0s on power-up. BUFFER AMPLIFIER The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a 2kΩ load with a 100pF load capacitance. EXTERNAL REFERENCE The reference voltage input is buffered which makes the DAC input resistance independent of code. The REFIN pin has an input resistance of 10MΩ and an input capacitance of typically 5pF. The reference voltage determines the DAC full-scale output. HARDWARE CONFIGURATION OPTIONS The WM2619 has two configuration options that are controlled by device pins. DEVICE POWERDOWN The device can be powered-down by pulling pin NPD (pin 15) high. This powers down the DAC. This will reduce power consumption significantly. When the power down function is released the device reverts to the DAC code set prior to power down. DAC UPDATE The NLDAC pin (Pin 16) can be held high to prevent serial word writes from updating the DAC latch. By writing the new value to the DAC then pulling NLDAC low, the new DAC code is loaded into the DAC latch. PARALLEL INTERFACE The device registers data on the positive edge of NWE (Pin 17). It must be enabled with NCS (Pin 18) low. WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999 8 WM2619 Production Data PACKAGE DIMENSIONS DT: 20 PIN TSSOP (6.5 x 4.4 x 1.0 mm) b DM008.C e 20 11 E1 E GAUGE PLANE 1 θ 10 D 0.25 c A A2 L A1 -C0.05 C Symbols A A1 A2 b c D e E E1 L θ REF: MIN ----0.05 0.80 0.19 0.09 6.40 4.30 0.45 o 0 Dimensions (mm) NOM --------1.00 --------6.50 0.65 BSC 6.4 BSC 4.40 0.60 ----- SEATING PLANE MAX 1.20 0.15 1.05 0.30 0.20 6.60 4.50 0.75 o 8 JEDEC.95, MO-153 NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MO-153, VARIATION = AC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. WOLFSON MICROELECTRONICS LTD Production Data Rev1.0 June 1999 9