WM2639 12-Bit Parallel Input Voltage Output DAC with Internal Reference Production Data, July 1999, Rev 1.0 FEATURES • • • • • • • DESCRIPTION 12-bit voltage output DAC Single supply 2.7V to 5.5V operation DNL ± 0.3 LSBs, INL ± 1.2 LSBs Internal programmable voltage reference Settling time 1µ µ s typical 12-bit microprocessor compatible interface Power down mode 10nA The WM2639 is a 12-bit voltage output, resistor string, digital-toanalogue converter. A hardware controlled power down mode is provided that reduces current consumption to 10nA. The device has been designed to interface efficiently to industry standard microprocessors and DSPs. The WM2639 features an internal programmable voltage reference simplifying overall system design. The reference voltage can also be supplied externally. APPLICATIONS • • • • • • • • Battery powered test instruments Digital offset and gain adjustment Battery operated/remote industrial controls Machine and motion control devices Wireless telephone and communication systems Speech synthesis Arbitrary waveform generation Mass storage devices Excellent performance is delivered with a typical DNL of 0.3 LSBs and typical INL of 1.2 LSBs. The output stage is buffered by a x2 gain near rail-to-rail amplifier, which features a Class A output stage (slow mode, Class AB). The 12 data bits are double buffered enabling the output to be asynchronously updated under hardware control. The settling time of the DAC is software programmable to allow the designer to optimise speed versus power dissipation. The device is available in a 20-pin TSSOP package. Commercial temperature (0° to 70°C) and Industrial temperature (-40° to 85°C) variants are supported. ORDERING INFORMATION DEVICE TEMP. RANGE PACKAGE WM2639CDT 0° to 70°C 20-pin TSSOP WM2639IDT -40° to 85°C 20-pin TSSOP BLOCK DIAGRAM TYPICAL PERFORMANCE VDD (11) X1 REF(12) 1 5V = VDD, VREF 1.024V/2.048V SELECTABLE REFERENCE 0.8 0.4 2-BIT REFERENCE SELECT LATCH REFERENCE INPUT BUFFER X1 D[0-11] (19,20, 1-10) NWE (17) DAC OUTPUT BUFFER -0.2 12-BIT DAC LATCH data 0.2 DNL - LSB REFERENCE OUTPUT BUFFER WITH OUPUT ENABLE X2 (13) OUT -0.4 12-BIT INPUT REGISTER NCS (18) 2-BIT CONTROL LATCH REG (15) -0.8 -1 POWER-ON RESET (14) GND POWERDOWN CONTROL WM2639 512 1024 2048 2559 3583 4095 (16) NLDAC WOLFSON MICROELECTRONICS LTD Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: [email protected] http://www.wolfson.co.uk Production Data contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronics’ Terms and conditions.. Master 15/07/99 15:02 1999 Wolfson Microelectronics Ltd. WM2639 Production Data PIN CONFIGURATION D2 1 20 D3 2 19 D0 D4 3 18 NCS D5 4 17 NWE D6 5 16 NLDAC D7 6 15 REG D8 7 14 AGND D9 8 13 OUT D10 9 12 REF D11 10 11 VDD D1 PIN DESCRIPTION PIN NO NAME TYPE 1 D2 Digital input Data input. 2 D3 Digital input Data input. 3 D4 Digital input Data input. 4 D5 Digital input Data input. 5 D6 Digital input Data input. 6 D7 Digital input Data input. 7 D8 Digital input Data input. 8 D9 Digital input Data input. 9 D10 Digital input Data input. 10 D11 Digital input Data input.(MSB) 11 VDD Supply 12 REF Analogue I/O 13 OUT Analogue output 14 AGND Supply 15 REG Digital input Register select. Digital input used to access control register. 16 NLDAC Digital input Load DAC. Digital input active low. NLDAC must be taken low to update the DAC latch from the holding latches. 17 NWE Digital input Write enable. Digital input active low. 18 NCS Digital input Chip select. Digital input active low. 19 D0 Digital input Data input. (LSB) 20 D1 Digital input Data input. WOLFSON MICROELECTRONICS LTD DESCRIPTION Positive power supply. Analogue reference voltage input/output. DAC analogue voltage output. Analogue Ground. Production Data Rev 1.0 July 1999 2 WM2639 Production Data ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. CONDITION MIN MAX -0.3V VDD + 0.3V -0.3V VDD + 0.3V 0°C -40°C 70°C 85°C -65°C 150°C Digital supply voltages, VDD to GND 7V Reference input voltage Digital input voltage range to GND Operating temperature range, TA WM2639CDT WM2639IDT Storage temperature Lead temperature 1.6mm (1/16 inch) soldering for 10 seconds 260°C RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL Supply voltage VDD TEST CONDITIONS MIN 2.7 TYP MAX UNIT 5.5 V High-level digital input voltage VIH VDD = 2.7V to 5.5V Low-level digital input voltage VIL VDD = 2.7V to 5.5V 0.8 V VREF See Note VDD - 1.5 V Reference voltage to REF Load resistance RL Load capacitance CL Operating free-air temperature TA 2 V 2 kΩ 100 pF WM2639CDT 0 70 °C WM2639IDT -40 85 °C Note: Reference voltages greater than VDD/2 will cause output saturation for large DAC codes. WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 July 1999 3 WM2639 Production Data ELECTRICAL CHARACTERISTICS Test Conditions: RL = 10kΩ, CL = 100pF. VDD = 5V ± 10%, VREF = 2.048V and VDD = 3V ± 10%, VREF = 1.024V over recommended operating free-air temperature range (unless noted otherwise) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Static DAC Specifications Resolution 12 bits Integral non-linearity INL See Note 1 ± 1.2 ±3 LSB Differential non-linearity DNL See Note 2 ± 0.3 ± 0.5 LSB Zero code error ZCE See Note 3 3 ± 20 mV GE See Note 4 ± 0.3 % FSR DC PSRR See Note 5 0.5 mV/V Zero code error temperature coefficient See Note 6 20 ppm/°C Gain error temperature coefficient See Note 6 20 ppm/°C Gain error d.c. power supply rejection ratio DAC Output Specifications Output voltage range 0 Output load regulation VDD - 0.4 V 0.1 0.3 % Slow 1.3 1.6 mA Fast 2.3 2.8 mA Slow 0.9 1.2 mA Fast 1.9 2.4 mA Slow 1.2 1.5 mA Fast 2.1 2.6 mA Slow 0.9 1.1 mA Fast 1.8 2.3 mA 0.01 1 µA 2kΩ to 10kΩ load See Note 7 Power Supplies Active supply current IDD No load, VIH = VDD, VIL = 0V VDD = 5V, VREF = 2.048V, Internal VDD = 5V, VREF = 2.048V, External VDD = 3V, VREF = 1.024V, Internal VDD = 3V, VREF = 1.024V, External See Note 8 Power down supply current No load, all inputs 0V or VDD See Note 9 Dynamic DAC Specifications Slew rate DAC code 32-4095, 10%-90% Slow 1.2 1.7 V/µs Fast 6.0 10 V/µs Slow 3.5 µs Fast 1 µs 5 nV-s See Note 10 Settling time DAC code 32-4095 See Note 11 Glitch energy WOLFSON MICROELECTRONICS LTD Code 2047 to 2048 Production Data Rev 1.0 July 1999 4 WM2639 Production Data Test Conditions: RL = 10kΩ, CL = 100pF. VDD = 5V ± 10%, VREF = 2.048V and VDD = 3V ± 10%, VREF = 1.024V over recommended operating free-air temperature range (unless noted otherwise) PARAMETER Signal to noise ratio Signal to noise and distortion ratio SYMBOL TEST CONDITIONS MIN TYP SNR fs = 480ksps, fOUT = 1kHz, BW = 20kHz, TA=25°C See Note 12 fs = 480ksps, fOUT = 1kHz, BW = 20kHz, TA=25°C 73 78 dB 61 67 dB SNRD MAX UNIT See Note 12 Total harmonic distortion THD fs = 480ksps, fOUT = 1kHz, BW = 20kHz, TA=25°C SPFDR fs = 480ksps, fOUT = 1kHz, BW = 20kHz, TA = 25°C -69 -62 dB See Note 12 Spurious free dynamic range 63 74 dB 10 MΩ See Note 12 Reference configured as input Reference input resistance RREFIN Reference input capacitance CREFIN Reference feedthrough 55 pF -60 dB Slow 500 kHz Fast 900 kHz VREF = 1VPP at 1kHz + 1.024Vdc, DAC code 0 Reference input bandwidth VREF= 0.2VPP + 1.024V d.c. DAC code 2048 Reference configured as output Low reference voltage VREFOUTL High reference voltage VREFOUTH Output source current IREFSRC Output sink current IREFSNK VDD > 4.75V 1.003 1.024 1.045 V 2.027 2.048 2.069 V 1 mA -1 mA Load Capacitance 100 PSRR -48 pF dB Digital Inputs High level input current IIH Input voltage = VDD 1 µA Low level input current IIL Input voltage = 0V -1 µA Input capacitance CI 8 pF Notes: 1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects of zero code and full scale errors). 2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two codes. A guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change in digital input code. 3. Zero code error is the voltage output when the DAC input code is zero. 4. Gain error is the deviation from the ideal full scale output excluding the effects of zero code error. 5. Power supply rejection ratio is measured by varying VDD from 4.5V to 5.5V and measuring the proportion of this signal imposed on the zero code error and the gain error. 6. Zero code error and Gain error temperature coefficients are normalised to full scale voltage. 7. Output load regulation is the difference between the output voltage at full scale with a 10kΩ load and 2kΩ load. It is expressed as a percentage of the full scale output voltage with a 10kΩ load. 8. IDD is measured while continuously writing code 2048 to the DAC. For VIH < VDD - 0.7V and VIL > 0.7V supply current will increase. 9. Typical supply current in power down mode is 10nA. Production test limits are wider for speed of test. 10. Slew rate results are for the lower value of the rising and falling edge slew rates. 11. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling edges. Limits are ensured by design and characterisation, but are not production tested. WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 July 1999 5 WM2639 Production Data 12. SNR, SNRD, THD and SPFDR are measured on a synthesised sinewave at frequency fOUT generated with a sampling frequency fs. SERIAL INTERFACE tSUD X D[0-11] DATA X tSUR X REG REG X tHDR NCS tSUCSWE tWHWE NWE tSUWELD tWLD NLDAC Figure 1 Timing Diagram Test Conditions: RL = 10kΩ, CL = 100pF. VDD = 5V± 10%, VREF = 2.048V and VDD = 3V± 10%, VREF = 1.024V over recommended operating free-air temperature range (unless noted otherwise) SYMBOL TEST CONDITIONS MIN Setup time NCS low before positive NWE edge 15 ns tSUD Setup time data ready before positive NWE edge 10 ns tSUR Setup time REG ready before positive NWE edge 20 ns tHDR Data and REG hold after positive NWE edge 5 ns Setup time NWE high before NLDAC low 5 ns High pulse width of NWE 20 ns Low pulse width of NLDAC 23 ns tSUCSWE tSUWELD tWHWE tWLD WOLFSON MICROELECTRONICS LTD TYP MAX UNIT Production Data Rev 1.0 July 1999 6 WM2639 Production Data TYPICAL PERFORMANCE GRAPHS 3 5V = VDD, VREF = External. 2.048V, Speed = Fast mode, Load = 10k/100pF 2 INL - LSB 1 0 -1 -2 -3 0 512 1024 1536 2048 2559 3071 3583 4095 DIGITAL CODE Figure 2 Integral Non-Linearity 3 5 VDD = 5V, VREF = Int. 2V, Input Code = 0 VDD = 3V, VREF = Internal. 1V, Input Code = 0 4.5 2.5 Vo - OUTPUT VOLTAGE - V Vo - OUTPUT VOLTAGE - V 4 2 1.5 1 3.5 3 2.5 2 1.5 1 0.5 0.5 0 0 0 0 0.5 1 1.5 2 2.5 3 3.5 0.5 1 1.5 4 2 2.5 3.5 Slow Slow 4 Fas) Fast Figure 3 Sink Current VDD = 3V Figure 4 Sink Current VDD = 5V 2.0395 4.0795 VDD = 5V, VREF = Int. 2V, Input Code = 4095 VDD = 3V, VREF = Int. 1V, Input Code = 4095 2.039 4.079 2.0385 4.0785 2.038 4.078 Vo - OUTPUT VOLTAGE - V Vo - OUTPUT VOLTAGE - V 3 ISINK - mA ISINK - mA 2.0375 2.037 2.0365 4.0775 4.077 4.0765 2.036 4.076 2.0355 4.0755 2.035 4.075 0 0.5 1 1.5 2 2.5 3 3.5 ISOURCE - mA WOLFSON MICROELECTRONICS LTD 0 0.5 1 1.5 2 2.5 3 3.5 4 ISOURCE - mA Slow Figure 5 Source Current VDD = 3V 4 Fast Slow Fast Figure 6 Source Current VDD = 5V Production Data Rev 1.0 July 1999 7 WM2639 Production Data DEVICE DESCRIPTION GENERAL FUNCTION The device uses a resistor string network buffered with an op amp to convert 12-bit digital data to analogue voltage levels (see Block Diagram). The output voltage is determined by the reference input voltage and the input code according to the following relationship: ( Output voltage = 2 VREF ) CODE 4096 INPUT 1111 1111 OUTPUT ( 1111 2 VREF : 1000 0000 4096 : 0001 ( 2 VREF 1000 0000 0000 ( 2 VREF 0111 1111 1111 ) 2048 = V REF 4096 ( : 0000 0000 ) 2047 4096 : 0001 ( 2 VREF 0000 ) 2049 4096 2 VREF 0000 ) 4095 0000 ) 1 4096 0V Table 1 Binary Code Table (0V to 2VREF Output), Gain = 2 POWER ON RESET An internal power-on-reset circuit resets the DAC register to all 0s on power-up. BUFFER AMPLIFIER The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a 2kΩ load with a 100pF load capacitance. HARDWARE CONFIGURATION OPTIONS The WM2639 has one configuration option that is controlled by a device pin. DAC UPDATE The NLDAC pin (Pin 16) can be held high to prevent word writes from updating the DAC latch. By writing the new value to the DAC then pulling NLDAC low, the new DAC code is loaded into the DAC latch. PARALLEL INTERFACE The device registers data on the positive edge of NWE (Pin 17). It must be enabled with NCS (Pin 18) low. Whether the data is written to the DAC holding latch or the control register, depends on the state of input pin REG (Pin 15). REG = 0 selects the DAC holding latch, REG = 1 selects the control register. WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 July 1999 8 WM2639 Production Data SOFTWARE CONFIGURATION OPTIONS DATA FORMAT The WM2639 writes data either to the DAC holding latch or to the control register depending on the state of input pin REG. REG DATA DESTINATION (PIN 15) 0 DAC holding latch 1 Control register D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X REF1 REF0 X PWR SPD Table 1 Register Bits PROGRAMMABLE SETTLING TIME Settling time is a software selectable 3.5µs or 1µs, typical to within ±0.5LSB of final value. This is controlled by the value of SPD – Bit D0. A ONE defines a settling time of 1µs, a ZERO (default) defines a settling time of 3.5µs. PROGRAMMABLE POWER DOWN The power down function can be controlled by PWR. A ZERO configures the device as active, or fully powered up, a ONE configures the device into power down mode. When the power down function is released the device reverts to the DAC code set prior to power down. PROGRAMMABLE INTERNAL REFERENCE The reference can be sourced internally or externally under software control. If an external reference voltage is applied to the REF pin, the device must be configured to accept this. If an external reference is selected, the reference voltage input is buffered which makes the DAC input resistance independent of code. The REF pin has an input resistance of 10MΩ and an input capacitance of typically 55pF. The reference voltage determines the DAC full-scale output. If an internal reference is selected, a voltage of 1.024V or 2.048 is available. The internal reference can source up to 1mA and can therefore be used as an external system reference. REF1 REF0 REFERENCE 0 0 External (default) 0 1 1.024V 1 0 2.048V 1 1 External Table 2 Programmable Internal Reference WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 July 1999 9 WM2639 Production Data PACKAGE DIMENSIONS DT: 20 PIN TSSOP (6.5 x 4.4 x 1.0 mm) b DM008.C e 20 11 E1 E GAUGE PLANE 1 θ 10 D 0.25 c A A2 L A1 -C0.05 C Symbols A A1 A2 b c D e E E1 L θ MIN ----0.05 0.80 0.19 0.09 6.40 4.30 0.45 0o Dimensions (mm) NOM --------1.00 --------6.50 0.65 BSC 6.4 BSC 4.40 0.60 SEATING PLANE MAX 1.20 0.15 1.05 0.30 0.20 6.60 4.50 0.75 8 REF: NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MO-153, VARIATION = AC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 July 1999 10