WM5628L, WM5628 Production Data Sept. 1996 Rev 2 3 & 5V Octal 8-Bit Voltage Output DAC with Serial Interface Description Features WM5628L and WM5628 are Octal 8-bit digital to analogue converters (DAC) controlled via a serial interface. Each DAC's output voltage range is programmable for either x1 or x 2 its reference input voltage, allowing near rail to rail operation for the x 2 output range. High impedance buffered voltage reference inputs are provided for each group of four DACs. WM5628L operates on a single supply voltage of 3 V while WM5628 operates on 5 V. WM5628/L interfaces to all popular microcontrollers and microprocessors via a three wire serial interface with CMOS compatible, schmitt trigger, digital inputs. An 12 bit command word comprises 3 DAC select bits, an output range selection bit and 8-bits of data. Individual or all DAC outputs are changed using WM5628/L's double buffered DAC registers and the separate LOAD and LDAC inputs. DAC outputs are updated simultaneously by writing a complete set of new values and then pulsing the LDAC input. The DAC outputs are optimised for single supply operation and driving ground referenced loads. An internal power-on-reset function sets the DAC's input codes to zero at power up. Ideal in space critical applications WM5628/L is available in wide-bodied and DIP packages for commercial (0oC to 70oC) and industrial (-40oC to 85o C) temperature ranges. • • • • • • Pin Configuration Top View 16 pin N and DW packages DACB DACA GND Data CLK VDD DACE DACF 1 2 3 4 5 6 7 8 16 DACC 15 DACD 14 Ref1 13 LDAC 12 Load 11 Ref2 10 DACH 9 DAC G Production Data data sheets contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronics standard terms and conditions Eight 8-bit voltage output DAC's Three wire serial interface Programmable x1 or x 2 output range. Power-on-reset sets outputs to zero Buffered voltage reference inputs Simultaneous DAC output update Key Specifications • • • • Single supply operation: WM5628L : 3 V WM5628 : 5V 0 to 4 V output (x 2 output range) at 5 V VDD 0 to 2.5 V output (x 2 output range) at 3 V VDD Guaranteed monotonic output Applications • • • • • • Programmable d.c. voltage sources Digitally controlled attenuator/amplifier Signal synthesis Mobile communications Automatic test equipment Process control Ordering Information DEVICE TEMP. RANGE PACKAGE WM5628CN 0oC to 70oC 16 pin plastic DIP WM5628CDW WM5628IN WM5628IDW WM5628LCN WM5628LCDW WM5628LIN WM5628LIDW 0oC to 70oC -40oC to 85oC -40oC to 85oC 0oC to 70oC 0oC to 70oC -40oC to 85oC -40oC to 85oC 16 pin wide-bodied plastic SO 16 pin plastic DIP 16 pin wide-bodied plastic SO 16 pin plastic DIP 16 pin wide-bodied plastic SO 16 pin plastic DIP 16 pin wide-bodied plastic SO Wolfson Microelectronics Lutton Court, Bernard Terrace, Edinburgh EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 email: [email protected] www: http://www.wolfson.co.uk © 1996 Wolfson Microelectronics WM5628L, WM5628 Block Diagram VDD 6 Ref 1 14 DAC 9 Latch Latch 8 Latch 8 Latch 8 Latch 8 Latch 8 Latch 8 Latch 8 Latch 8 DAC 9 Latch DAC 9 Latch DAC 9 Ref 2 Latch 1 x2 16 x2 15 x2 DACA DACB DACC DACD 11 DAC 9 Latch DAC 9 Latch DAC 9 Latch DAC 9 5 CLK Data 4 Load 12 Latch Serial Interface 7 x2 8 x2 9 x2 10 x2 Power-on-Reset 13 LDAC 2 2 x2 Wolfson Microelectronics 3 GND DACE DACF DACG DACH WM5628L, WM5628 Absolute Maximum Ratings (note 1) Supply Voltage (VDD - VGND) . . . . . . . . . . . . +7V Digital Inputs . . . . . . . . . . .GND - 0.3 V, VDD + 0.3 V Reference inputs . . . . . . . GND - 0.3 V, VDD + 0.3 V Operating temperature range, TA . . . . WM5628_C_ . . . . . . . . . . . . . . WM5628_I_ . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . Lead Temperature 1.6mm (1/16 inch) from case for 10 secs . . . . . . . . . . . TMIN to TMAX 0oC to +70oC -40oC to +85oC -50oC to +150oC . . . . 260OC Recommended Operating Conditions Supply voltage WM5628 Supply Voltage WM5628L Reference input range, X1 gain DAC output load resistance to GND High level digital input voltage Low level digital input voltage Clock frequency SYMBOL V DD V DD VREF RL V IH VIL F CLK MIN 4.75 2.7 NOMINAL MAX 5.25 5.25 VDD - 1.5 3.3 10 0.8 VDD 0.8 1 UNIT V V V kΩ V V MHz Electrical Characteristics: WM5628 VDD = 5 V, GND = 0 V, VREF = 2 V, RL = 10 kΩ, CL = 100 pF, TA = full range, unless otherwise stated. PARAMETER Power Supply Supply current Static Accuracy Resolution Monotonicity Differential Nonlinearity Integral Nonlinearity Zero-code error Zero-code error temperature coefficient Zero-code error supply rejection Full scale error Full scale error temperature coefficient Full scale error supply rejection Output sink current Output source current SYMBOL IDD TEST CONDITIONS MIN TYP Outputs unloaded, digital inputs = 0 V or VDD MAX 4.0 8 8 DNL INL ZCE FSE IO(SINK) IO(SOURCE) UNIT mA VREF = 2 V, Range x 2. (note 3) VREF = 2 V, Range x 2. (note 4) VREF = 2 V, Range x 2. (note 5) Input code = 00 Hex (note 6) ± 0.1 10 Bits Bits LSB LSB mV µV/OC Input code = 00 Hex, VDD = 5 V ± 5 % (note 7) VREF = 2 V, Range x 2. (note 8) Input code = FF Hex (note 9) 0.5 mV/V Input code = FF Hex, VDD = 5 V ± 5 % (note 10) Each DAC output ± 0.9 ± 1.0 30 ± 60 20 2 ± 25 mV µV/OC 0.5 mV/V µA mA Wolfson Microelectronics 3 WM5628L, WM5628 Electrical Characteristics: WM5628L VDD = 3 .6V, GND = 0 V, VREF = 2 V x 1 gain, R L = 10 kΩ, CL = 100 pF, TA = full range, unless otherwise stated. PARAMETER Power Supply Supply current Static Accuracy Resolution Monotonicity Differential Nonlinearity Integral Nonlinearity Zero-code error Zero-code error temperature coefficient Full scale error Full scale error temperature coefficient Output sink current Output source current Power supply sensitivity SYMBOL IDD TEST CONDITIONS MIN TYP VDD = 3.3v MAX 4 8 8 DNL INL ZCE FSE VREF = 1.25 V, Range x 2. (note 3) VREF = 1.25 V, Range x 2. (note 4) VREF = 1.25 V, Range x 2. (note 5) Input code = 00 Hex (note 6) 10 ± 60 ± 25 mV µV/O C 0.5 µA mA mV/V ± 0.9 0 I O(SINK) Each DAC output IO(SOURCE) IREF VDD = 3.3V, VREF = 1.5V PSRR mA Bits Bits LSB LSB mV µV/O C ± 1.0 VREF = 1.25 V, Range x 2. (note 8) Input code = FF Hex (note 9) UNIT 30 20 1 Electrical Characteristics: WM5628 & WM5628L VDD = 2.7 to 5.5V, GND = 0 V, VREF = 2 V x 1 gain, R L = 10 kΩ, CL = 100 pF, TA = full range, unless otherwise stated. PARAMETER Digital Inputs High level input current Low level input current Input capacitance Timing Parameters Data input setup time Data input hold time CLK to Load Load to CLK Load duration LDAC duration Load to LDAC Reference Inputs Reference input voltage Reference input capacitance Reference feedthrough Channel to channel isolation 4 SYMBOL IIH IIL CI TEST CONDITIONS TYP VI = VDD VI = 0V MAX ±10 ±10 15 t SD t HD 50 50 50 50 250 250 0 t HL t SL tWL tWD t LD VREF MIN A, B, C, D, inputs UNIT µA µA pF ns ns ns ns ns ns ns GND VDD-1.5 V A, B, C, D, inputs 15 pF A, B, C, D inputs (note 11) -60 dB A, B, C, D inputs (note 12) -60 dB Wolfson Microelectronics WM5628L, WM5628 Electrical Characteristics: WM5628 & WM5628L (continued) VDD = 3 .6V, GND = 0 V, V REF = 2 V x 1 gain, RL = 10 kΩ, CL = 100 pF, TA = full range, unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS Dynamic Performance Output settling time To 1/2LSB, VDD=3V & 5V (note 13) Output slew rate Input bandwidth (note 14) Large Signal Bandwidth Measured at -3dB point Digital Crosstalk Clk = 1MHz sq wave measured at DACA - DACD Notes: 1. Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating range limits are given under Recommended Operating Conditions. Guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. 2. Total Unadjusted Error is the sum of integral linearity error, zero code error and full scale error over the input code range. 3. Differential Nonlinearity (DNL) is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. A guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. 4. Integral Nonlinearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects of zero code and full-scale errors). 5. Zero code error is the deviation from zero voltage output when the digital input code is zero. 6. Zero code error temperature coefficient is given by: 6 ZCETC = (ZCE(Tmax - ZCE(Tmin)) /VREF x 10 / (Tmax - Tmin) MIN TYP 10 1 100 100 -50 MAX UNIT µs V/µs kHz kHz dB 8. Full-scale error is the deviation from the ideal full-scale output (VREF - 1LSB) with an output load of 10kΩ 9. Full-Scale Temperature Co-efficient is given by: FSETC = (FSE(T max) - FSE(Tmin)) / VREF x 106 / T max - T min) 10. Full Scale Error Rejection Ratio (FSE-RR) is measured by varying the V DD voltage from 4.5 to 5.5 V d.c. and measuring the proportion of this signal imposed on the full-scale output voltage 11 Reference feedthrough is measured at a DAC output with an input code = 00 Hex with a VREF input = 1 Vdc + 1 VPP at 10kHz 12. Channel to channel isolation is measured at a DAC output with an input code of one DAC to FF Hex and the code oa all other DACs to oo Hex with a VREF input = 1 Vdc + 1 Vpp at 10kHz 13 Setting time is the time for the output signal to remain within ±0.5 LSB of the final measurement value for a digital input code change of 00 Hex to FF Hex. For WM 5628: VDD = 5V, VREF = 2V and range = x 2. For WM5628L: V DD = 3, V REF = 1.25V and range = x 2. 14 Reference bandwidth is the -3dB bandwidth with an input at VREF = 1.25 Vdc =+ 2 V pp with a digital input code of full-scale. 7. Zero-code Error Rejection Ratio (ZCE-RR) is measured by varying the VDD voltage, from 4.5 to 5.5 V d.c., and measuring the proportion of this signal imposed on the zero-code output voltage. Wolfson Microelectronics 5 WM5628L, WM5628 Parameter Measurement Information DACA DACB DACC . 10KΩ CL - 100pF . DACH Slewing Settling Time and Linearity Measurements Typical Performance Characteristics Typical DNL, INL and TUE * at VDD = 5 V Diffe re ntia l Nonlinea rity Integral Nonlinearity VDD = 5 V, Vref = 2.5 V, Range x 1, TA = 25oC V DD = 5 V, Vref =2.5 V, Ra nge x 1, TA = 25o C 0.4 Error (lsb) Error (lsb) 0.2 0.1 0 -0.1 -0.2 0.2 0 -0.2 0 32 64 96 128 160 192 224 256 0 32 64 96 Inpu t Code Total Unadjusted Error Error (ls Error (lsb) 0.25 0 -0.25 192 224 256 V DD = 5 V, Vref = 1.25 V, Ra ng e x 2, TA = 25oC 0.2 0.1 0 -0.1 -0.2 -0.5 0 32 64 96 128 160 192 224 256 Input C ode 0 32 64 96 128 160 Inpu t Code * see note 2 6 160 Diffe re ntia l Nonline a rity V DD = 5 V, Vref = 2.5 V, Range x 1, TA = 25o C 0.5 128 Inp ut Code Wolfson Microelectronics 192 224 256 WM5628L, WM5628 Typical Performance Characteristics (continued) Inte gra l Nonline a rity Tota l Una d justed Error V DD = 5 V, Vref = 1.25 V, Ra nge x 2, TA = 25o C VDD = 5 V, Vref = 1.25 V, Ra nge x 2, TA = 25oC 0.4 0.5 Error (ls Error (ls Typical DNL, INL and TUE * at VDD = 5 V (continued) 0.2 0 -0.2 0.25 0 -0.25 -0.5 0 32 64 96 128 160 InputC ode 192 224 256 0 32 64 96 128 160 Inpu t Code 192 224 256 Typical DNL, INL and TUE at VDD = 3 V Diffe re ntia l Nonlinea rity Integral Nonlinearity VDD = 3 V, V re f = 1.25 V , Ra n g e x 2, TA = 25oC V DD = 3 V, Vref = 1.25 V, Range x 2, TA = 25 oC 0.5 Error (lsb) Error (lsb) 0.2 0.1 0 -0.1 -0.2 0.25 0 -0.25 -0.5 0 32 64 96 128 160 192 224 256 0 32 64 Inpu t Code 96 128 160 Inp ut Code 192 224 256 Total Unadjusted Error VDD = 3 V, Vref = 1.25 V, Range x 2, TA = 25o C 0 -0.25 -0.5 0 32 64 96 128 160 InputC ode 192 224 256 Supply Current vs Temperature Output Source Current vs Output Voltage 8 2.4 7 2.2 6 5 4 IDD (mA) Iout (mA) Error (ls 0.5 0.25 VDD = 5 V T A = 25O C Vref = 2 V Range = x 2 Input code = 255 3 2 VDD = 5V Vre f = 2V Range = x 2 Input Code = 255 2 1.8 VDD + 3V Vre f = 1.25V 1.6 1 1.4 0 0 1 2 3 V out (V) 4 5 -50 -25 0 25 50 75 100 o Temperature ('C) C Wolfson Microelectronics 7 WM5628L, WM5628 Typical Performance Characteristics (continued) Small Signal Frequency Response Large Signal Frequency Response 10 2 0 0 Relative Gain (dB) Relative Gain (dB) -2 -4 -6 -8 -10 VDD = 5 V O TA = 25 C Vref = 1.25 Vdc + 2 Vpp Input Code = 255 -12 -14 -16 -10 -20 V DD = 5 V T A = 25O C Vref = 2 V dc + 0.5 Vpp Input cod e = 255 -30 -40 -50 -18 -60 -20 1 10 100 1000 1 10 Positive Rise and Settling Time VDD = 3 V 500 mV/Vert. div 2 µs/Hor. div 100 1000 10000 Frequency (kHz) Frequency (kHz) VDD = 3 V TA = 25OC code 00 to FF Hex Range = x 2 Vref = 1.25 V Negative Fall and Settling Time VDD = 3 V 500 mV/Vert. div 2 µs/Hor. div VDD = 3 V TA = 25OC code FF to 00 Hex Range = x 2 Vref = 1.25 V Rise time = 2.5 µs, Positive slew rate = 0.80 µs Settling time = 4.5 µs Fall time = 4.85 µs, Negative slew rate = 0.41 µs Settling time = 8.0 µs Positive Rise and Settling Time VDD = 5 V Negative Fall and Settling Time VDD = 5 V 1 V/Vert. div 2 µs/Hor. div VDD = 5 V TA = 25OC code 00 to FF Hex Range = x 2 Vref = 2 V Rise time = 3.75 µs, Positive slew rate = 0.54 µs Settling time = 5.9 µs 8 VDD = 5 V TA = 25OC code FF to 00 Hex Range = x 2 Vref = 2 V 1 V/Vert. div 5 µs/Hor. div Fall time = 5.9 µs, Negative slew rate = 0.54 µs Settling time = 8.5 µs Wolfson Microelectronics WM5628L, WM5628 Equivalent Input and Output Circuits Timing Waveforms Load and LDAC Timing Data Input Timing CLK tSD Data CLK 50 % 50 % tHL tHD tSL tWL Load tLD tWD LDAC Wolfson Microelectronics 9 WM5628L, WM5628 Timing Diagrams 1 2 3 4 5 6 7 8 9 10 11 12 CLK Data A2 A1 RNG A0 D7 D6 D5 D4 D3 D2 D1 D0 Load LDAC Figure 1. Load controlled update (LDAC = 0) 1 2 3 4 5 6 7 8 9 10 11 12 CLK Data A2 A1 RNG A0 D7 D6 D5 D4 D3 D2 D1 D0 Load LDAC Figure 2. LDAC controlled update 1 2 3 4 5 6 7 8 9 10 11 12 CLK Data A2 A1 RNG A0 D7 D6 D5 D4 D3 D2 D1 D0 Load LDAC Figure 3. Load controlled update (LDAC = 0) using 8-bit serial word. 1 2 3 4 5 6 7 8 9 10 11 12 CLK Data A2 A1 A0 RNG D7 D6 D5 D4 D3 D2 Load LDAC Figure 4. LDAC controlled update using 8-bit serial word. 10 Wolfson Microelectronics D1 D0 WM5628L, WM5628 Pin Descriptions Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name DACB DACA GND Data CLK VDD DACE DACF DACG DACH Ref2 Load LDAC Ref1 DACD DACC Type Analogue output Analogue input Supply Digital input Digital input Supply Analogue output Analogue output Analogue output Analogue output Analogue input Digital input Digital input Analogue input Analogue output Analogue output Function DAC B output DAC A output Ground return Serial data input Serial interface clock, negative edge sensitive Positive supply voltage DAC E output DAC F output DAC G output DAC H output Reference to DACE, DACF, DACG and DACH Serial input load DAC update latch control Reference to DACA, DACB, DACC and DACD DAC D output DAC C output Functional Description DAC operation Each of WM5628/L 's eight digital to analogue converters (DACs) are implemented using a single resistor string with 256 taps corresponding to each of the input 8-bit codes. One end of a resistor string is connected to the GND pin and the other end is driven from the output of a reference input buffer. The use of a resistor string guarantees monotonicity of the DAC's output voltage. Linearity depends upon the matching of the resistor string's individual elements and the performance of the output buffer. Two high input impedance voltage reference buffers are provided, each driving four DACs, Each DAC has a voltage output amplifier which is programmable for gains of x1 or x 2 through the serial interface. The DAC output amplifiers feature rail to rail output stages, allowing outputs over the full supply voltage range to be achieved with a x 2 gain setting and a VDD /2 reference voltage input. Used in this way a slight degradation in linearity will occur as the output voltage approaches V DD. A power-on-reset activates at power up resetting the DACs inputs to code 0. Each output voltage is given by: Data Interface WM5628/L's eight double buffered DAC inputs allow several ways of controlling the update of each DAC's output. Serial data is input, MSB first, into the DATA input pin Serial Input DAC Address and Output Tables using CLK, LOAD and LDAC control inputs and comprises 3 DAC address bits, an output range (RNG) bit and 8 DAC input bits. With the LOAD pin high data is clocked into the DATA pin on each falling edge of CLK. Any number of data bits may be clocked in, only the last 12 bits are used. When all data bits have been clocked in, a falling edge at the LOAD pin latches the data and RNG bits into the correct 9 bit input latch using the 3 bit DAC address. If the LDAC input pin is low, the second latch at the DAC input is transparent, and the DAC input and RNG bit will be updated on the falling edge of LOAD simultaneously with the input latch, as shown in figure 1. If the LDAC input is high during serial data input, as shown in figure 2, the falling edge of the LOAD input stores the data in the addressed input latch. The falling edge of LDAC updates the second latches from the input latches and hence the DAC outputs. Vout = Vref x CODE/256 x (RNG+1 ) Where: RNG controls the output gains of x 1 and x 2 CODE is the range 0 to 255 Wolfson Microelectronics 11 WM5628L, WM5628 Functional Description (continued) Using these inputs individual DACs can be updated using one 12 bit serial input word and the LOAD pin. Using both LOAD and LDAC, all or selected DACs can be updated after an appropriate number of data words have been inputted. Figures 3 &4 illustrate operation with the 8 clock pulses available from some microprocessors. If the data input is interrupted in this way the clock input must be held low during the break in clock pulses. The RNG bit controls the DAC output range. When RNG = 0 the output is between Vref(A,B,C,D) and GND and when RNG = 1 the range is between 2 x Vref (A,B,C,D) and GND. Serial Input DAC Address and Output Tables A2 0 0 0 0 1 1 1 1 12 A1 A0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 DAC Updated DACA DACB DACC DACD DACE DACF DACG DACH D7 D6 D5 D4 D3 D2 D1 D0 Output Voltage 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 GND (1/256) x Ref (1 + RNG) 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 (127/256) x Ref (1 + RNG) (128/256) x Ref (1 + RNG) 1 1 1 1 1 1 1 1 (255/256) x Ref (1 + RNG) Wolfson Microelectronics WM5628L, WM5628 Functional Description (Continued) Linearity, offset, and gain error using single end supplies When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset the output voltage may not change with the first code depending on the magnitude of the offset voltage. The output amplifier, with a negative voltage offset, attempts to drive the output to a negative voltage. However, because the most negative supply rail is GND, the output cannot drive to a negative voltage. So when the output offset voltage is negative, the output voltage remains at ZERO volts until the input code value produces a sufficient output voltage to overcome the inherent negative offset voltage, resulting in the transfer function shown below This negative offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive to a negative voltage. For a DAC, linearity is measured between ZERO input code ( all inputs 0 ) and full scale code ( all inputs 1 ) after offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity in the unipolar mode is measured between full scale code and the lowest code which produces a positive output voltage. The code is calculated from the maximum specification for the negative offset. Effect of negative offset (single supply) Wolfson Microelectronics 13 WM5628L, WM5628 Package Descriptions Dual-In-Line Package N or P N 1 0.325 N/2 0.290 0.015 Min. 0.280 A 0.070 Max. 0.240 0.210 Max. Seating plane 105O 90O 0.014 0.150 0.008 0.115 0.030 0.022 Dimension 'A' Variations N 0.045 0.005 Min. Min Max 8 0.355 0.400 14 0.735 0.775 16 0.735 0.775 20 0.940 0.975 Pin spacing 0.100 B.S.C. 0.014 Notes: A. Dimensions are in inches B. Falls within JEDEC MS-001( 20 pin package is shorter than MS-001) C. N is the maximum number of terminals D. All end pins are partial width pins as shown, except the 14 pin package which is full width. Rev. 1 November 96 14 Wolfson Microelectronics WM5628L, WM5628 Package Description Wide body Plastic Small-Outline Package DW - 16 pin shown 1,27 B.S.C. 0,51 0,33 16 PINS** 0,25 M 16 20 24 28 A MAX 10,50 13,00 15,60 18,10 A MIN 10,10 12,60 15,20 17,70 DIM 9 10,65 10,00 7,60 7,40 0.75 x 45 0 0.25 x 45 0 1 8 A Gauge Plane 0o - 8o 1,27 0,40 2,65 2,35 0,30 0,10 0,10 0,33 0,23 Notes: A. Dimensions in millimeters. B. Complies with Jedec standard MS-013. C. This drawing is subject to change without notice. D. Body dimensions do not include mold flash or protrusion. E. Dimension A, mould flash or protrusion shall not exceed 0.15mm. Body width, interlead flash or protrusions shall not exceed 0.25mm. Rev. 1 November 96 Wolfson Microelectronics 15