XICOR X1240

Preliminary Information
X1240
16K
2-Wire RTC
Real Time Clock/Calendar with EEPROM
FEATURES
DESCRIPTION
• 2-Wire Interface interoperable with I2C.
—400kHz data transfer rate
• Secondary Power Supply Input with internal
switch-over circuitry.
• Year 2000 Compliant
• 2K bytes of EEPROM
—64 Byte Page Write Mode
—3 bit Block Lock
• Low Power CMOS
—<1µA Operating Current
—<3mA Active Current during Program
—<400µA Active Current during Data Read
• Single Byte Write Capability
• Typical Nonvolatile Write Cycle Time: 5ms
• High Reliability
—1,000,000 Endurance Cycles
—Guaranteed Data Retention: 100 Years
• Small Package Options
—8-Lead SOIC Package, 8L TSSOP Package
The X1240 is a Real Time Clock with clock/calendar
circuits. The dual port clock register allows the clock to
operate, without loss of accuracy, even during read and
write operations.
The clock/calendar provides functionality that is controllable and readable through a set of registers. The
clock, using a low cost 32.768kHz crystal input, accurately tracks the time in seconds, minutes, hours, date,
day, month and years. It has leap year correction,
automatic adjustment for the year 2000 and months
with less than 31 days.
The device offers a backup power input pin. This
Vback pin allows the device to be backed up by a nonrechargeable battery. The RTC is fully operational
from 1.8 to 5.5 volts.
The X1240 provides a 2K byte EEPROM array, giving
a safe, secure memory for critical user and configuration data. This memory is unaffected by complete failure of the main and backup supplies.
BLOCK DIAGRAM
32.768kHz
X1
Frequency
Divider
Oscillator
X2
SCL
Serial
Interface
Decoder
Control
Decode
Logic
Control
Registers
Status
Register
(EEPROM)
(SRAM)
Timer
Calendar
Logic
Time
Keeping
Registers
(SRAM)
16K
EEPROM
Array
SDA
8
Xicor, Inc. 1994, 1995, 1996, 1997, 1998, 1999 Patents Pending
9900-3003.5 12/6/99 CM
1Hz
1
Characteristics subject to change without notice
X1240
PIN CONFIGURATION
Figure 1. Recommended Crystal connection
X1240
18pF
8 pin SOIC
1
2
X1
X2
NC
VSS
VBack
VCC
X1
X2
3
4
8
7
6
5
X1240
8 pin TSSOP
1
8
2
7
3
6
4
5
VCC
VBack
SCL
SDA
10M
X1
X2
220K
43pF
POWER CONTROL OPERATION
SCL
SDA
VSS
NC
The Power control circuit accepts a VCC and a VBACK
input. The power control circuit will switch to VBACK
when VCC < VBACK - 0.2V. It will switch back to VCC
when VCC exceeds VBACK.
Figure 2. Power Control
PIN DESCRIPTIONS
Serial Clock (SCL)
VCC
The SCL input is used to clock all data into and out of
the device. The input buffer on this pin is always active
(not gated).
VBACK
Internal
Voltage
VCC = VBACK -0.2V
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It has an open drain output and
may be wire ORed with other open drain or open collector outputs. The input buffer is always active (not
gated).
REAL TIME CLOCK OPERATION
The Real Time Clock (RTC) uses an external, 32.768KHz
quartz crystal to maintain an accurate internal representation of the year, month, day, date, hour, minute,
and seconds. The RTC has leap-year correction and a
century byte. The clock will also correct for months having fewer than 31 days and will have a bit that controls
24 hour or AM/PM format. When the X1240 powers up
after the loss of both VCC and VBACK, the clock will not
increment until at least one byte is written to the clock
register.
An open drain output requires the use of a pull-up
resistor. The output circuitry controls the fall time of
the output signal with the use of a slope controlled
pull-down. The circuit is designed for 400kHz 2-wire
interface speeds.
VBACK
This input provides a backup supply voltage to the
device. VBACK supplies power to the device in the
event the VCC supply fails.
Reading the Real Time Clock
The RTC is read by initiating a Read command and
specifying the address corresponding to the register of
the Real Time Clock. The RTC Registers can then be
read in a Sequential Read Mode. Since the clock runs
continuously and a read takes a finite amount of time,
there is the possibility that the clock could change during the course of a read operation. In this device, the
time is latched by the read command (falling edge of
X1, X2
The X1 and X2 pins are the input and output, respectively, of an inverting amplifier that can be configured
for use as an on-chip oscillator. A 32.768kHz quartz
crystal is used. Recommeded crystals are Sieko VT-200
or Epson C-002RX. The crystal supplies a timebase
for a clock/oscillator. The internal clock can be driven
by an external signal on X1, with X2 left unconnected.
2
X1240
the clock on the ACK bit prior to RTC data output) into
a separate latch to avoid time changes during the read
operation. The clock continues to run.
The CCR is divided into 3 sections. These are:
1. Control (2 bytes)
2. Real Time Clock (8 bytes)
3. Status (1 byte)
Writing to the Real Time Clock
The time and date may be set by writing to the RTC
registers. To avoid changing the current time by an
uncompleted write operation, the current time value is
loaded into a seperate buffer at the falling edge of the
clock on the ACK bit before the RTC data input bytes,
the clock continues to run. The new serial input data
replaces the values in the buffer. This new RTC value
is loaded back into the RTC Register by a stop bit at
the end of a valid write sequence. An invalid write
operation aborts the time update procedure and the
contents of the buffer are discarded. After a valid write
operation the RTC will reflect the newly loaded data
beginning with the first “one second” clock cycle after
the stop bit. The RTC continues to update the time
while an RTC register write is in progress and the RTC
continues to run during any nonvolatile write sequences.
A single byte may be written to the RTC without affecting the other bytes.
Sections 1) and 2) are nonvolatile and Section 3) is
volatile. Each register is read and written through buffers. The non-volatile portion (or the counter portion of
the RTC) is updated only if RWEL is set and only after
a valid write operation and stop bit. A sequential read or
page write operation provides access to the contents
of only one section of the CCR per operation. Access
to another section requires a new operation. Continued reads or writes, once reaching the end of a section, will wrap around to the start of the section. A read
or page write can begin at any address in the CCR.
Section 3) is a volatile register. It is not necessary to set
the RWEL bit prior to writing the status register. Section 3)
supports a single byte read or write only. Continued reads
or writes from this section terminates the operation.
The state of the CCR can be read by performing a random read at any address in the CCR at any time. This
returns the contents of that register location. Additional
registers are read by performing a sequential read.
The read instruction latches all Clock registers into a
buffer, so an update of the clock does not change the
time being read. A sequential read of the CCR will not
result in the output of data from the memory array. At
the end of a read, the master supplies a stop condition
to end the operation and free the bus. After a read of
the CCR, the address remains at the previous address
+1 so the user can execute a current address read of
the CCR and continue reading the next Register.
CLOCK/CONTROL REGISTERS (CCR)
The Control/Clock Registers are located in an area
logically separated from the array and are only accessible following a slave byte of “1101111x” and reads or
writes to addresses [0000h:003Fh].
CCR access
The contents of the CCR can be modified by performing
a byte or a page write operation directly to any address in
the CCR. Prior to writing to the CCR (except the status
register), however, the WEL and RWEL bits must be
set using a two step process (See section “Writing to
the Clock/Control Registers.”)
3
X1240
Addr.
003F
Type
Bit
Range
7
6
5
4
3
2
1
0 (optional)
SR
BAT
0
0
0
0
RWEL
WEL
RTCF
0037
Y2K
0
0
Y2K21
Y2K20
Y2K13
0
0
Y2K10
19/20
0036
DW
0
0
0
0
0
DY2
DY1
DY0
0-6
0035
YR
Y23
Y22
Y21
Y20
Y13
Y12
Y11
Y10
0-99
MO
0
0
0
G20
G13
G12
G11
G10
1-12
DT
0
0
D21
D20
D13
D12
D11
D10
1-31
0032
HR
MIL
0
H21
H20
H13
H12
H11
H10
0-23
0031
MN
0
M22
M21
M20
M13
M12
M11
M10
0-59
0030
SC
0
S22
S21
S20
S13
S12
S11
S10
0-59
0011
INT
0
0
0
0
0
0
0
0
00h
BL
BP2
BP1
BP0
0
0
0
0
0
00h
0034
0033
0010
Status
Reg
Name
Factroy
Settings
Table 1. Clock/Control Memory Map
RTC
(SRAM)
Control
(E2PROM)
REAL TIME CLOCK REGISTERS
Leap Years
Leap years add the day February 29 and are defined
as those years that are divisible by 4. Years divisible
by 100 are not leap years, unless they are also divisible by 400. This means that the year 2000 is a leap
year, the year 2100 is not. The X1240 does not correct
for the leap year in the year 2100.
Year 2000 (Y2K)
The X1240 has a century byte that “rolls over” from 19
to 20 when the years byte changes from 99 to 00. The
Y2K byte can contain only the values of 19 or 20.
Day of the Week Register (DW)
This register provides a Day of the Week status and
uses three bits DY2 to DY0 to represent the seven
days of the week. The counter advances in the cycle
0-1-2-3-4-5-6-0-1-2-... The assignment of a numerical
value to a specific day of the week is arbitrary and may
be decided by the system software designer. The
Clock Default values define 0=Sunday.
STATUS REGISTER (SR)
The Status Register is located in the RTC area at
address 003FH. This is a volatile register only and is
used to control the WEL and RWEL write enable
latches, and read a Low Voltage Sense bit. This register is logically seperated from both the array and the
Clock/Control Registers (CCR).
Clock/Calendar Registers (YR, MO, DT, HR, MN, SC)
These registers depict BCD representations of the
time. As such, SC (Seconds) and MN (Minutes) range
from 00 to 59, HR (Hour) is 1 to 12 with an AM or PM
indicator (H21 bit) or 0 to 23 (with MIL=1), DT (Date) is
1 to 31, MO (Month) is 1 to 12, YR (year) is 0 to 99.
Table 2. Status Register (SR)
24 Hour Time
If the MIL bit of the HR register is 1, the RTC will use a
24-hour format. If the MIL bit is 0, the RTC will use 12hour format and bit H21 will function as an AM/PM
indicator with a ‘1’ representing PM. The clock defaults
to Standard Time with H21=0.
Addr
7
6
5
4
3
2
1
0
003Fh
BAT
0
0
0
0
RWEL
WEL
RTCF
Default
0
0
0
0
0
0
0
0
BAT: Battery Supply—Volatile
This bit set to “1” indicates that the device is operating
from VBACK, not VCC. It is a read only bit and is set/
reset by hardware.
4
X1240
RWEL: Register Write Enable Latch—Volatile
This bit is a volatile latch that powers up in the LOW
(disabled) state. The RWEL bit must be set to “1” prior
to any writes to the Clock/Control Registers. Writes to
RWEL bit do not cause a nonvolatile write cycle, so the
device is ready for the next operation immediately after
the stop condition. A write to the CCR requires both the
RWEL and WEL bits to be set in a specific sequence.
Table 3. Block Protect Bits
BP1
BP0
Array Lock
BP2
WEL: Write Enable Latch—Volatile
The WEL bit controls the access to the CCR and memory array during a write operation. This bit is a volatile
latch that powers up in the LOW (disabled) state. While
the WEL bit is LOW, writes to the CCR or any array
address will be ignored (no acknowledge will be issued
after the Data Byte). The WEL bit is set by writing a “1”
to the WEL bit and zeroes to the other bits of the Status
Register. Once set, WEL remains set until either reset
to 0 (by writing a “0” to the WEL bit and zeroes to the
other bits of the Status Register) or until the part powers up again. Writes to WEL bit do not cause a non-volatile write cycle, so the device is ready for the next
operation immediately after the stop condition.
Protected Addresses
X1240
0
0
0
None
None
0
0
1
600h - 7FFh
Upper 1/4
0
1
0
400h - 7FFh
Upper 1/2
0
1
1
000h - 7FFh
Full Array
1
0
0
000h - 03Fh
First Page
1
0
1
000h - 07Fh
First 2 pgs
1
1
0
000h - 0FFh
First 4 pgs
1
1
1
000h - 1FFh
First 8 Pgs
WRITING TO THE CLOCK/CONTROL REGISTERS
Changing any of the nonvolatile bits of the clock/control
register requires the following steps:
—Write a 02H to the Status Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceeded by a start and ended with a stop).
RTCF: Real Time Clock Fail Bit—Volatile
This bit is set to a ‘1’ after a total power failure. This is a
read only bit that is set by hardware when the device
powers up after having lost all power to the device. The
bit is set regardless of whether VCC or VBACK is applied
first. The loss of one or the other supplies does not
result in setting the RTCF bit. The first valid write to the
RTC (writing one byte is sufficient) resets the RTCF bit
to ‘0’.
—Write a 06H to the Status Register to set both the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceeded by a start
and ended with a stop).
—Write one to 8 bytes to the Clock/Control Registers
with the desired clock, or control data. This sequence
starts with a start bit, requires a slave byte of
“11011110” and an address within the CCR and is
terminated by a stop bit. A write to the CCR changes
EEPROM values so these initiate a nonvolatile write
cycle and will take up to 10ms to complete. Writes to
undefined areas have no effect. The RWEL bit is
reset by the completion of a nonvolatile write write
cycle, so the sequence must be repeated to again initiate another change to the CCR contents. If the
sequence is not completed for any reason (by sending an incorrect number of bits or sending a start
instead of a stop, for example) the RWEL bit is not
reset and the device remains in an active mode.
Unused Bits:
These devices do not use bits 3 through 6, but must
have a zero in these bit positions. The Data Byte output
during a SR read will contain zeros in these bit locations.
CONTROL REGISTERS
Block Protect Bits - BP2, BP1, BP0 - (Nonvolatile)
The Block Protect Bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write to
a protected block of memory is ignored. The block protect bits will prevent write operations to one of eight
segments of the array. The partitions are described in
Table 3.
—Writing all zeros to the status register resets both the
WEL and RWEL bits.
—A read operation occurring between any of the previous operations will not interrupt the register write
operation.
—The RWEL and WEL bits can be reset by writing a 0
to the Status Register.
5
X1240
SERIAL COMMUNICATION
Start Condition
Interface Conventions
The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this family operate as slaves in all applications.
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met. See Figure 3.
Stop Condition
All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the Standby power mode after a read
sequence. A stop condition can only be issued after
the transmitting device has released the bus Refer to
Figure 3.
Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 3.
Figure 3. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable
Data Change
Data Stable
Figure 4. Valid Start and Stop Conditions
SCL
SDA
Start
Stop
6
X1240
Figure 5. Acknowledge Response From Receiver
SCL from Master
1
8
9
Data Output from
Transmitter
Data Output
from Receiver
Start
Acknowledge
Acknowledge
Acknowledge is a software convention used to indicate successful data transfer. The transmitting device,
either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 5.
WRITE OPERATIONS
Byte Write
For a byte write operation, the device requires the
Slave Address Byte and the Word Address Bytes. This
gives the master access to any one of the words in the
array or CCR. (Note: Prior to writing to the CCR, the
master must write a 02h, then 06h to the status register in preceding operations to enable the write operation. See “Writing to the Clock/Control Registers” on
page 6.) Upon receipt of each address byte, the
X1240 responds with an acknowledge. After receiving
both address bytes the X1240 awaits the eight bits of
data. After receiving the 8 data bits, the X1240 again
responds with an acknowledge. The master then terminates the transfer by generating a stop condition.
The X1240 then begins an internal write cycle of the
data to the nonvolatile memory. During the internal
write cycle, the device inputs are disabled, so the
device will not respond to any requests from the master.
The SDA output is at high impedance. See Figure 6.
The device will respond with an acknowledge after
recognition of a start condition and if the correct
Device Identifier and Select bits are contained in the
Slave Address Byte. If a write operation is selected,
the device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for:
—The Slave Address Byte when the Device Identifier
and/or Select bits are incorrect
—All Data Bytes of a write when the WEL in the Write
Protect Register is LOW
A write to a protected block of memory is ignored, but
will still receive an acknowledge. At the end of the
write command, the X1240 will not initiate an internal
write cycle, and will continue to ACK commands.
—The 2nd Data Byte of a Register Write Operation
(when only 1 data byte is allowed)
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.
7
X1240
Figure 6. Byte Write Sequence
S
t
a
r
t
Signals from
the Master
SDA Bus
Word
Address 1
Slave
Address
1
1 11 0
Signals from
the Slave
Word
Address 0
S
t
o
p
Data
0000 0
A
C
K
A
C
K
A
C
K
A
C
K
Figure 7. Writing 30 bytes to a 64-byte page starting at adress 40.
7 bytes
23 bytes
address pointer
ends here
Addr = 7
address
=6
address
40
address
63
Figure 8. Page Write Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
S
t
a
r
t
(1 < n < 64)
Word
Address 1
Slave
Address
1
1 1 10
Word
Address 0
Data
(1)
S
t
o
p
Data
(n)
0 00 0 0
A
C
K
A
C
K
Page Write
The X1240 has a page write operation. It is initiated in
the same manner as the byte write operation; but instead
of terminating the write cycle after the first data byte is
transferred, the master can transmit up to 63 more bytes
to the memory array and up to 7 more bytes to the
clock/control registers. (Note: Prior to writing to the
CCR, the master must write a 02h, then 06h to the status register in two preceding operations to enable the
write operation. See “Writing to the Clock/Control Registers” on page 5.)
A
C
K
A
C
K
After the receipt of each byte, the X1240 responds
with an acknowledge, and the address is internally
incremented by one. When the counter reaches the
end of the page, it “rolls over” and goes back to the
first address on the same page. This means that the
master can write 64 bytes to a memory array page or 8
bytes to a CCR section starting at any location on that
page. If the master begins writing at location 40 of the
memory and loads 30 bytes, then the first 23 bytes are
written to addresses 40 through 63, and the last 7
bytes are written to columns 0 through 6. Afterwards,
8
X1240
Figure 9. Acknowledge Polling Sequence
the address counter would point to location 7 on the
page that was just written. If the master supplies more
than the maximum bytes in a page, then the previously
loaded data is over written by the new data, one byte at
a time.
Byte load completed
by issuing STOP.
Enter ACK Polling
The master terminates the Data Byte loading by issuing
a stop condition, which causes the device to begin the
non-volatile write cycle. As with the byte write operation,
all inputs are disabled until completion of the internal
write cycle. Refer to Figure 8 for the address, acknowledge, and data transfer sequence.
Issue START
Issue Slave
Address Byte
(Read or Write)
Stops and Write Modes
Stop conditions that terminate write operations must be
sent by the master after sending at least 1 full data byte
and it’s associated ACK signal. If a stop is issued in the
middle of a data byte, or before 1 full data byte + ACK is
sent, then the device will reset itself without performing
the write. The contents of the array will not be affected.
ACK
returned?
Issue STOP
NO
YES
nonvolatile write
Cycle complete.
Continue command
sequence?
Acknowledge Polling
The disabling of the inputs during non-volatile write
cycles can be used to take advantage of the typical
5mS write cycle time. Once the stop condition is issued
to indicate the end of the master’s byte load operation,
the device initiates the internal non-volatile write cycle.
Acknowledge polling can be initiated immediately. To
do this, the master issues a start condition followed by
the Slave Address Byte for a write or read operation. If
the device is still busy with the non-volatile write cycle
then no ACK will be returned. If the device has completed the write operation, an ACK will be returned and
the host can then proceed with the read or write operation.
Refer to the flow chart in Table 9.
NO
Issue STOP
YES
Continue normal
Read or Write
command
sequence
PROCEED
Upon receipt of the Slave Address Byte with the R/W bit
set to one, the device issues an acknowledge and then
transmits the eight bits of the Data Byte. The master terminates the read operation when it does not respond
with an acknowledge during the ninth clock and then
issues a stop condition. Refer to Figure 10 for the
address, acknowledge, and data transfer sequence.
READ OPERATIONS
There are three basic read operations: Current Address
Read, Random Read, and Sequential Read.
Current Address Read
Internally the device contains an address counter that
maintains the address of the last word read incremented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power up, the sixteen bit address
is initialized to 0h. In this way, a current address read
can be initiated immediately after the power on reset to
download the contents of memory starting at the first
location.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condition
during the ninth cycle or hold SDA HIGH during the
ninth clock cycle and then issue a stop condition.
9
X1240
Figure 10. Current Address Read Sequence
Signals from
the Master
SDA Bus
S
t
a
r
t
S
t
o
p
Slave
Address
1
11 11
A
C
K
Signals from
the Slave
Data
newly loaded address. This operation could be useful
if the master knows the next address it needs to read,
but is not ready for the data.
Random Read
Random read operation allows the master to access
any memory location in the array. Prior to issuing the
Slave Address Byte with the R/W bit set to one, the
master must first perform a “dummy” write operation.
Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indicating it requires additional data. The device continues to
output data for each acknowledge received. The master
terminates the read operation by not responding with
an acknowledge and then issuing a stop condition.
The master issues the start condition and the Slave
Address Byte, receives an acknowledge, then issues
the Word Address Bytes. After acknowledging receipts
of the Word Address Bytes, the master immediately
issues another start condition and the Slave Address
Byte with the R/W bit set to one. This is followed by an
acknowledge from the device and then by the eight bit
word. The master terminates the read operation by not
responding with an acknowledge and then issuing a
stop condition. Refer to Figure 11 for the address,
acknowledge, and data transfer sequence.
The data output is sequential, with the data from address
n followed by the data from address n + 1. The address
counter for read operations increments through all page
and column addresses, allowing the entire memory
contents to be serially read during one operation. At
the end of the address space the counter “rolls over” to
the start of the address space and the device continues
to output data for each acknowledge received. Refer
to Figure 12 for the acknowledge and data transfer
sequence.
In a similar operation, called “Set Current Address,”
the device sets the address if a stop is issued instead of
the second start shown in Figure 11. The X1240 then
goes into standby mode after the stop and all bus activity
will be ignored until a start is detected. This operation
loads the new address into the address counter. The next
Current Address Read operation will read from the
Figure 11. Random Address Read Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
S
t
a
r
t
Slave
Address
1
Word
Address 0
Word
Address 1
1110
S
t
a
r
t
0 0 0 00
A
C
K
1
A
C
K
10
A
C
K
S
t
o
p
Slave
Address
111 1
A
C
K
Data
X1240
DEVICE ADDRESSING
Following the Slave Byte is a two byte word address.
The word address is either supplied by the master
device or obtained from an internal counter. On power
up the internal address counter is set to address 0h,
so a current address read of the EEPROM array starts
at address 0. When required, as part of a random
read, the master device must supply the 2 Word
Address Bytes.
Following a start condition, the master must output a
Slave Address Byte. The first four bits of the Slave
Address Byte specify access to the EEPROM array or
to the CCR. Slave bits ‘1010’ access the EEPROM
array. Slave bits ‘1101’ access the CCR.
Bit 3 through Bit 1 of the slave byte specify the device
select bits. These are set to ‘111’.
In a random read operation, the slave byte in the
“dummy write” portion must match the slave byte in
the “read” section. That is if the random read is from
the array the slave byte must be ‘1010111x’ in both
instances. Similarly, for a random read of the Clock/
Control Registers, the slave byte must be ‘1101111x’
in both places.
The last bit of the Slave Address Byte defines the
operation to be performed. When this R/W bit is a one,
then a read operation is selected. A zero selects a
write operation. Refer to Figure 12.
After loading the entire Slave Address Byte from the
SDA bus, the device compares the device identifier
and device select bits with ‘1010111’ or ‘1101111’.
Upon a correct compare, the device outputs an
acknowledge on the SDA line.
Figure 12. Sequential Read Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
Slave
Address
A
C
K
A
C
K
A
C
K
1
A
C
K
Data
(2)
Data
(1)
11
Data
Data
(n-1)
(n)
(n is any integer greater than 1)
S
t
o
p
X1240
Figure 13. Slave Address, Word Address, and Data Bytes (64 Byte pages)
Device Identifier
Array
CCR
1
Slave Address Byte
Byte 0
0
1
1
0
0
1
1
1
1
0
0
0
0
0
A10
A9
A8
High Order Word Address
Byte 1
A7
A6
A5
A4
A3
A2
A1
A0
Low Order Word Address
Byte 2
D7
D6
D5
D4
D3
D2
D1
D0
Data Byte
Byte 3
1
12
R/W
X1240
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Temperature Under Bias .................. -65˚C to +135˚C
Storage Temperature ....................... -65˚C to +150˚C
Voltage on any pin with respect to ground-1.0V to 7.0V
DC Output Current .............................................5 mA
Lead Temperature (Soldering, 10 Seconds) .... 300˚C
DC OPERATING CHARACTERISTICS (Temperature = -40°c to +85°c, unless otherwise stated.)
Symbol
Parameter
Min
Typ
Max
Unit
Notes
Vcc
Main Power Supply
2.7
3.6
V
VBACK
Backup Power Supply
1.8
3.6
V
VCB
Switch to Backup Supply
VCC =
VBACK -0.2
VBACK -0.1
V
(17)
VBC
Switch to Main Supply
VCC =
VBACK
VBACK +0.1
V
(17)
ICC1
Read Active Supply Current
VCC = 2.7V
400
µA
(5), (8), (15)
VCC = 3.6V
800
µA
VCC = 2.7V
1.5
mA
VCC = 3.6V
3.0
mA
VCC = 2.7V
1.7
µA
VCC = 3.6V
1.5
µA
VBACK = 1.8V
1.0
µA
VBACK = 3.6V
1.5
µA
ICC2
Program Supply Current
(nonvolatile)
ICC3
Main Timekeeping Current
IBACK1
IBACK2
Backup Timekeeping Current
Backup Supply Current
(External crystal network)
(5), (8), (16), (17)
(5), (7), (16), (17)
(7), (10), (16),
(17)
VBACK = 1.8V
1.6
3
µA
VBACK = 3.6V
7.5
10
µA
(7), (10), (16),
(17)
ILI
Input Leakage Current
10
µA
(11)
ILO
Output Leakage Current
10
µA
(11)
VIL
Input LOW Voltage
-0.5
VCC x 0.2 or
VBACK x 0.2
V
(5), (14)
VIH
Input HIGH Voltage
VCC x 0.7 or
VBACK x 0.7
VCC + 0.5
VBACK + 0.5
V
(5), (14)
VHYS
Schmitt Trigger Input
Hysteresis
Vcc related level
V
(14)
VOL
Output LOW Voltage
VCC = 2.7V
0.4
V
(12)
VCC = 3.6V
0.4
V
(13)
VOH
Output HIGH Voltage
Notes: (1)
(2)
.05 x VCC or
.05 x VBACK
VCC = 2.7V
1.6
VCC = 3.6V
2.4
The device enters the Active state after any start, and remains active: for 9 clock cycles if the Device Select Bits in the Slave
AddressByte are incorrect or until 200nS after a stop ending a read or write operation.
The device enters the Program state 200nS after a stop ending a write operation and continues for t WC.
13
X1240
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
The device goes into the Timekeeping state 200nS after any stop, except those that initiate a non-volatile write cycle; t WC after a
stop that initiates a non-volatile write cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in
the Slave Address Byte.
For reference only and not tested.
VIL = VCC x 0.1, VIH = VCC x 0.9, fSCL = 400KHz, SDA = Open
VIL = VCC x 0.1, VIH = VCC x 0.9, fSCL = 400KHz, fSDA = 400KHz, Vcc = 1.22 x Vcc Min
VCC = 0V.
VBACK= 0V.
VSDA=VSCL=VCC, Others=GND or VCC
VSDA=VSCL=VBACK, Others=GND or VBACK
VSDA = GND to VCC, VCLK = GND or VCC
IOL = 3.0mA at 5V, 1.5mA at 2.7V
IOH = -1.0mA at 5V, -0.4mA at 2.7V
Threshold voltages based on the higher of Vcc or Vback.
Driven by external 32.768KHz square wave oscillator on X1, X2 open.
Using recommended crystal and oscillator network applied to X1 and X2 (25°C).
Periodically sampled and not 100% tested.
CAPACITANCE (TA = 25˚C, f = 1.0 MHz, VCC = 5V)
Symbol
COUT
Parameter
Max
Units
Test Conditions
(Notes:)
Output Capacitance (SDA)
8
pF
VOUT = 0V
CIN (Notes:)
Input Capacitance (SCL)
6
pF
VIN = 0V
Notes: (1) This parameter is periodically sampled and not 100% tested.
AC CHARACTERISTICS
AC Test Conditions
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
Input Rise and Fall Times
10ns
Input and Output Timing
Levels
VCC x 0.5
Output Load
Standard Output Load
EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR
VCC = 5V (Standard Output Load for testing the device
with VCC = 5.0V)
5.0V
1533Ω
SDA
100pF
14
For VOL= 0.4V
and IOL = 3 mA
X1240
AC SPECIFICATIONS (TA = -40˚C to +85˚C, VCC = +2.7V to +3.6V, unless otherwise specified.)
Symbol
Parameter
Min
Max
Units
400
KHz
fSCL
SCL Clock Frequency
0
tIN
Pulse width Suppression Time at inputs
50
tAA
SCL LOW to SDA Data Out Valid
0.1
tBUF
Time the bus must be free before a new transmission
can start
1.3
µS
tLOW
Clock LOW Time
1.3
µS
tHIGH
Clock HIGH Time
0.6
µS
tSU:STA
Start Condition Setup Time
0.6
µS
tHD:STA
Start Condition Hold Time
0.6
µS
tSU:DAT
Data In Setup Time
100
nS
tHD:DAT
Data In Hold Time
0
µS
tSU:STO
Stop Condition Setup Time
0.6
µS
tDH
Data Output Hold Time
50
nS
tR
SDA and SCL Rise Time
tF
SDA and SCL Fall Time
Cb
Capacitive load for each bus line
nS
0.9
20
+.1Cb(3)
300
nS
20
+.1Cb(3)
300
nS
400
pF
Notes: (1) Typical values are for TA = 25˚C and VCC = 5.0V
(2) This parameter is periodically sampled and not 100% tested.
(3) Cb = total capacitance of one bus line in pF.
TIMING DIAGRAMS
Bus Timing
tF
SCL
tHIGH
tLOW
tR
tSU:DAT
tSU:STA
SDA IN
tHD:STA
tHD:DAT
tSU:STO
tAA tDH
SDA OUT
15
µS
tBUF
X1240
Write Cycle Timing
SCL
SDA
8th bit of last byte
ACK
tWC
Stop
Condition
Start
Condition
Power Up Timing
Symbol
Parameter
Min.
Typ(1)
Max.
Units
tPUR(1)
Time from Power Up to Read
1
mS
(1)
Time from Power Up to Write
5
mS
tPUW
Notes: (1) Delays are measured from the time VCC is stable until the specified operation can be initiated. These parameters are periodically
sampled and not 100% tested.
(2) Typical values are for TA = 25˚C and VCC = 5.0V
Nonvolatile Write Cycle Timing
Symbol
tWC(1)
Parameter
Min.
Write Cycle Time
Typ.(1)
Max.
Units
5
10
mS
Notes: (1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.
It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
16
X1240
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.020 (0.50) X 45°
0.050" TYPICAL
0.050"
TYPICAL
0° – 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS)
17
0.030"
TYPICAL
8 PLACES
X1240
8-LEAD PLASTIC, TSSOP, PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.114 (2.9)
.122 (3.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° – 8°
Seating Plane
.019 (.50)
.029 (.75)
(4.16) (7.72)
Detail A (20X)
(1.78)
.031 (.80)
.041 (1.05)
(0.42)
(0.65)
ALL MEASUREMENTS ARE TYPICAL
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
18
X1240
ORDERING INFORMATION
Vcc Range
Package
8L SOIC
2.7-3.6V
8L TSSOP
Operating
Temperature Range
Part Number
16Kb EEPROM
0oC – 70oC
X1240S8
-40oC – 85oC
X1240S8I
0oC – 70oC
X1240V8
-40o
o
X1240V8I
C – 85 C
Part Mark Information
8Pin PDIP/8-Lead SOIC
8-Lead TSSOP
X1240 X
XX
EYWW
XXXXX
Blank = 8-Lead SOIC
Blank = 2.7 to 3.6V, 0 to +70°C
I = 2.7 to 3.6V, -40 to +85°C
X1240 = 2.7 to 3.6V, 0 to +70°C
X1240I = 2.7 to 3.6V, -40 to +85°C
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc.
makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the
described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the
right to discontinue production and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.
Copyright 1999. Xicor, Inc. All rights reserved. Printed in the USA. Xicor, Inc. is a registered trademark. All other trademarks or service marks
mentioned in this document are the property of their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967;
4,883, 976. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1.
Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or
sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury to the user.
2.
A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or effectiveness.
19