Preliminary Information Pin 7 No Connect X24042 X24042 4K 512 x 8 Bit Serial E2PROM TYPICAL FEATURES DESCRIPTION • • The X24042 is a CMOS 4,096 bit serial E2PROM, internally organized 512 x 8. The X24042 features a serial interface and software protocol allowing operation on a simple two wire bus. • • • • • • 2.7V to 5.5V Power Supply Low Power CMOS —Active Read Current Less Than 1 mA —Active Write Current Less Than 3 mA —Standby Current Less Than 50 µA Internally Organized 512 x 8 2 Wire Serial Interface —Bidirectional Data Transfer Protocol Sixteen Byte Page Write Mode —Minimizes Total Write Time Per Byte Self Timed Write Cycle —Typical Write Cycle Time of 5 ms High Reliability —Endurance: 100,000 Cycles —Data Retention: 100 Years 8 Pin Mini-DlP and 8 Pin SOIC Packages The X24042 is fabricated with Xicor’s advanced CMOS Textured Poly Floating Gate Technology. The X24042 utilizes Xicor’s proprietary Direct WriteTM cell providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. FUNCTIONAL DIAGRAM (8) VCC (4) VSS (5) SDA H.V. GENERATION TIMING & CONTROL START CYCLE START STOP LOGIC CONTROL LOGIC (6) SCL SLAVE ADDRESS REGISTER +COMPARATOR LOAD (3) A2 INC E2PROM 32 X 128 XDEC WORD ADDRESS COUNTER (2) A1 (1) A0 R/W YDEC 8 CK PIN DATA REGISTER DOUT DOUT ACK 3849 FHD F01 © Xicor, 1991 Patents Pending 3849-1 1 Characteristics subject to change without notice X24042 PIN DESCRIPTIONS PIN CONFIGURATION Serial Clock (SCL) DIP/SOIC The SCL input is used to clock all data into and out of the device. A0 1 8 VCC A1 2 7 NC A2 3 6 SCL VSS 4 5 SDA Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. X24042 3849 FHD F02 An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Pull-Up Resistor selection graph at the end of this data sheet. PIN NAMES Address (A0) A0 is unused by the X24042, however, it must be tied to VSS to insure proper device operation. Address (A1, A2) The Address inputs are used to set the appropriate bits of the seven bit slave address. These inputs can be used static or actively driven. If used statically they must be tied to VSS or VCC as appropriate. If driven they must be driven to VSS or to VCC. Symbol Description A0–A2 SDA SCL NC VSS VCC Address Inputs Serial Data Serial Clock No Connect Ground Supply Voltage 3849 PGM T01 2 X24042 DEVICE OPERATION Start Condition The X24042 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers, and provide the clock for both transmit and receive operations. Therefore, the X24042 will be considered a slave in all applications. All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X24042 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used by the X24042 to place the device into the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2. Figure 1. Data Validity SCL SDA DATA STABLE DATA CHANGE 3849 FHD F06 Figure 2. Definition of Start and Stop SCL SDA START BIT STOP BIT 3849 FHD F07 3 X24042 Acknowledge after the receipt of each subsequent eight bit word. Acknowledge is a software convention used to indicate successful data transfers. The transmitting device will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 3. In the read mode the X24042 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the X24042 will continue to transmit data. If an acknowledge is not detected, the X24042 will terminate further data transmissions. The master must then issue a stop condition to return the X24042 to the standby power mode and place the device into a known state. The X24042 will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the X24042 will respond with an acknowledge Figure 3. Acknowledge Response From Receiver SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE 3849 FHD F08 4 X24042 DEVICE ADDRESSING The last bit of the slave address defines the operation to be performed. When set to one a read operation is selected, when set to zero a write operation is selected. Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (see Figure 4). For the X24042 this is fixed as 1010[B]. Following the start condition, the X24042 monitors the SDA bus comparing the slave address being transmitted with its slave address (device type and state of the A2 and A1 inputs). Upon a correct compare the X24042 outputs an acknowledge on the SDA line. Depending on the state of the R/W bit, the X24042 will execute a read or write operation. Figure 4. Slave Address HIGH ORDER WORD ADDRESS DEVICE TYPE IDENTIFIER WRITE OPERATIONS 1 0 1 0 A2 A1 DEVICE ADDRESS A0 R/W Byte Write For a write operation, the X24042 requires a second address field. This address field is the word address, comprised of eight bits, providing access to any one of the 512 words in the selected page of memory. Upon receipt of the word address the X24042 responds with an acknowledge, and awaits the next eight bits of data, again responding with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the X24042 begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress the X24042 inputs are disabled, and the device will not respond to any requests from the master. Refer to Figure 5 for the address, acknowledge and data transfer sequence. 3849 FHD F09 The next two significant bits addresses a particular device. A system could have up to four X24042 devices on the bus (see Figure 10). The four addresses are defined by the state of the A1 and A2 input. The next bit of the slave address is an extension of the array’s address and is concatenated with the eight bits of address in the word address field, providing direct access to the whole 512 x 8 array. Figure 5. Byte Write S T BUS ACTIVITY: A R MASTER T SDA LINE BUS ACTIVITY: X24042 SLAVE ADDRESS WORD ADDRESS S T O P DATA S P A C K A C K A C K 3849 FHD F10 5 X24042 Flow 1. ACK Polling Sequence Page Write The X24042 is capable of a sixteen byte page write operation. It is initiated in the same manner as the byte write operation, but instead of terminating the write cycle after the first data word is transferred, the master can transmit up to seven more words. After the receipt of each word, the X24042 will respond with an acknowledge. WRITE OPERATION COMPLETED ENTER ACK POLLING ISSUE START After the receipt of each word, the three low order address bits are internally incremented by one. The high order eight bits of the word address remain constant. The master should not transmit more than eight words prior to generating the stop condition. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. Refer to Figure 6 for the address, acknowledge and data transfer sequence. ISSUE SLAVE ADDRESS AND R/W = 0 ACK RETURNED? Acknowledge Polling ISSUE STOP NO YES The disabling of the inputs can be used to take advantage of the typical 5 ms write cycle time. Once the stop condition is issued to indicate the end of the host’s write operation the X24042 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the X24042 is still busy with the write operation no ACK will be returned. If the X24042 has completed the write operation an ACK will be returned and the host can then proceed with the next read or write operation. Refer to Flow 1. NEXT OPERATION A WRITE? NO YES ISSUE STOP ISSUE BYTE ADDRESS PROCEED PROCEED 3849 FHD F11 Figure 6. Page Write S T BUS ACTIVITY: A R MASTER T SDA LINE BUS ACTIVITY: X24042 SLAVE ADDRESS WORD ADDRESS n DATA n DATA n+1 S T O P DATA n+15 S P A C K A C K A C K NOTE: In this example n = xxxx 000 (B); x = 1 or 0 6 A C K A C K 3849 FHD F12 X24042 The read operation is terminated by the master; by not responding with an acknowledge and by issuing a stop condition. Refer to Figure 7 for the sequence of address, acknowledge and data transfer. READ OPERATIONS Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the slave address is set to a one. There are three basic read operations: current address read, random read and sequential read. Random Read Random read operations allow the master to access any memory location in a random manner. Prior to issuing the slave address with the R/W bit set to one, the master must first perform a “dummy” write operation. The master issues the start condition, and the slave address followed by the word address it is to read. After the word address acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to one. This will be followed by an acknowledge from the X24042 and then by the eight bit word. The read operation is terminated by the master; by not responding with an acknowledge and by issuing a stop condition. Refer to Figure 8 for the address, acknowledge and data transfer sequence. It should be noted that the ninth clock cycle of the read operation is not a “don’t care.” To terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a stop condition. Current Address Read Internally the X24042 contains an address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n + 1. Upon receipt of the slave address with R/W set to one, the X24042 issues an acknowledge and transmits the eight bit word. Figure 7. Current Address Read S T BUS ACTIVITY: A R MASTER T SDA LINE S T O P SLAVE ADDRESS S P A C K BUS ACTIVITY: X24042 DATA 3849 FHD F13 Figure 8. Random Read S T BUS ACTIVITY: A R MASTER T SDA LINE BUS ACTIVITY: X24042 S T A R T WORD ADDRESS n SLAVE ADDRESS S T O P SLAVE ADDRESS S S A C K A C K P A C K DATA n 3849 FHD F14 7 X24042 Sequential Read The data output is sequential, with the data from address n followed by the data from n + 1. The address counter for read operations increments all address bits, allowing the entire memory contents to be serially read during one operation. At the end of the address space (address 511) the counter “rolls over” to address 0 and the X24042 continues to output data for each acknowledge received. Refer to Figure 9 for the address, acknowledge and data transfer sequence. Sequential reads can be initiated as either a current address read or random access read. The first word is transmitted as with the other read modes; however, the master now responds with an acknowledge, indicating it requires additional data. The X24042 continues to output data for each acknowledge received. The read operation is terminated by the master; by not responding with an acknowledge and by issuing a stop condition. Figure 9. Sequential Read SLAVE BUS ACTIVITY: ADDRESS MASTER A C K A C K S T O P A C K P SDA LINE BUS ACTIVITY: X24042 A C K DATA n+1 DATA n DATA n+2 DATA n+x 3849 FHD F15 Figure 10. Typical System Configuration VCC PULL-UP RESISTORS SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER 3849 FHD F16 8 X24042 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ................. –65°C to +135°C Storage Temperature ...................... –65°C to +150°C Voltage on any Pin with Respect to VSS ................................. –1.0V to +7V D.C. Output Current ........................................... 5 mA Lead Temperature (Soldering, 10 Seconds) .............................. 300°C *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Commercial Industrial Military 0°C –40°C –55°C 70°C +85°C +125°C Supply Voltage Limits X24042 X24042-3 X24042-2.7 4.5V to 5.5V 3.0V to 5.5V 2.7V to 5.5V 3849 PGM T03 3849 PGM T02 D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified) Limits Symbol Parameter Min. Max. Units 1 3 mA ISB1(1) VCC Standby Current 150 µA ISB2(1) VCC Standby Current 50 µA VCC Supply Current (Read) VCC Supply Current (Write) lCC1 lCC2 ILI ILO VlL(2) VIH(2) VOL Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage 10 10 –1.0 VCC x 0.3 VCC x 0.7 VCC + 0.5 0.4 µA µA V V V Test Conditions SCL = VCC x 0.1/VCC x 0.9 Levels @ 100 KHz, SDA = Open, All Other Inputs = GND or VCC – 0.3V SCL = SDA = VCC – 0.3V, All Other Inputs = GND or VCC, VCC = 5.5V SCL = SDA = VCC – 0.3V, All Other Inputs = GND or VCC, VCC = 3V VIN = GND to VCC VOUT = GND to VCC IOL = 3 mA 3849 PGM T04 CAPACITANCE TA = 25°C, F = 1.0MHZ, VCC = 5V Symbol Test Max. Units Conditions CI/O(3) CIN(3) Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, SCL) 8 6 pF pF VI/O = 0V VIN = 0V 3849 PGM T05 Notes: (1) Must perform a stop command prior to measurement. (2) VIL min and VIH max. are for reference only and are not 100% tested. (3) This parameter is periodically sampled and not 100% tested. 9 X24042 A.C. CONDITIONS OF TEST Input Pulse Levels Input Rise and Fall Times I/O Timing Levels EQUIVALENT A.C. LOAD CIRCUIT 5.0V VCC x 0.1 to VCC x 0.9 1533Ω 10ns VCC x 0.5 Output 100pF 3849 PGM T06 3849 FHD F03 A.C. CHARACTERISTICS LIMITS (Over recommended operating conditions, unless otherwise specified). READ & WRITE CYCLE LIMITS Symbol tSCL tI tAA tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tDH Parameter Min. SCL Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs SCL Low to SDA Data Out Valid Time the Bus Must Be Free Before a New Transmission Can Start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time 0 0.3 4.7 Max. Units 100 100 3.5 KHz ns µs µs µs µs µs µs µs ns µs ns µs ns 4.0 4.7 4.0 4.7 0 250 1 300 4.7 300 3849 PGM T07 POWER-UP TIMING Symbol Parameter Max. Units tPUR(4) tPUW(4) Power-Up to Read Operation Power-Up to Write Operation 1 5 ms ms 3849 PGM T08 Bus Timing tHIGH tF tLOW tR SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO SDA IN tAA tDH tBUF SDA OUT 3849 FHD F04 Note: (4) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. 10 X24042 WRITE CYCLE LIMITS Symbol Parameter tWR(6) Write Cycle Time Min. Typ.(5) Max. Units 5 10 ms 3849 PGM T09 The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the X24042 bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. Write Cycle Timing SCL ACK 8th BIT SDA WORD n tWR STOP CONDITION START CONDITION X24042 ADDRESS 3849 FHD F05 Notes: (5) Typical values are for TA = 25°C and nominal supply voltage (5V). (6) tWR is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the device requires to perform the internal write operation. Guidelines for Calculating Typical Values of Bus Pull-Up Resistors SYMBOL TABLE WAVEFORM RESISTANCE (KΩ) 120 RMIN = 100 VCC MAX =1.8KΩ IOL MIN t MAX RMAX = R CBUS MAX. RESISTANCE 80 60 40 20 MIN. RESISTANCE 0 0 20 40 60 80 100 120 BUS CAPACITANCE (pF) 3849 FHD F17 11 INPUTS OUTPUTS Must be steady Will be steady May change from Low to High Will change from Low to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance X24042 NOTES 12 X24042 PACKAGING INFORMATION 8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P 0.430 (10.92) 0.360 (9.14) 0.092 (2.34) DIA. NOM. 0.255 (6.47) 0.245 (6.22) PIN 1 INDEX PIN 1 0.300 (7.62) REF. HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL 0.140 (3.56) 0.130 (3.30) SEATING PLANE 0.020 (0.51) 0.015 (0.38) 0.062 (1.57) 0.058 (1.47) 0.150 (3.81) 0.125 (3.18) 0.020 (0.51) 0.016 (0.41) 0.110 (2.79) 0.090 (2.29) 0.015 (0.38) MAX. 0.060 (1.52) 0.020 (0.51) 0.325 (8.25) 0.300 (7.62) 0° 15° TYP. 0.010 (0.25) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 13 X24042 PACKAGING INFORMATION 8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) PIN 1 INDEX PIN 1 0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7° 0.053 (1.35) 0.069 (1.75) 0.004 (0.19) 0.010 (0.25) 0.050 (1.27) 0.010 (0.25) X 45° 0.020 (0.50) 0° – 8° 0.0075 (0.19) 0.010 (0.25) 0.016 (0.41) 0.037 (0.937) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESIS IN MILLIMETERS) 14 X24042 ORDERING INFORMATION X24042 P T -V VCC Limits Blank = 4.5V to 5.5V 3 = 3.0 to 5.5V 2.7 = 2.7V to 5.5V Device Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C M = Military = –55°C to +125°C Package P = 8-Lead Plastic DIP S8 = 8-Lead SOIC Part Mark Convention X24042 Blank = 8-Lead SOIC P = 8-Lead Plastic DIP S = 8-Lead SOIC X X Blank = 4.5V to 5.5V, 0°C to +70°C I = 4.5V to 5.5V, –40°C to +85°C D = 3.0V to 5.5V, 0°C to +70°C E = 3.0V to 5.5V, –40°C to +85°C F = 2.7V to 5.5V, 0°C to +70°C G = 2.7V to 5.5V, –40°C to +85°C LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 15