APPLICATION NOTE A V A I L A B L E X25401 AN56 X25401 256 Bit 16 x 16 Bit SPI Serial AUTOSTORE™ NOVRAM FEATURES DESCRIPTION • • The Xicor X25401 is a serial 256 bit NOVRAM featuring a static RAM configured 16 x 16, overlaid bit-by-bit with a nonvolatile E2PROM array. The X25401 features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple three-wire bus. The bus signals are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus. • • • • • • • • 1MHz Clock Rate AUTOSTORE™ NOVRAM —Automatically Performs a Store Operation Upon Loss of VCC Single 5 Volt Supply Ideal for use with Single Chip Microcomputers —Minimum I/O Interface —SPI Mode (0,0 & 1,1) Serial Port Compatible —Easily Interfaced to Microcontroller Ports Software and Hardware Control of Nonvolatile Functions Auto Recall on Power-Up TTL and CMOS Compatible Low Power Dissipation —Active Current: 10mA —Standby Current: 50µA 8-Lead PDIP and 8-Lead SOIC Packages High Reliability —Store Cycles: 1,000,000 —Data Retention: 100 Years The Xicor NOVRAM design allows data to be transferred between the two memory arrays by means of software commands or external hardware inputs. A store operation (RAM data to E2PROM) is completed in 5ms or less and a recall operation (E2PROM data to RAM) is completed in 2µs or less. The X25401 also includes the AUTOSTORE feature, a user selectable feature that automatically performs a store operation when VCC falls below a preset threshold. Xicor NOVRAMs are designed for unlimited write operations to RAM, either from the host or recalls from E2PROM and a minimum 1,000,000 store operations. Inherent data retention is specified to be greater than 100 years. FUNCTIONAL DIAGRAM CS (1) SI (3) SCK (2) INSTRUCTION REGISTER INSTRUCTION DECODE COLUMN DECODE EC R STATIC RAM 256-BIT ROW DECODE AL L ST O R E NONVOLATILE 2 E PROM CONTROL LOGIC RECALL (6) AS (7) SO (4) 4-BIT COUNTER 2051 FHD F01 AUTOSTORE™ NOVRAM is a trademark of Xicor, Inc. COPS is a trademark of National Semiconductor Corp. © Xicor, Inc. 1992, 1995, 1996 Patents Pending 2051-1.5 8/1/97 T0/C0/D2 SH 1 Characteristics subject to change without notice X25401 PIN DESCRIPTIONS PIN CONFIGURATION Chip Select (CS) The Chip Select input must be LOW to enable all read/ write operations. CS must remain LOW following a Read or Write command until the data transfer is complete. CS HIGH places the X25401 in the low power standby mode and resets the instruction register. Therefore, CS must be brought HIGH after the completion of an operation in order to reset the instruction register in preparation for the next command. DIP/SOIC CS 1 8 VCC SCK 2 7 AS 6 RECALL 5 VSS SI 3 SO 4 X25401 Serial Clock (SCK) 2051 FHD F02 The Serial Clock input is used to clock all data into and out of the device. Serial Data In (SI) SI is the serial data input. PIN NAMES Serial Data Out (SO) Symbol CS SCK SI SO RECALL AS VCC VSS SO is the serial data output. It is in the high impedance state except during data output cycles in response to a READ instruction. AUTOSTORE Output (AS) AS is an open drain output which, when asserted indicates VCC has fallen below the AUTOSTORE threshold (VASTH). AS may be wire-ORed with multiple open drain outputs and used as an interrupt input to a microcontroller or as an input to a low power reset circuit. Description Chip Enable Serial Clock Serial Data In Serial Data Out Recall Input AUTOSTORE Output +5V Ground 2051 PGM T01 RECALL RECALL LOW will initiate an internal transfer of data from E2PROM to the RAM array. 2 X25401 DEVICE OPERATION reset upon power-up and must be intentionally set by the user to enable any write or store operations. Although a recall operation is performed upon power-up, the previous recall latch is not set by this operation. The X25401 contains an 8-bit instruction register. It is accessed via the SI input, with data being clocked in on the rising edge of SCK. CS must be LOW during the entire data transfer operation. WRDS and WREN Table 1 contains a list of the instructions and their operation codes. The most significant bit (MSB) of all instructions is a logic one (HIGH), bits 6 through 3 are either RAM address bits (A) or don’t cares (X) and bits 2 through 0 are the operation codes. The X25401 requires the instruction to be shifted in with the MSB first. Internally the X25401 contains a “write enable” latch. This latch must be set for either writes to the RAM or store operations to the E2PROM. The WREN instruction sets the latch and the WRDS instruction resets the latch, disabling both RAM writes and E2PROM stores, effectively protecting the nonvolatile data from corruption. The write enable latch is automatically reset on power-up. After CS is LOW, the X25401 will not begin to interpret the data stream until a logic “1” has been shifted in on SI. Therefore, CS may be brought LOW with SCK running and SI LOW. SI must then go HIGH to indicate the start condition of an instruction before the X25401 will begin any action. STO The software STO instruction will initiate a transfer of data from RAM to E2PROM. In order to safeguard against unwanted store operations, the following conditions must be true: • STO instruction issued. • The internal “write enable” latch must be set (WREN instruction issued). • The “previous recall” latch must be set (either a software or hardware recall operation). In addition, the SCK clock is totally static. The user can completely stop the clock and data shifting will be stopped. Restarting the clock will resume shifting of data. RCL and RECALL Once the store cycle is initiated, all other device functions are inhibited. Upon completion of the store cycle, the write enable latch is reset. Refer to Figure 4 for a state diagram description of enabling/disabling conditions for store operations. Either a software RCL instruction or a LOW on the RECALL input will initiate a transfer of E2PROM data into RAM. This software or hardware recall operation sets an internal “previous recall” latch. This latch is TABLE 1. INSTRUCTION SET Instruction Format, I2 I1 I0 Operation WRDS (Figure 3) STO (Figure 3) ENAS WRITE (Figure 2) WREN (Figure 3) RCL (Figure 3) READ (Figure 1) 1XXXX000 1XXXX001 1XXXX010 1AAAA011 1XXXX100 1XXXX101 1AAAA11X Reset Write Enable Latch (Disables Writes and Stores) Store RAM Data in E2PROM Enable AUTOSTORE Feature Write Data into RAM Address AAAA Set Write Enable Latch (Enables Writes and Stores) Recall E2PROM Data into RAM Read Data from RAM Address AAAA 2051 PGM T11 X = Don’t Care A = Address 3 X25401 WRITE AUTOSTORE Feature The WRITE instruction contains the 4-bit address of the word to be written. The write instruction is immediately followed by the 16-bit word to be written. CS must remain LOW during the entire operation. CS must go HIGH before the next rising edge of SCK. If CS is brought HIGH prematurely (after the instruction but before 16 bits of data are transferred), the instruction register will be reset and the data that was shifted-in will be written to RAM. The AUTOSTORE instruction (ENAS) sets the “AUTOSTORE enable” latch, allowing the X25401 to automatically perform a store operation when VCC falls below the AUTOSTORE threshold (VASTH). If CS is kept LOW for more than 24 SCK clock cycles (8-bit instruction plus 16-bit data), the data already shifted-in will be overwritten. Power-Up Condition WRITE PROTECTION The X25401 provides two software write protection mechanisms to prevent inadvertent stores of unknown data. Upon power-up the “write enable” and “AUTOSTORE enable” latches are in the reset state, disabling any store operation. READ The READ instruction contains the 4-bit address of the word to be accessed. Unlike the other six instructions, I0 of the instruction word is a “don’t care”. This provides two advantages. In a design that ties both SI and SO together, the absence of an eighth bit in the instruction allows the host time to convert an I/O line from an output to an input. Secondly, it allows for valid data output during the ninth SCK clock cycle. Unknown Data Store All data bits are clocked by the falling edge of SCK (refer to Read Cycle Diagram). The X25401 performs a power-up recall that transfers the E2PROM contents to the RAM array. Although the data may be read from the RAM array, this recall does not set the “previous recall” latch. During this power-up recall operation, all commands are ignored. Therefore, the host should delay any operations with the X25401 a minimum of tPUR after VCC is stable. The “previous recall” latch must be set after power-up. It may be set only by performing a software or hardware recall operation, which assures that data in all RAM locations is valid. SYSTEM CONSIDERATIONS Power-Up Recall LOW POWER MODE When CS is HIGH, non-critical internal devices are powered-down, placing the device in the standby power mode, thereby minimizing power consumption. 4 X25401 Figure 1. RAM Read CS SCK 1 2 3 4 5 6 7 8 SI 1 A A A A 1 1 X* 9 10 11 12 22 23 24 HIGH Z SO D0 D1 D2 D3 D13 D14 D15 D0 *Bit 8 of Read Instructions is Don’t Care 2051 FHD F09.1 Figure 2. RAM Write CS SK 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 DI 1 A A A A 0 1 1 D0 D1 D2 D12 D13 D14 D15 2051 FHD F10.1 Figure 3. Non-Data Operations CS SCK 1 2 3 4 5 6 7 8 SI 1 X X X X I2 I1 I0 2051 FHD F11.1 5 X25401 Figure 4. X25401 State Diagram POWER ON POWER-UP RECALL POWER OFF RAM READ RAM READ ENABLED RCL COMMAND OR RECALL AUTOSTORE POWER DOWN STO OR WRDS CMD RAM READ OR WRITE RAM READ & WRITE ENABLED ENAS COMMAND STORE ENABLED WREN COMMAND RAM READ RAM READ ENABLED STO OR WRDS CMD WREN COMMAND RAM READ & WRITE ENABLED RAM READ OR WRITE STORE ENABLED AUTOSTORE ENABLED 2051 FHD F12.1 6 X25401 ABSOLUTE MAXIMUM RATINGS* Temperature under Bias .................. –65°C to +135°C Storage Temperature ....................... –65°C to +150°C Voltage on any Pin with Respect to VSS ....................................... –1V to +7V D.C. Output Current ............................................. 5mA Lead Temperature (Soldering, 10 seconds) .............................. 300°C *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Supply Voltage Limits Commercial Industrial Military 0°C –40°C –55°C +70°C +85°C +125°C X25401 5V ±10% 2051 PGM T03.2 2051 PGM T02.1 D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Limits Symbol Parameter lCC1 Min. VCC Supply Current (TTL Inputs) VCC Supply Current (During AUTOSTORE) VCC Standby Current (TTL Inputs) VCC Standby Current (CMOS Inputs) Input Load Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage (AS) ICC2 ISB1 ISB2 ILI ILO VlL(1) VIH(1) VOL VOH VOL(AS) –1 2 Max. Units 10 mA 2 mA 1 mA 50 µA 10 10 0.8 VCC + 1 0.4 µA µA V V V V V 2.4 0.4 Test Conditions SCK = 0.4V/2.4V Levels @ 1MHz, SO = Open, All Other Inputs = VIH All Inputs = VIH, CS = VIL SO = Open, VCC = 4.3V SO = Open, CS = VIL, All Other Inputs = VIH SO = Open, CS = VSS All Other Inputs = VCC – 0.3V VIN = VSS to VCC VOUT = VSS to VCC IOL = 4.2mA IOH = –2mA IOL (AS) = 1mA 2051 PGM T04.3 ENDURANCE AND DATA RETENTION Parameter Endurance Store Cycles Data Retention Min. Units 100,000 1,000,000 100 Data Changes Per Bit Store Cycles Years 2051 PGM T05 CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Symbol COUT(2) CIN(2) Parameter Output Capacitance Input Capacitance Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. 7 Max. Units Test Conditions 8 6 pF pF VOUT = 0V VIN = 0V 2051 PGM T06.2 X25401 EQUIVALENT A.C. LOAD CIRCUIT A.C. CONDITIONS OF TEST Input Pulse Levels 5V 0V to 3V Input Rise and Fall Times Input and Output Timing Levels 919Ω OUTPUT 10ns 1.5V 2051 PGM T07.1 497Ω 100pF 2051 FHD F03 A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Read and Write Cycle Limits Symbol FSK(3) tSCKH tSCKL tDS tDH tPD1 tPD tZ tCSS tCSH tCDS Parameter Min. SCK Frequency SCK Positive Pulse Width SCK Negative Pulse Width Data Setup Time Data Hold Time SCK to Data Bit 0 Valid SCK to Data Valid Chip Select to Output High Z Chip Select Setup Chip Select Hold Chip Deselect Max. Units 1 MHz ns ns ns ns ns ns µs ns ns ns 400 400 400 80 375 375 1 800 350 800 2051 PGM T08.1 POWER-UP TIMING Symbol Parameter Max. Units tPUR(4) tPUW(4) Power-up to Read Operation Power-up to Write or Store Operation 200 5 µs ms 2051 PGM T09 Notes: (3) SCK rise and fall times must be less than 50ns. (4) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. 8 X25401 Write Cycle 1/FSCK SCK CYCLE # tSCKH X SCK tSCKL 1 2 n tCSH tCSS tCDS CS tDS tDH SI 2051 FHD F04.1 Read Cycle SK CYCLE # 6 7 8 9 10 n SCK CS tPD SI 12 I1 DON’T CARE tPD1 SO tZ HIGH Z D0 D1 Dn HIGH Z 2051 FHD F05.1 9 X25401 NONVOLATILE OPERATIONS Operation RECALL Software Instruction Hardware Recall Software Recall Software Store 0 1 1 NOP(5) RCL STO Write Enable Latch State Previous Recall Latch State X X SET X X SET 2051 PGM T10 ARRAY RECALL LIMITS Symbol Parameter Min. tRCC tRCP tRCZ Recall Cycle Time Recall Pulse Width(6) Recall to Output in High Z 2 500 Max. Units 500 µs ns ns 2051 PGM T11 Recall Timing tRCC tRCP RECALL tRCZ HIGH Z SO 2051 FHD F06 SOFTWARE STORE CYCLE LIMITS Symbol Parameter Min. tST Store Time After Clock 8 of STO Command Typ.(7) Max. 2 5 Units ms 2051 PGM T12.1 Notes: (5) NOP designates when the X25401 is not currently executing an instruction. (6) Recall rise time must be <10µs. (7) Typical values are for TA = 25°C and nominal supply voltage. 10 X25401 AUTOSTORE Cycle Limits Symbol VASTO VASTH VASEND Parameter Min. AUTOSTORE Cycle Time AUTOSTORE Threshold Voltage AUTOSTORE Cycle End Voltage 4.0 3.5 Max. Units 5 4.3 ms V V 2051 PGM T13 AUTOSTORE Cycle Timing Diagrams VCC VOLTS (V) 5 4 AUTOSTORE CYCLE IN PROGRESS 3 VASTH VASEND 2 tASTO 1 STORE TIME TIME (ms) VCC VASTH 0V tPUR tASTO tPUR AS 2051 FHD F08 SYMBOL TABLE WAVEFORM 11 INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed N/A Changing: State Not Known Center Line is High Impedance X25401 PACKAGING INFORMATION 8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P 0.430 (10.92) 0.360 (9.14) 0.260 (6.60) 0.240 (6.10) PIN 1 INDEX PIN 1 0.300 (7.62) REF. HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL 0.145 (3.68) 0.128 (3.25) SEATING PLANE 0.025 (0.64) 0.015 (0.38) 0.065 (1.65) 0.045 (1.14) 0.150 (3.81) 0.125 (3.18) 0.020 (0.51) 0.016 (0.41) 0.110 (2.79) 0.090 (2.29) 0.015 (0.38) MAX. 0.060 (1.52) 0.020 (0.51) 0.325 (8.25) 0.300 (7.62) 0° 15° TYP. 0.010 (0.25) NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 3926 FHD F01 12 X25401 PACKAGING INFORMATION 8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) PIN 1 INDEX PIN 1 0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7° 0.053 (1.35) 0.069 (1.75) 0.004 (0.19) 0.010 (0.25) 0.050 (1.27) 0.010 (0.25) X 45° 0.020 (0.50) 0.050" TYPICAL 0.050" TYPICAL 0° – 8° 0.0075 (0.19) 0.010 (0.25) 0.250" 0.016 (0.410) 0.037 (0.937) 0.030" TYPICAL 8 PLACES FOOTPRINT NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 3926 FHD F22.1 13 X25401 ORDERING INFORMATION X25401 P T -V VCC Limits Blank = 5V ±10% Device Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C M = Military = –55°C to +125°C Package P = 8-Lead Plastic DIP S = 8-Lead SOIC LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. US. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use as critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its satety or effectiveness. 14