X2804C X2804C 4K 512 x 8 Bit 5 Volt, Byte Alterable E2PROM FEATURES DESCRIPTION • • The Xicor X2804C is a 512 x 8 E2PROM, fabricated with an advanced, high performance N-channel floating gate MOS technology. Like all Xicor Programmable nonvolatile memories it is a 5V only device. The X2804C features the JEDEC approved pinout for byte-wide memories, compatible with industry standard RAMs, ROMs and EPROMs. • • • • • 90ns Access Time Simple Byte and Page Write —Single 5V Supply —No External High Voltages or VPP Control Circuits —Self-Timed —No Erase Before Write —No Complex Programming Algorithms —No Overerase Problem High Performance Advanced NMOS Technology Fast Write Cycle Times —16 Byte Page Write Operation —Byte or Page Write Cycle: 5ms Typical —Complete Memory Rewrite: 640ms Typical —Effective Byte Write Cycle Time: 300µs Typical DATA Polling —Allows User to Minimize Write Cycle Time JEDEC Approved Byte-Wide Pinout High Reliability —Endurance: 10,000 Cycles —Data Retention: 100 Years The X2804C supports a 16-byte page write operation, typically providing a 300µs/byte write cycle, enabling the entire memory to be written in less than 640ms. The X2804C also features DATA Polling, a system software support scheme used to indicate the early completion of a write cycle. Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. PIN CONFIGURATION PLASTIC DIP A7 1 24 VCC A6 2 23 A8 A5 3 22 NC A4 4 21 WE A3 5 20 A2 6 19 OE NC A1 7 18 CE A0 8 17 I/O0 I/O1 9 16 I/O7 I/O6 10 15 I/O2 VSS 11 14 I/O5 I/04 12 13 I/O3 X2804C 6612 FHD F02.1 ©Xicor, Inc. 1993, 1995 Patents Pending 6612-1.3 3/27/96 T2/C1/D1 NS 1 Characteristics subject to change without notice X2804C PIN DESCRIPTIONS PIN NAMES Addresses (A0–A8) Symbol Description The Address inputs select an 8-bit memory location during a read or write operation. A0–A8 I/O0–I/O7 WE CE OE VCC VSS NC Address Inputs Data Input/Output Write Enable Chip Enable Output Enable +5V Ground No Connect Chip Enable (CE) The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power consumption is reduced. Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read operations. 6612 PGM T01 FUNCTIONAL DIAGRAM 4.096-BIT E2PROM ARRAY X BUFFERS LATCHES AND DECODER A0–A8 ADDRESS INPUTS I/O BUFFERS AND LATCHES Y BUFFERS LATCHES AND DECODER I/O0–I/O7 DATA INPUTS/OUTPUTS CE OE CONTROL LOGIC WE VCC VSS 6612 FHD F01 2 X2804C byte load cycle, started by the WE HIGH to LOW transition, must begin within 20µs of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 20µs, the internal automatic programming cycle will commence. There is no page write window limitation. The page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 20µs. DEVICE OPERATION Read Read operations are initiated by both OE and CE LOW and WE HIGH. The read operation is terminated by either CE or OE returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH. DATA Polling Write The X2804C features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the X2804C, eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on I/O7 (i.e., write data = 0xxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, I/O7 will reflect true data. Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X2804C supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 5ms. Page Write Operation WRITE PROTECTION The page write feature of the X2804C allows the entire memory to be typically written in 450ms. Page write allows two to sixteen bytes of data to be consecutively written to the X2804C prior to the commencement of the internal programming cycle. Although the host system may read data from any other device in the system to transfer to the X2804C, the destination page address of the X2804C should be the same on each subsequent strobe of the WE and CE inputs. That is, A4 through A10 must be the same for each transfer of data to the X2804C during a page write cycle. There are three features that protect the nonvolatile data from inadvertent writes. • Noise Protection—A WE pulse which is typically less than 10ns will not initiate a write cycle. • VCC Sense—All functions are inhibited when VCC is ≤3V, typically. • Write Inhibit—Holding either OE LOW, WE HIGH, or CE HIGH during power-up and power-down, will inhibit inadvertent writes. Write cycle timing specifications must be observed concurrently. The page write mode can be entered during any write operation. Following the initial byte write cycle, the host can write an additional one to fifteen bytes in the same manner as the first byte was written. Each successive ENDURANCE Xicor E2PROMs are designed and tested for applications requiring extended endurance. 3 X2804C prime concern. Enabling CE will cause transient current spikes. The magnitude of these spikes is dependent on the output capacitive loading of the l/Os. Therefore, the larger the array sharing a common bus, the larger the transient spikes. The voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. As a minimum, it is recommended that a 0.1µF high frequency ceramic capacitor be used between VCC and VSS at each device. Depending on the size of the array, the value of the capacitor may have to be larger. SYSTEM CONSIDERATIONS Because the X2804C is frequently used in large memory arrays, it is provided with a two line control architecture for both read and write operations. Proper usage can provide the lowest possible power dissipation and eliminate the possibility of contention where multiple I/O pins share the same bus. To gain the most benefit, it is recommended that CE be decoded from the address bus and be used as the primary device selection input. Both OE and WE would then be common among all devices in the array. For a read operation this assures that all deselected devices are in their standby mode and that only the selected device(s) is outputting data on the bus. In addition, it is recommended that a 4.7µF electrolytic bulk capacitor be placed between VCC and VSS for each eight devices employed in the array. This bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the PC board traces. Because the X2804C has two power modes, standby and active, proper decoupling of the memory array is of 4 X2804C ABSOLUTE MAXIMUM RATINGS* Temperature under Bias X2804C ....................................... –10°C to +85°C X2804CI ..................................... –65°C to +135°C Storage Temperature ....................... –65°C to +150°C Voltage on any Pin with Respect to VSS .................................. –1V to +7V D.C. Output Current ............................................. 5mA Lead Temperature (Soldering, 10 seconds)...... 300°C *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Supply Voltage Limits Commercial Industrial 0°C –40°C +70°C +85°C X2804C 5V ±10% 6612 PGM T03 6612 PGM T02.2 D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Limits Symbol Parameter Min. Typ.(1) Max. Units Test Conditions CE = OE = VIL All I/O’s = Open Other Inputs = VCC CE = VIH, OE = VIL All I/O’s = Open Other Inputs = VCC VIN = VSS to VCC VOUT = VSS to VCC, CE = VIH ICC VCC Current (Active) 70 110 mA ISB VCC Current (Standby) 35 50 mA ILI ILO VlL(2) VIH(2) VOL VOH Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage 10 10 0.8 VCC +1 0.4 µA µA V V V V –1 2 2.4 IOL = 2.1mA IOH = –400µA 6612 PGM T02.1 Notes: (1) Typical values are for TA = 25°C and nominal supply voltage and are not tested. (2) VIL min. and VIH max. are for reference only and are not tested. 5 X2804C ENDURANCE AND DATA RETENTION Parameter Min. Minimum Endurance Data Retention Max. Unit 10,000 100 Cycles/Byte Years 6612 PGM T03 POWER-UP TIMING Symbol Parameter Typ.(1) Units tPUR(3) Power-Up to Read Operation Power-Up to Write Operation 1 5 ms ms tPUW(3) 6612 PGM T04 CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Symbol Test Max. Units Conditions CI/O(3) CIN(3) Input/Output Capacitance Input Capacitance 10 6 pF pF VI/O = 0V VIN = 0V 6612 PGM T05.1 A.C. CONDITIONS OF TEST Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels MODE SELECTION 0V to 3V 5ns 1.5V 3852 PGM T06.1 CE OE WE Mode L L H X X L H X L X H L X X H Read Write Standby and Write Inhibit Write Inhibit Write Inhibit I/O Power DOUT Active DIN Active High Z Standby — — — — 6612 PGM T07 Note: (3) This parameter is periodically sampled and not 100% tested. EQUIVALENT A.C. LOAD CIRCUITS 5V 1.92KΩ OUTPUT 1.37KΩ 100pF 6612 FHD F22.3 6 X2804C A.C. CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Read Cycle Limits X2804C-90 Min. Max. Symbol Parameter tRC tCE tAA tOE tLZ(4) tOLZ(4) tHZ(4) tOHZ(4) tOH Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE LOW to Active Output OE LOW to Active Output CE HIGH to High Z Output OE HIGH to High Z Output Output Hold from Address Change 90 X2804C-15 Min. Max. X2804C-20 Min. Max. X2804C-25 Min. Max. 150 200 250 90 90 60 0 0 150 150 80 0 0 50 50 0 200 200 100 0 0 60 60 0 250 250 100 0 0 60 60 0 60 60 0 Units ns ns ns ns ns ns ns ns ns 6612 PGM T10.1 Read Cycle tRC ADDRESS tCE CE tOE OE VIH WE tOLZ tOHZ tLZ DATA I/O HIGH Z tOH DATA VALID tHZ DATA VALID tAA 6612 FHD F04 Notes: (4) tLZ min., tHZ, tOLZ, and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured from the point when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven. 7 X2804C Write Cycle Limits X2804C-90 Symbol tWC(5) tAS tAH tCS tCH tCW tOES tOEH tWP tWPH tDV tDS tDH tDW tBLC Parameter Min. Write Cycle Time Address Setup Time Address Hold Time Write Setup Time Write Hold Time CE Pulse Width OE HIGH Setup Time OE HIGH Hold Time WE Pulse Width WE HIGH Recovery Data Valid Data Setup Data Hold Delay to Next Write Byte Load Cycle Max. X2804C-15,-20,-25 Min. 10 5 80 0 0 80 10 5 80 50 Max. Units 10 ms ns ns ns ns ns ns ns ns ns µs ns ns µs µs 5 100 0 0 100 10 10 100 50 100 35 5 10 1 100 100 50 10 10 1 100 6612 PGM T09.1 WE Controlled Write Cycle tWC ADDRESS tAS tAH tCS tCH CE OE tOES tOEH tWP WE tDV DATA IN DATA VALID tDS DATA OUT tDH HIGH Z 6612 FHD F05 Notes: (5) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation. For faster tWC, please refer to X28C16 and X28HC16 product data sheets. 8 X2804C CE Controlled Write Cycle tWC ADDRESS tAS tAH tCW CE tOES OE tOEH tCS tCH WE tDV DATA IN DATA VALID tDS tDH HIGH Z DATA OUT 6612 FHD F06 Page Mode Write Cycle OE (6) CE tWP tBLC WE tWPH ADDR.* (7) I/O LAST BYTE BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n+1 BYTE n+2 tWC *For each successive write within the page write operation, A4–A10 should be the same or writes to an unknown address could occur. 6612 FHD F07.1 Notes: (6) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation. (7) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE or WE controlled write cycle timing. 9 X2804C DATA Polling Timing Diagram(10) ADDRESS An An An CE WE tOEH tOES OE tDW I/O7 DIN=X DOUT=X DOUT=X tWC 6612 FHD F08 Note: (10) Polling operations are by definition read cycles and are therefore subject to read cycle timings. SYMBOL TABLE WAVEFORM 10 INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed N/A Changing: State Not Known Center Line is High Impedance X2804C Normalized Active Supply Current vs. Ambient Temperature Normalized Standby Supply Current vs. Ambient Temperature 1.4 1.4 VCC = 5V NORMALIZED ISB NORMALIZED ICC VCC = 5V 1.2 1.0 0.8 1.0 0.8 0.6 0.6 –55 +25 –55 +25 +125 AMBIENT TEMPERATURE (°C) +125 AMBIENT TEMPERATURE (°C) 6612 FHD F09.1 6612 FHD F10.1 Normalized Access Time vs. Ambient Temperature 1.4 VCC = 5V NORMALIZED TAA 1.2 1.2 1.0 0.8 0.6 –55 +25 +125 AMBIENT TEMPERATURE (°C) 6612 FHD F11.1 11 X2804C PACKAGING INFORMATION 24-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P 1.265 (32.13) 1.230 (31.24) 0.557 (14.15) 0.530 (13.46) PIN 1 INDEX PIN 1 0.080 (2.03) 0.065 (1.65) 1.100 (27.94) REF. 0.162 (4.11) 0.140 (3.56) SEATING PLANE 0.030 (0.76) 0.015 (0.38) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.065 (1.65) 0.040 (1.02) 0.022 (0.56) 0.014 (0.36) 0.625 (15.87) 0.600 (15.24) 0° 15° TYP. 0.010 (0.25) NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 3926 FHD F03 12 X2804C ORDERING INFORMATION X2804C X X -X Access Time –90 = 90ns –15 = 150ns –20 = 200ns –25 = 250ns Device Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C Package P = 24-Lead Plastic DIP 13