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X9430
Dual Digitally Controlled Potentiometer (XDCP™) with Operational Amplifier
FEATURES
DESCRIPTION
•
•
•
•
The X9430 is a monolithic CMOS IC that incorporates
two operational amplifiers and two nonvolatile digitally
controlled potentiometers. The amplifiers are CMOS
differential input voltage operational amplifiers with
near rail-to-rail outputs. All pins for the two amplifiers
are brought out of the package to allow combining
them with the potentiometers or using them as complete stand-alone amplifiers.
Two CMOS voltage operational amplifiers
Two digitally controlled potentiometers
Can be combined or used separately
Amplifiers
—Low voltage operation
—V+/V- = ±2.7V to ±5.5V
—Rail-to-rail CMOS performance
—1MHz gain bandwidth product
• Digitally controlled potentiometer
—Dual 64 tap potentiometers
—Rtotal = 10k¾
—SPI serial interface
—VCC = 2.7V to 5.5V
The digitally controlled potentiometers consist of a
series string of 63 polycrystalline resistors that behave
as standard integrated circuit resistors. The SPI serial
port, common to both pots, allows the user to program
the connection of the wiper output to any of the resistor
nodes in the series string. The wiper position is saved
in the on board E2 memory to allow for nonvolatile restoration of the wiper position.
A wide variety of applications can be implemented
using the potentiometers and the amplifiers. A typical application is to implement the amplifier as a wiper buffer in
circuits that use the potentiometer as a voltage reference. The potentiometer can also be combined with
the amplifier yielding a digitally programmable gain
amplifier or programmable current source.
BLOCK DIAGRAM
VCC
RW0
RH0 RL0
V+
HOLD
VNI0
Control and
Memory
CS
SCK
SO
SI
A1
A0
+
VOUT0
–
WCR0
VINV0
VNI1
+
VOUT1
–
WCR1
VINV1
WP
REV 1.0 6/20/00
VSS
RW1
RL1 RH1
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V–
Characteristics subject to change without notice.
1 of 21
X9430 – Preliminary Information
PIN DESCRIPTIONS
Device Address (A0–A1)
Host Interface Pins
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked
out by the falling edge of the serial clock.
The address inputs are used to set the least significant
2 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9430. A maximum of 4 devices may occupy the
SPI serial bus.
Potentiometer Pins1
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the device are
input on this pin. Data is latched by the rising edge of
the serial clock.
RH (RH0–RH1), RL (RL0–RL1)
Serial Clock (SCK)
RW (RW0–RW1)
The SCK input is used to clock data into and out of the
X9430.
The wiper output is equivalent to the wiper output of a
mechanical potentiometer.
Chip Select (CS)
Amplifier and Device Pins
When CS is HIGH, the X9430 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9430, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
Hardware Write Protect Input WP
The WP pin when low prevents nonvolatile writes to
the wiper counter register.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK
is LOW. If the pause feature is not used, HOLD should
be held HIGH at all times.
The RH and RL inputs are equivalent to the terminal
connections on either end of a mechanical potentiometer.
Amplifier Input Voltage VNI(0,1) and VINV(0,1)
VNI and VINV are inputs to the noninverting (+) and
inverting (-) inputs of the operational amplifiers.
Amplifier Output Voltage VOUT(0,1)
VOUT is the voltage output pin of the operational amplifier.
Analog Supplies V+, VThe Analog Supplies V+, V- are the supply voltages for
the XDCP analog section and the operational amplifiers.
System Supply VCC and Ground VSS
The system supply VCC and its reference VSS is used
to bias the interface and control circuits.
1.
REV 1.0 6/20/00
Alternate designations for RH, RL, RW are VH, VL, VW
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Characteristics subject to change without notice.
2 of 21
X9430 – Preliminary Information
PIN CONFIGURATION
PIN NAMES
Symbol
SOIC
SCK
Serial Clock
SI
Serial Input
SO
Serial Output
VINV0
A0-A1
Device Address
A0
S0
CS
Chip Select
HOLD
Hold
RH0–RH1, RL0–RL1
Potentiometers (terminal
equivalent)
RW0–RW1
Potentiometers (wiper
equivalent)
VNI(0,1), VINV(0,1)
Amplifier Input Voltages
VOUT0, VOUT1
Amplifier Outputs
WP
Hardware Write Protection
V+,V-
Analog and Voltage Amplifier
Supplies
VCC
System/Digital Supply Voltage
VSS
System Ground
VCC
1
24
V+
RL0
RH0
2
3
23
22
VOUT0
VNI0
RW0
4
5
21
20
CS
WP
SI
A1
RL1
6
7
X9430
8
9
19
18
17
16
HOLD
SCK
VINV1
RH1
RW1
10
15
VNI1
11
14
VOUT1
VSS
12
13
V-
TSSOP
1
24
HOLD
2
3
23
22
VOUT0
4
5
21
20
SCK
VINV1
VNI1
V+
VCC
6
7
RL0
RH0
SO
A0
VINV0
VNI0
Description
VOUT1
19
18
V-
PRINCIPLES OF OPERATION
VSS
8
9
17
16
RW1
RH1
RW0
10
15
RL1
CS
11
14
A1
WP
12
13
SI
The X9430 is an integrated microcircuit incorporating two
digitally controlled potentiometers, two operational
amplifiers and their associated registers and counters;
and the serial interface logic providing direct communication between the host and the digitally controlled
potentiometers.
X9430
Serial Interface
The X9430 supports the SPI interface hardware conventions. The device is accessed via the SI input with
data clocked in on the rising edge of SCK. CS must be
LOW and the HOLD and WP pins must be HIGH during the entire operation.
REV 1.0 6/20/00
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Characteristics subject to change without notice.
3 of 21
X9430 – Preliminary Information
Potentiometer/Array Description
The X9430 is comprised of two resistor arrays and two
operational amplifiers. Each array contains 63 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (RH and RL).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(RW) output. Within each individual array only one
switch may be turned on at a time. These switches are
controlled by a volatile wiper counter register (WCR).
The six bits of the WCR are decoded to select, and
enable, one of sixty-four switches.
The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
data registers into the WCR. These data registers and
the WCR can be read and written by the host system.
Operational Amplifier
The voltage operational amplifiers are CMOS rail-to-rail
output general purpose amplifiers. They are designed
to operate from dual (±) power supplies. The amplifiers
may be configured like any standard amplifier. All pins
are externally available to allow connection with the
potentiometers or as stand alone amplifiers.
VH (0,1)
HOLD
VCC
(DR0-DR3)0,1
WCR0,1
VL (0,1)
CS
Control and
Memory
SCK
VW (0,1)
VINV (0,1)
WCR0
SO
SI
VN (0,1)
A1
WCR1
A0
+
(DR0-DR3)0,1
WP
VOUT (0,1)
–
VSS
Detailed Block Diagram
(One of 2 Circuits)
Write in Process
INSTRUCTIONS AND PROGRAMMING
The contents of the data registers are saved to nonvolatile memory when the CS pin goes from LOW to
HIGH after a complete write sequence is received by
the device. The progress of this internal write operation can be monitored by a write in process bit (WIP).
The WIP bit is read with a read status command.
REV 1.0 6/20/00
Identification (ID) Byte
The first byte sent to the X9430 from the host, following a CS going HIGH to LOW, is called the identification byte. The most significant four bits of the slave
address are a device type identifier, for the X9430 this
is fixed as 0101[B] (refer to Figure 1).
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Characteristics subject to change without notice.
4 of 21
X9430 – Preliminary Information
The two least significant bits in the ID byte select one of
four devices on the bus. The physical device address is
defined by the state of the A0-A1 input pins. The X9430
compares the serial data stream with the address input
state; a successful compare of both address bits is
required for the X9430 to successfully continue the
command sequence. The A0–A1 inputs can be actively
driven by CMOS input signals or tied to VCC or VSS.
The remaining two bits in the slave byte must be set to 0.
Figure 1. Identification Byte Format
Device Type
Identifier
The basic sequence of the two byte instructions is illustrated in Figure 3. These two-byte instructions
exchange data between a wiper counter register and
one of the four data registers associated with each. A
transfer from a data register to a wiper counter register
is essentially a write to a static RAM. The response of
the wiper to this action will be delayed tWRL. A transfer
from the wiper counter register (current wiper position)
to a data register is a write to nonvolatile memory and
takes a minimum of tWR to complete. The transfer can
occur between one of the two potentiometers and one
of its associated registers; or it may occur globally,
wherein the transfer occurs between both of the potentiometers and one of their associated registers.
The next byte sent to the X9430 contains the instruction and register pointer information. The four most significant bits are the instruction. The next four bits point
to one of the WCRs of the two pots, and when applicable, they point to one of four associated data registers.
The format is shown below in Figure 2.
Five instructions require a three-byte sequence to complete. These instructions transfer data between the
host and the X9430; either between the host and one
of the data registers or directly between the host and
the Wiper Counter and Registers. These instructions
are: 1) Read Wiper Counter Register, read the current
wiper position of the selected pot 2) Write Wiper
Counter Register, i.e. change current wiper position of
the selected pot; 3) Read Data Register, read the contents of the selected nonvolatile register; 4) Write Data
Register, write a new value to the selected data register;
5)Read Status, returns the contents of the WIP bit which
indicates if an internal write cycle is in progress.
Figure 2. Instruction Byte Format
The sequence of these operations is shown in Figure 4
and Figure 5.
0
1
0
1
0
0
A1
A0
Device Address
Instruction Byte
Register
Select
I3
I2
I1
Instructions
I0
R1
R0
0
P0
WCR Select
The four high order bits of the instruction byte specify
the operation. The next two bits (R1 and R0) select one
of the four registers that is to be acted upon when a
register oriented instruction is issued. The last bit (P0)
selects which one of the two potentiometers is to be
affected by the instruction.
The final command is Increment/Decrement. It is different from the other commands, because it’s length is
indeterminate. Once the command is issued, the master can clock the selected wiper up and/or down in one
resistor segment steps; thereby, providing a fine tuning
capability to the host. For each SCK clock pulse (tHIGH)
while SI is HIGH, the selected wiper will move one
resistor segment towards the VH terminal. Similarly, for
each SCK clock pulse while SI is LOW, the selected
wiper will move one resistor segment towards the VL
terminal. A detailed illustration of the sequence and
timing for this operation are shown in Figure 6 and
Figure 7.
Four of the ten instructions are two bytes in length and
end with the transmission of the instruction byte.
REV 1.0 6/20/00
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Characteristics subject to change without notice.
5 of 21
X9430 – Preliminary Information
Figure 3. Two Byte Command Sequence
CS
SCK
SI
0
1
0
1
0
0
A1
A0
I3
I2
I1
I0
R1 R0
0
P0
Figure 4. Three-Byte Command Sequence (Write)
CS
SCK
SI
0
1
0
0
1
0
A1 A0
I3
I2
I1 I0
R1 R0 0
P0
0
0
D5 D4 D3 D2 D1 D0
Figure 5. Three-Byte Command Sequence(Read)
CS
SCK
SI
Don’t Care
0
1
0
0
1
0
A1 A0
I3
I2
I1 I0
R1 R0 0
P0
S0
0
0
D5 D4 D3 D2 D1 D0
Figure 6. Increment/Decrement Command Sequence
CS
SCK
SI
0
REV 1.0 6/20/00
1
0
1
0
0
A1
A0
I3
I2
I1
I0
0
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0
0
P0
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
Characteristics subject to change without notice.
6 of 21
X9430 – Preliminary Information
Figure 7. Increment/Decrement Timing
tWRID
SCK
SI
VOUT
VW
INC/DEC CMD Issued
REGISTER OPERATION
Both digitally controlled potentiometers share the serial
interface and share a common architecture. Each
potentiometer is associated with a wiper counter register (WCR), and four data registers. Figure 8 illustrates
the control, registers, and system features of the
device.
Figure 8. System Block Diagram
VH (0,1)
HOLD VCC
CS
SCK
SO
SI
A1
A0
(DR0-DR3)0,1 WCR0,1
VL (0,1)
Control and
Memory
WCR0
VW (0,1)
VINV (0,1)
VN (0,1)
WCR1
WP
+
–
VSS
VOUT (0,1)
Detailed Block Diagram
Wiper Counter (WCR) and Analog Control
Registers (ACR)
The X9430 contains two wiper counter registers, one
for each XDCP. The wiper counter register is equivalent
to a serial-in, parallel-out counter with its outputs
decoded to select one of sixty-four switches along its
REV 1.0 6/20/00
resistor array. The contents of the wiper counter register
can be altered in four ways: it may be written directly by
the host via the write WCR instruction (serial load); it
may be written indirectly by transferring the contents of
one of four associated data registers (DR) via the XFR
data register instruction (parallel load); it can be modified one step at a time by the increment/decrement
instruction (WCR only). Finally, it may be loaded with
the contents of its associated data register zero (R0)
upon power-up.
The wiper counter register is a volatile register; that is,
its contents are lost when the X9430 is powered-down.
Although the registers are automatically loaded with
the value in R0 upon power-up, it should be noted this
may be different from the value present at power-down.
Data Registers (DR)
Each potentiometer has four nonvolatile data registers
(DR). These can be read or written directly by the host
and data can be transferred between any of the four
data registers and the WCR. It should be noted all
operations changing data in one of these registers is a
nonvolatile operation and will take a maximum of 10ms.
If the application does not require storage of multiple settings for the potentiometer, these registers can be used
as regular memory locations that could store system
parameters or user preference data.
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Characteristics subject to change without notice.
7 of 21
X9430 – Preliminary Information
REGISTER DESCRIPTIONS AND MEMORY MAP
Wiper Counter Register (WCR)
0
Memory Map
0
WP5 WP4 WP3 WP2 WP1
(volatile)
WCRO
WCR1
DR0
DR0
DR1
DR1
Data Registers (DR, R0-R3)
DR2
DR2
Wiper Position or User Data
DR3
DR3
(Nonvolatile)
WP0
(LSB)
WP0-WP5 identify wiper position.
Instruction Format
Notes: (1)
(2)
(3)
(4)
“A1 ~ A0”: stands for the device addresses sent by the master.
WPx refers to wiper position data in the Wiper Counter Register
“I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
“D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
Read Wiper Counter Register (WCR)
Read the contents of the Wiper Counter Register pointed to by P1-P0
device type
identifier
device
addresses
instruction
opcode
CS
Falling
Edge 0 1 0 1 0 0 A A 1
1 0
0
0
1
WCR
addresses
0
0
wiper position
(sent by X9430 on SO)
CS
W W W W W W Rising
P
0
0 0 P P P P P P Edge
0
5 4 3 2 1 0
Write Wiper Counter Register (WCR)
Write new value to the Wiper Counter Register pointed to by P1-P0
device type
device
instruction
identifier
addresses
opcode
CS
Falling
Edge 0 1 0 1 0 0 A A 1 0 1 0
1 0
WCR
addresses
0
0
Data Byte
(sent by Host on SI)
CS
Rising
W W W W W W
P
0
0 0 P P P P P P Edge
0
5 4 3 2 1 0
Read Data Register (DR)
Read the contents of the Register pointed to by P1-P0 and R1-R0
device type
device
instruction
DR/WCR
Data Byte
identifier
addresses
opcode
addresses
(sent by X9430 on SO)
CS
CS
Falling
Rising
W W W W W W
Edge 0 1 0 1 0 0 A A 1 0 1 1 R R 0 P 0 0 P P P P P P Edge
1 0
1 0
0
5 4 3 2 1 0
Write Data Register (DR)
Write new value to the Register pointed to by P1-P0 and R1-R0
device type
device
instruction
DR/WCR
identifier
addresses
opcode
addresses
CS
Falling
Edge 0 1 0 1 0 0 A A 1 1 0 0 R R 0 P
1 0
1 0
0
REV 1.0 6/20/00
Data Byte
(sent by host on SI)
CS
Rising
W W W W W W
0 0 P P P P P P Edge
5 4 3 2 1 0
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HIGH-VOLTAGE
WRITE CYCLE
Characteristics subject to change without notice.
8 of 21
X9430 – Preliminary Information
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Transfer the contents of the Register pointed to by R1-R0 to the WCR
device type
device
instruction
DR/WCR
CS
CS
identifier
addresses
opcode
addresses
Falling
Rising
Edge 0 1 0 1 0 0 A A 1 1 0 1 R R 0 P Edge
1 0
1 0
0
Transfer Wiper Counter Register (WCR) to Data Register (DR)
Transfer the contents of the WCR to the Register pointed to by R1-R0
device type
device
instruction
DR/WCR
CS
CS
identifier
addresses
opcode
addresses
HIGH-VOLTAGE
Falling
Rising
WRITE CYCLE
Edge 0 1 0 1 0 0 A A 1 1 1 0 R R 0 P Edge
1 0
1 0
0
P0: 0-WCR0, 1-WCR1
Increment/Decrement Wiper Counter Register (WCR)
Enable Increment/decrement of the WCR pointed to by P1-P0
device type
device
instruction
WCR
increment/decrement
CS
CS
identifier
addresses
opcode
addresses (sent by master on SDA)
Falling
Rising
Edge 0 1 0 1 0 0 A A 0 0 1 0 X X 0 P I/ I/ . . . . I/ I/ Edge
1 0
0 D D
D D
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
Transfer the contents of all four Data Registers pointed to by R1-R0 to their respective WCR
device type
device
instruction
DR
CS
CS
identifier
addresses
opcode
addresses
Falling
Rising
Edge 0 1 0 1 0 0 A A 0 0 0 1 R R 0 0 Edge
1 0
1 0
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
Transfer the contents of all WCRs to their respective data Registers pointed to by R1-R0
device type
device
instruction
DR
CS
CS
identifier
addresses
opcode
addresses
Falling
Rising
Edge 0 1 0 1 0 0 A A 1 0 0 0 R R 0 0 Edge
1 0
1 0
HIGH-VOLTAGE
WRITE CYCLE
Read Status
Returns the contents of the WIP bit which indicates if an internal write cycle is in progress
device type
device
instruction
wiper
Data Byte
identifier
addresses
opcode
addresses
(sent by X9430 on SO)
CS
CS
Falling
Rising
W
Edge 0 1 0 1 0 0 A A 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 I Edge
1 0
P
REV 1.0 6/20/00
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Characteristics subject to change without notice.
9 of 21
X9430 – Preliminary Information
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ....................–65°C to +135°C
Storage temperature .........................–65°C to +150°C
Voltage on SCK, SCL or any
address input with respect to VSS ...........–1V to +7V
Voltage on V+ (referenced to VSS) ........................ +7V
Voltage on V- (referenced to VSS) .......................... -7V
(V+) – (V-).............................................................. 10V
Any VH .................................................................... V+
Any VL ...................................................................... VLead temperature (soldering, 10 seconds)........ 300°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification)
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Min.
0°C
Max.
+70°C
Device
X9430
Supply Voltage (VCC) Limits
5V ±10%
Industrial
–40°C
+85°C
X9430-2.7
2.7V to 5.5V
POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
RTOTAL
Parameter
Min.
End to end resistance
Typ. Max.
–20
Power rating
IW
Wiper current
RW
Wiper resistance
Vv+
VvVTERM
Voltage on V+ pin
Voltage on V- pin
–3
%
50
mW
+3
mA
¾
V+ = 5V, V- = -5V, IW = 3mA
100
250
¾
V+ = 2.7V, V- = -2.7V, IW = 1mA
V
X9430-2.7
+2.7
+5.5
X9430
-5.5
-4.5
X9430-2.7
-5.5
-2.7
V-
V+
Absolute linearity (1)
linearity (2)
Temperature coefficient of RTOTAL
Ratiometric temperature coefficient
25°C, each pot
100
+5.5
Resolution (4)
Test Conditions
40
+4.5
Noise
Relative
+20
X9430
Voltage on any RH or RL pin
Unit
V
V
-100
dBv
1.6
%
–1
–0.2
Ref: 1V
+1
MI(3)
Vw(n)(actual)–Vw(n)(expected)
+0.2
MI(3)
Vw(n + 1)–[Vw(n) + MI]
±300
ppm/°C
±20
ppm/°C
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used
as a potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (RH–RL)/63, single pot (=LSB)
(4) Individual array resolutions
REV 1.0 6/20/00
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Characteristics subject to change without notice.
10 of 21
X9430 – Preliminary Information
AMPLIFIER ELECTRICAL CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified.)
Industrial
Symbol
VOS
TCVOS
IB
Parameter
Condition
Min.
Commercial
Typ. Max. Min. Typ. Max.
Unit
Input Offset Voltage
V+/V- ±3V to ±5V
1
Input Offset Voltage Temp.
Coefficient
V+/V- ±3V to ±5V
-10
-10
µV/°C
Input bias current
V+/V- ±3V to ±5V
50
50
pA
25
pA
3
1
2
mV
Input offset current
V+/V- ±3V to ±5V
CMRR
Common mode
rejection ratio
VCM = -1V to +1V
70
70
dB
PSRR
Power supply
rejection ratio
V+/V- ±3V to ±5V
70
70
dB
Input common mode
voltage range
Tj = 25°C
V-
AV
Large signal voltage gain
VO = -1V to + 1V
30
VO
Output voltage swing
VV+
IOS
VCM
25
V+
50
V30
+0.1
V+
V
50
V/mV
+0.1
-.15
V
V
-.15
IO
Output current
V+/V- = ±5.5V
V+/V- = ±3.3V
IS
Supply current
V+/V- = ±5.0V
3
3
mA
V+/V- = ±3.0V
1.5
1.5
mA
50
30
50
30
mA
mA
GB
Gain-bandwidth prod
RL = 100k, CL = 50pf
1.0
1.0
MHz
SR
Slew rate
RL = 100k, CL = 50pf
1.5
1.5
V/µsec
ΦM
Phase margin
RL = 100k,
CL = 50pf
80
80
Deg.
V+ and V- (±5V to ±3V) are the amplifier power supplies. The amplifiers are specified with dual power supplies.
VCC and VSS are the logic supplies. All ratings are over the temperature range for the Industrial (-40 to + 85°C) and
Commercial (0 to 70°C) versions of the part unless specified differently.
REV 1.0 6/20/00
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Characteristics subject to change without notice.
11 of 21
X9430 – Preliminary Information
POTENTIOMETER D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
400
µA
fSCK = 2MHz, SO = Open,
Other Inputs = VSS
ICC1
VCC supply current (active)
ICC2
VCC supply current (nonvolatile
write)
1
mA
fSCK = 2MHz, SO = Open,
Other Inputs = VSS
ISB
VCC current (standby)
1
µA
SCK = SI = VSS, Addr. = VSS
ILI
Input leakage current
10
µA
VIN = VSS to VCC
ILO
Output leakage current
10
µA
VOUT = VSS to VCC
VIH
Input HIGH voltage
VCC x 0.7
VCC + 0.5
V
VIL
Input LOW voltage
–0.5
VCC x 0.1
V
VOL
Output LOW voltage
0.4
V
IOL = 3mA
ENDURANCE AND DATA RETENTION
Parameter
Min.
Unit
Minimum endurance
100,000
Data changes per register
Data retention
100
years
CAPACITANCE
Symbol
COUT
CIN
(5)
(5)
CL | CH | CW
Test
Typ.
Max.
Unit
Test Conditions
Output capacitance (SO)
8
pF
VOUT = 0V
Input capacitance (A0, A1, SI, WP, HOLD and SCK)
6
pF
VIN = 0V
Potentiometer capacitance
10/10/
pF
POWER-UP TIMING
Symbol
tPUR
(6)
(6)
tPUW
Parameter
Max.
Unit
Power-up to initiation of read operation
1
ms
Power-up to initiation of write operation
5
ms
A.C. TEST CONDITIONS
(7) The power-up order of power supplies are VCC, V+
and V-.
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x 0.5
SPICE Macro Model
RTOTAL
Notes: (5) This parameter is periodically sampled and not 100%
tested.
(6) tPUR and tPUW are the delays required from the time the
third (last) power supply (VCC, V+ or V-) is stable until
the specific instruction can be issued. These parameters
are
periodically sampled and not 100% tested.
REV 1.0 6/20/00
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RH
CW
CH
CL
RL
RW
Characteristics subject to change without notice.
12 of 21
X9430 – Preliminary Information
AC TIMING
Symbol
Parameter
Min.
Max.
Unit
2.0
MHz
fSCK
SSI/SPI clock frequency
tCYC
SSI/SPI clock cycle time
500
ns
tWH
SSI/SPI clock high time
200
ns
tWL
SSI/SPI clock low time
200
ns
tLEAD
Lead time
250
ns
tLAG
Lag time
250
ns
tSU
SI, SCK, HOLD and CS input setup time
50
ns
tH
SI, SCK, HOLD and CS input hold time
50
ns
tRI
SI, SCK, HOLD and CS input rise time
2
µs
tFI
SI, SCK, HOLD and CS input fall time
2
µs
500
ns
200
ns
tDIS
SO output disable time
0
tV
SO output valid time
tHO
SO output hold time
tRO
SO output rise time
50
ns
tFO
SO output fall time
50
ns
0
ns
tHOLD
HOLD time
400
ns
tHSU
HOLD setup time
100
ns
tHH
HOLD hold time
100
ns
tHZ
HOLD low to output in high Z
100
ns
tLZ
HOLD high to output in low Z
100
ns
TI
Noise suppression time constant at SI, SCK, HOLD and CS inputs
tCS
20
ns
CS deselect time
2
µs
tWPASU
WP, A0 and A1 setup time
0
ns
tWPAH
WP, A0 and A1 hold time
0
ns
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
tWR
Parameter
High-voltage write cycle time (store instructions)
Typ.
Max.
Unit
5
10
ms
Typ.
Max.
Unit
.2
50
V/ms
VCC RAMP (sample tested)
Symbol
trVCC
REV 1.0 6/20/00
Parameter
VCC power—up rate
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Characteristics subject to change without notice.
13 of 21
X9430 – Preliminary Information
DCP Timing
Symbol
tWRPO
Parameter
Min. Max. Unit
Wiper response time after the third (last) power supply is stable
10
µs
tWRL
Wiper response time after instruction issued (all load instructions)
10
µs
tWRID
Wiper response time from an active SCL/SCK edge (increment/decrement instruction)
10
µs
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
TIMING DIAGRAMS
Input Timing
tCS
CS
SCK
...
tSU
SI
SO
REV 1.0 6/20/00
tLAG
tCYC
tLEAD
tH
MSB
tWL
tWH
...
tRI
tFI
LSB
High Impedance
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Characteristics subject to change without notice.
14 of 21
X9430 – Preliminary Information
Output Timing
CS
SCK
...
tV
tDIS
...
MSB
SO
SI
tHO
LSB
ADDR
Hold Timing
CS
tHSU
tHH
SCK
...
tRO
tFO
SO
tHZ
tLZ
SI
tHOLD
HOLD
DCP Timing (for All Load Instructions)
CS
SCK
...
tWRL
MSB
SI
...
LSB
VWx
SO
High Impedance
REV 1.0 6/20/00
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Characteristics subject to change without notice.
15 of 21
X9430 – Preliminary Information
DCP Timing (for Increment/Decrement Instruction)
CS
SCK
...
tWRID
...
VWx
SI
SO
ADDR
Inc/Dec
Inc/Dec
...
High Impedance
Write Protect and Device Address Pins Timing
(Any Instruction)
CS
tWPASU
tWPAH
WP
A0
A1
REV 1.0 6/20/00
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Characteristics subject to change without notice.
16 of 21
X9430 – Preliminary Information
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+VR
VR
VW
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Application Circuits
Noninverting Amplifier
VS
Voltage Regulator
+
VO
–
VIN
VO (REG)
317
R1
R2
Iadj
R1
R2
VO = (1+R2/R1)VS
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
Offset Voltage Adjustment
R1
Comparator with Hysterisis
R2
VS
VS
–
+
VO
100KΩ
–
VO
+
}
}
TL072
R1
R2
10KΩ
10KΩ
+12V
REV 1.0 6/20/00
10KΩ
VUL = {R1/(R1+R2)} VO(max)
VLL = {R1/(R1+R2)} VO(min)
-12V
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Characteristics subject to change without notice.
17 of 21
X9430 – Preliminary Information
Application Circuits (continued)
Attenuator
Filter
C
VS
+
R2
R1
VS
R
VO
+
VO
–
–
R3
R4
R2
All RS = 10kΩ
R1
GO = 1 + R2/R1
fc = 1/(2pRC)
VO = G VS
-1/2 ð G ð +1/2
R1
R2
}
}
Inverting Amplifier
Equivalent L-R Circuit
VS
R2
C1
–
VS
VO
+
+
–
R1
ZIN
VO = G VS
G = - R2/R1
R3
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
Function Generator
C
R2
–
+
R1
–
} RA
+
} RB
frequency µ R1, R2, C
amplitude µ RA, RB
REV 1.0 6/20/00
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Characteristics subject to change without notice.
18 of 21
X9430 – Preliminary Information
PACKAGING INFORMATION
24-Lead Plastic Small Outline Gull Wing Package Type S
0.290 (7.37) 0.393 (10.00)
0.299 (7.60) 0.420 (10.65)
Pin 1 Index
Pin 1
0.014 (0.35)
0.020 (0.50)
0.598 (15.20)
0.610 (15.49)
(4X) 7°
0.092 (2.35)
0.105 (2.65)
0.003 (0.10)
0.012 (0.30)
0.050 (1.27)
0.050" Typical
0.010 (0.25)
X 45°
0.020 (0.50)
0.050"
Typical
0° – 8°
0.009 (0.22)
0.013 (0.33)
0.420"
0.015 (0.40)
0.050 (1.27)
FOOTPRINT
0.030" Typical
24 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
REV 1.0 6/20/00
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Characteristics subject to change without notice.
19 of 21
X9430 – Preliminary Information
PACKAGING INFORMATION
24-Lead Plastic, TSSOP Package Type V
.026 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.303 (7.70)
.311 (7.90)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.06)
.005 (.15)
.010 (.25)
Gage Plane
0°–8°
(4.16) (7.72)
Seating Plane
.020 (.50)
.030 (.75)
(1.78)
Detail A (20X)
(0.42)
(0.65)
.031 (.80)
.041 (1.05)
ALL MEASUREMENTS ARE TYPICAL
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
REV 1.0 6/20/00
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Characteristics subject to change without notice.
20 of 21
X9430 – Preliminary Information
Ordering Information
X9430
Y
P
T
V
VCC Limits
Blank = 5V ±10%
–2.7 = 2.7 to 5.5V
Device
Temperature Range
Blank = Commercial = 0 to +70°C
I = Industrial = –40 to +85°C
Package
S24 = 24-Lead SOIC
V24 = 24-Lead TSSOP
Potentiometer Organization
Pot 0 Pot 1
W=
10K¾ 10K¾
LIMITED WARRANTY
©Xicor, Inc. 2000 Patents Pending
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
REV 1.0 6/20/00
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Characteristics subject to change without notice.
21 of 21