XILINX XCR5064C

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APPLICATION NOTE
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XCR5064C: 64 Macrocell CPLD with
Enhanced Clocking
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DS044 (v1.1) February 10, 2000
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Features
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Industry's first TotalCMOS™ PLD - both CMOS design
and process technologies
Fast Zero Power (FZP™) design technique provides
ultra-low power and very high speed
High speed pin-to-pin delays of 7.5 ns
Ultra-low static power of less than 100 µA
100% routable with 100% utilization while all pins and
all macrocells are fixed
Deterministic timing model that is extremely simple to
use
Up to 12 clocks with programmable polarity at every
macrocell
5V, In-System Programmable (ISP) using a JTAG
interface
- On-chip supervoltage generation
- ISP commands include: Enable, Erase, Program,
Verify
- Supported by multiple ISP programming platforms
- Four pin JTAG interface (TCK, TMS, TDI, TDO)
- JTAG commands include: Bypass, Idcode
Support for complex asynchronous clocking
Innovative XPLA™ architecture combines high speed
with extreme flexibility
1000 erase/program cycles guaranteed
20 years data retention guaranteed
Logic expandable to 37 product terms
PCI compliant
Advanced 0.5µ E2CMOS process
Security bit prevents unauthorized access
Design entry and verification using industry standard
and Xilinx CAE tools
Reprogrammable using industry standard device
programmers
Innovative Control Term structure provides either sum
terms or product terms in each logic block for:
- Programmable 3-state buffer
- Asynchronous macrocell register preset/reset
- Up to two asynchronous clocks
Programmable global 3-state pin facilitates "bed of
nails" testing without using logic resources
Available in PLCC and VQFP packages
Available in both Commercial and Industrial grades
Description
The XCR5064C CPLD (Complex Programmable Logic
Device) is the second in a family of CoolRunner™ CPLDs
from Xilinx Semiconductors. These devices combine high
DS044 (v1.1) February 10, 2000
Product Specification
speed and zero power in a 64 macrocell CPLD. With the
FZP design technique, the XCR5064C offers true pin-to-pin
speeds of 7.5 ns, while simultaneously delivering power
that is less than 100 µA at standby without the need for
`turbo bits' or other power down schemes. By replacing
conventional sense amplifier methods for implementing
product terms (a technique that has been used in PLDs
since the bipolar era) with a cascaded chain of pure CMOS
gates, the dynamic power is also substantially lower than
any competing CPLDz. These devices are the first TotalCMOS PLDs, as they use both a CMOS process technology
and the patented full CMOS FZP design technique.
The Xilinx FZP CPLDs utilize the patented XPLA
(eXtended Programmable Logic Array) architecture. The
XPLA architecture combines the best features of both PLA
and PAL type structures to deliver high speed and flexible
logic allocation that results in superior ability to make
design changes with fixed pinouts. The XPLA structure in
each logic block provides a fast 7.5 ns PAL path with five
dedicated product terms per output. This PAL path is joined
by an additional PLA structure that deploys a pool of 32
product terms to a fully programmable OR array that can
allocate the PLA product terms to any output in the logic
block. This combination allows logic to be allocated efficiently throughout the logic block and supports as many as
37 product terms on an output. The speed with which logic
is allocated from the PLA array to an output is only 2.0 ns,
regardless of the number of PLA product terms used, which
results in worst case tPD's of only 9.5 ns from any pin to any
other pin. In addition, logic that is common to multiple outputs can be placed on a single PLA product term and
shared across multiple outputs via the OR array, effectively
increasing design density.
The XCR5084C CPLDs are supported by industry standard CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor,
Synopsys, Synario, Viewlogic, and Synplicity), using text
(ABEL, VHDL, Verilog) and/or schematic entry. Design verification uses industry standard simulators for functional
and timing simulation. Development is supported on personal computer, Sparc, and HP platforms. Device fitting
uses Xilinx developed tools including WebFITTER.
The XCR5064C CPLD is reprogrammable using industry
standard device programmers from vendors such as Data
I/O, BPMicrosystems, SMS, and others. The XCR5064C
also includes an industry-standard, IEEE 1149.1, JTAG
interface through which In-System Programming (ISP) and
reprogramming of the device are supported.
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XCR5064C: 64 Macrocell CPLD with Enhanced Clocking
XPLA Architecture
Figure 1 shows a high level block diagram of a 64 macrocell
device implementing the XPLA architecture. The XPLA
architecture consists of logic blocks that are interconnected
by a Zero-power Interconnect Array (ZIA). The ZIA is a virtual crosspoint switch. Each logic block is essentially a
36V16 device with 36 inputs from the ZIA and 16 macrocells. Each logic block also provides 32 ZIA feedback paths
from the macrocells and I/O pins.
From this point of view, this architecture looks like many
other CPLD architectures. What makes the CoolRunner
family unique is what is inside each logic block and the
design technique used to implement these logic blocks.
The contents of the logic block will be described next.
Logic Block Architecture
Figure 2 illustrates the logic block architecture. Each logic
block contains control terms, a PAL array, a PLA array, and
16 macrocells. The 6 control terms can individually be configured as either SUM or PRODUCT terms, and are used to
control the preset/reset and output enables of the 16 macrocells’ flip-flops. In addition, two of the control terms can
be used as clock signals (see Macrocell Architecture Section for details). The PAL array consists of a programmable
AND array with a fixed OR array, while the PLA array consists of a programmable AND array with a programmable
OR array. The PAL array provides a high speed path
through the array, while the PLA array provides increased
product term density.
Each macrocell has five dedicated product terms from the
PAL array. The pin-to-pin tPD of the XCR5064C device
through the PAL array is 7.5 ns. If a macrocell needs more
than five product terms, it simply gets the additional product
terms from the PLA array. The PLA array consists of 32
product terms, which are available for use by all 16 macrocells. The additional propagation delay incurred by a macrocell using one or all 32 PLA product terms is just 2.0 ns.
So the total pin-to-pin tPD for the XCR5064C using six to 37
product terms is 9.5 ns (7.5 ns for the PAL + 2.0 ns for the
PLA)..
MC0
MC1
I/O
MC0
LOGIC
BLOCK
36
36
16
16
LOGIC
BLOCK
MC15
MC1
I/O
MC15
16
16
ZIA
MC0
MC1
I/O
MC0
LOGIC
BLOCK
36
36
16
16
16
16
MC15
LOGIC
BLOCK
MC1
I/O
MC15
SP00439
Figure 1: Xilinx XPLA CPLD Architecture
DS044 (v1.1) February 10, 2000
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XCR5064C: 64 Macrocell CPLD with Enhanced Clocking
36 ZIA INPUTS
6
CONTROL
TO 16 MACROCELLS
5
PAL
ARRAY
PLA
ARRAY
(32)
SP00435A
Figure 2: Xilinx XPLA Logic Block Architecture
3
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XCR5064C: 64 Macrocell CPLD with Enhanced Clocking
Macrocell Architecture
Figure 3 shows the architecture of the macrocell used in
the CoolRunner XCR5064C. The macrocell can be configured as either a D- or T- type flip-flop or a combinatorial
logic function. A D-type flip-flop is generally more useful for
implementing state machines and data buffering while a
T-type flip-flop is generally more useful in implementing
counters. Each of these flip-flops can be clocked from any
one of six sources. Four of the clock sources (CLK0, CLK1,
CLK2, CLK3) are connected to low-skew, device-wide clock
networks designed to preserve the integrity of the clock signal by reducing skew between rising and falling edges.
Clock 0 (CLK0) is designated as a “synchronous” clock and
must be driven by an external source. Clock 1 (CLK1),
Clock 2 (CLK2), and Clock 3 (CLK3) can be used as “synchronous” clocks that are driven by an external source, or
as “asynchronous” clocks that are driven by a macrocell
equation. CLK0, CLK1, CLK2 and CLK3 can clock the macrocell flip-flops on either the rising edge or the falling edge
of the clock signal. The other clock sources are two of the
six control terms (CT2 and CT3) provided in each logic
block. These clocks can be individually configured as either
a PRODUCT term or SUM term equation created from the
36 signals available inside the logic block. The timing for
asynchronous and control term clocks is different in that the
TCO time is extended by the amount of time that it takes for
the signal to propagate through the array and reach the
clock network, and the TSU time is reduced.
The six control terms of each logic block are used to control
the asynchronous Preset/Reset of the flip-flops and the
enable/disable of the output buffers in each macrocell. Control terms CT0 and CT1 are used to control the asynchro-
nous Preset/Reset of the macrocell's flip-flop. Note that the
Power-on Reset leaves all macrocells in the “zero” state
when power is properly applied, and that the Preset/Reset
feature for each macrocell can also be disabled. Control
terms CT2 and CT3 can be used as a clock signal to the
flip-flops of the macrocells, and as the Output Enable of the
macrocell's output buffer. Control terms CT4 and CT5 can
be used to control the Output Enable of the macrocell's output buffer. Having four dedicated Output Enable control
terms ensures that the CoolRunner devices are PCI compliant. The output buffers can also be always enabled or
always disabled. All CoolRunner devices also provide a
Global 3-State (GTS) pin, which, when enabled and pulled
Low, will 3-state all the outputs of the device. This pin is
provided to support “In-Circuit Testing” or “Bed-of-Nails
Testing”.
There are two feedback paths to the ZIA: one from the macrocell, and one from the I/O pin. The ZIA feedback path
before the output buffer is the macrocell feedback path,
while the ZIA feedback path after the output buffer is the I/O
pin feedback path. When the macrocell is used as an output, the output buffer is enabled, and the macrocell feedback path can be used to feedback the logic implemented
in the macrocell. When the I/O pin is used as an input, the
output buffer will be 3-stated and the input signal will be fed
into the ZIA via the I/O feedback path, and the logic implemented in the buried macrocell can be fed back to the ZIA
via the macrocell feedback path. It should be noted that
unused inputs or I/Os should be properly terminated (see
the section on Terminations in this data sheet and the application note Terminating Unused CoolRunner I/O Pins).
TO ZIA
PAL
PLA
D/T
CLK0
Q
INIT
(P or R)
GTS
CLK0
GND
CT0
CLK1
CLK1
CT4
CT5
V CC
GND
CT2
CT3
GND
SP00551
Figure 3: XCR5064C Macrocell Architecture
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XCR5064C: 64 Macrocell CPLD with Enhanced Clocking
Simple Timing Model
tPD = 7.5 ns, the tSU_PAL = 4 ns, and the tCO = 5.5 ns. If an
output is using six to 37 product terms, an additional 2ns
must be added to the tPD and tSU timing parameters to
account for the time to propagate through the PLA array.
Figure 4 shows the CoolRunner Timing Model. The CoolRunner timing model looks very much like a 22V10 timing
model in that there are three main timing parameters,
including tPD, tSU, and tCO. In other architectures, the user
may be able to fit the design into the CPLD, but is not sure
whether system timing requirements can be met until after
the design has been fit into the device. This is because the
timing models of competing architectures are very complex
and include such things as timing dependencies on the
number of parallel expanders borrowed, sharable expanders, varying number of X and Y routing channels used, etc.
In the XPLA architecture, the user knows up front whether
the design will meet system timing requirements. This is
due to the simplicity of the timing model. For example, in
the XCR5064C device, the user knows up front that if a
given output uses five product terms or less, the
TotalCMOS Design Technique for Fast Zero
Power
Xilinx is the first to offer a TotalCMOS CPLD, both in process technology and design technique. Xilinx employs a
cascade of CMOS gates to implement its Sum of Products
instead of the traditional sense amp approach. This CMOS
gate implementation allows Xilinx to offer CPLDs which are
both high performance and low power, breaking the paradigm that to have low power, you must have low performance. Refer to Figure 5 and Table 1 showing the ICC vs.
Frequency of our XCR5064C TotalCMOS CPL .
tPD_PAL = COMBINATORIAL PAL ONLY
tPD_PLA = COMBINATORIAL PAL + PLA
INPUT PIN
REGISTERED
tSU_PAL = PAL ONLY
tSU_PLA = PAL + PLA
INPUT PIN
D
Q
OUTPUT PIN
REGISTERED
tCO
OUTPUT PIN
GLOBAL CLOCK PIN
SP00441
Figure 4: CoolRunner Timing Model
100
TYPICAL
80
60
ICC
(mA)
40
20
0
0
20
40
60
80
100
120
140
160
180
200
FREQUENCY (MHz)
SP00663
Figure 5: ICC vs. Frequency at VCC = 5V, 25°C
Table 1: ICC vs. Frequency (VCC = 5.0V, 25°C)
Frequency (MHz)
Typical ICC (mA)
5
0
0.1
1
0.5
20
8.6
40
17.1
60
25.6
80
33.9
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100
42.2
120
50.3
140
58.3
160
66.4
180
74.7
200
82.7
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XCR5064C: 64 Macrocell CPLD with Enhanced Clocking
JTAG Testing Capability
JTAG is the commonly-used acronym for the Boundary
Scan Test (BST) feature defined for integrated circuits by
IEEE Standard 1149.1. This standard defines input/output
pins, logic control functions, and commands which facilitate
both board and device level testing without the use of specialized test equipment. The Xilinx XCR5064C devices use
the JTAG interface for In-System Programming/Reprogramming. Although only a subset of the full JTAG command set is implemented (see Table 2), the devices are
fully capable of sitting in a JTAG scan chain.
The Xilinx XCR5064C’s JTAG interface includes a TAP Port
defined by the IEEE 1149.1 JTAG Specification. As implemented in the Xilinx XCR5064C, the TAP Port includes four
of the five pins (refer to Table 3) described in the JTAG
specification: TCK, TMS, TDI, and TDO. The fifth signal
defined by the JTAG specification is TRST* (Test Reset).
TRST* is considered an optional signal, since it is not actually required to perform BST or ISP. The Xilinx XCR5064C
saves an I/O pin for general purpose use by not implementing the optional TRST* signal in the JTAG interface.
Instead, the Xilinx XCR5064C supports the test reset functionality through the use of its power up reset circuit, which
is included in all Xilinx CPLDs. The pins associated with the
TAP Port should connect to an external pull-up resistor to
keep the JTAG signs from floating when they are not being
used.
In the Xilinx XCR5064C, the four mandatory JTAG pins
each require a unique, dedicated pin on the device. The
devices come from the factory with these I/O pins set to
perform JTAG functions, but through the software, the final
function of these pins can be controlled. If the end application will require the device to be reprogrammed at some
future time with ISP, then the pins can be left as dedicated
JTAG functions, which means they are not available for use
as general purpose I/O pins. However, unlike competing
CPLDs, the Xilinx XCR5064C allow the macrocells associated with these pins to be used as buried logic when the
JTAG/ISP function is enabled. This is the default state for
the software, and no action is required to leave these pins
enabled for the JTAG/ISP functions. If, however, JTAG/ISP
is not required in the end application, the software can
specify that this function be turned off and that these pins
be used as general purpose I/O. Because the devices initially have the JTAG/ISP functions enabled, the JEDEC file
can be downloaded into the device once, after which the
JTAG/ISP pins will become general purpose I/O. This fea-
DS044 (v1.1) February 10, 2000
ture is good for manufacturing because the devices can be
programmed during test and assembly of the end product
and yet still use all of the I/O pins after the programming is
done. It eliminates the need for a costly, separate programming step in the manufacturing process. Of course, if the
JTAG/ISP function is never required, this feature can be
turned off in the software and the device can be programmed with an industry-standard programmer, leaving
the pins available for I/O functions. Table 4 defines the dedicated pins used by the four mandatory JTAG signals for
each of the XCR5064C package types.
5-Volt, In-System Programming (ISP)
ISP is the ability to reconfigure the logic and functionality of
a device, printed circuit board, or complete electronic system before, during, and after its manufacture and shipment
to the end customer. ISP provides substantial benefits in
each of the following areas:
•
•
•
Design
- Faster time-to-market
- Debug partitioning and simplified prototyping
- Printed circuit board reconfiguration during debug
- Better device and board level testing
Manufacturing
- Multi-Functional hardware
- Reconfigurability for Test
- Eliminates handling of “fine lead-pitch” components
for programming
- Reduced Inventory and manufacturing costs
- Improved quality and reliability
Field Support
- Easy remote upgrades and repair
- Support for field configuration, re-configuration, and
customization
The Xilinx XCR5064C allows for 5V, in-system programming/reprogramming of its EEPROM cells via its JTAG
interface. An on-chip charge pump eliminates the need for
externally-provided supervoltages, so that the XCR5064C
may be easily programmed on the circuit board using only
the 5-volt supply required by the device for normal operation. A set of low-level ISP basic commands implemented in
the XCR5064C enable this feature. The ISP commands
implemented in the Xilinx XCR5064C are specified in
Table 5. Please note that an ENABLE command must precede all ISP commands unless an ENABLE command has
already been given for a preceding ISP command.
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XCR5064C: 64 Macrocell CPLD with Enhanced Clocking
Table 2: XCR5064C Low-Level JTAG Boundary-Scan Commands
Instruction
(Instruction Code)
Register Used
Bypass
(1111)
Bypass Register
Description
Places the 1 bit bypass register between the TDI and TDO pins, which allows the BST data
to pass synchronously through the selected device to adjacent devices during normal device
operation. The Bypass instruction can be entered by holding TDI at a constant high value
and completing an Instruction-Scan cycle.
Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE to
be serially shifted out of TDO. The IDCODE instruction permits blind interrogation of the
components assembled onto a printed circuit board. Thus, in circumstances where the
component population may vary, it is possible to determine what components exist in a
product.
Idcode
(0001)
Boundary-Scan Register
Table 3: JTAG Pin Description
Pin
TCK
Name
Test Clock Output
TMS
Test Mode Select
TDI
Test Data Input
TDO
Test Data Output
Description
Clock pin to shift the serial data and instructions in and out of the TDI and TDO pins,
respectively.
Serial input pin selects the JTAG instruction mode. TMS should be driven high during
user mode operation.
Serial input pin for instructions and test data. Data is shifted in on the rising edge of
TCK.
Serial output pin for instructions and test data. Data is shifted out on the falling edge
of TCK. The signal is tri-stated if data is not being shifted out of the device.
Table 4: XCR5064C JTAG Pinout by Package Type
Device
XCR5064C
44-pin PLCC
44-pin VQFP
100-pin VQFP
TCK
32/C15
26/C15
62/C15
(Pin Number / Macrocell #)
TMS
TDI
13/B15
7/A8
7/B15
1/A8
15/B15
4/A8
TDO
38/D8
32/D8
73/D8
Table 5: Low Level ISP Commands
Instruction
(Register Used)
Enable
(ISP Shift Register)
Erase
(ISP Shift Register)
Program
(ISP Shift Register)
Verify
(ISP Shift Register)
7
Instruction
Code
1001
Description
Enables the Erase, Program, and Verify commands.
1010
Erases the entire EEPROM array.
1011
Programs the data in the ISP Shift Register into the addressed EEPROM row.
1100
Transfers the data from the addressed row to the ISP Shift Register. The data can
then be shifted out and compared with the JEDEC file. The outputs during this operation can be defined by the user.
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XCR5064C: 64 Macrocell CPLD with Enhanced Clocking
Terminations
The CoolRunner XCR5064C CPLDs are TotalCMOS™
devices. As with other CMOS devices, it is important to
consider how to properly terminate unused inputs and I/O
pins when fabricating a PC board. Allowing unused inputs
and I/O pins to float can cause the voltage to be in the linear
region of the CMOS input structures, which can increase
the power consumption of the device. The XCR5064C
CPLDs have programmable on-chip pull-down resistors on
each I/O pin. These pull-downs are automatically activated
by the fitter software for all unused I/O pins. Note that an I/O
macrocell used as buried logic that does not have the I/O
pin used for input is considered to be unused, and the
pull-down resistors will be turned on. We recommend that
any unused I/O pins on the XCR5064C device be left
unconnected.
There are no on-chip pull-down structures associated with
the dedicated input pins. Xilinx recommends that any
unused dedicated inputs be terminated with external 10kΩ
pull-up resistors. These pins can be directly connected to
VCC or GND, but using the external pull-up resistors maintains maximum design flexibility should one of the unused
dedicated inputs be needed due to future design changes.
DS044 (v1.1) February 10, 2000
When using the JTAG/ISP functions, it is also recommended that 10KΩ pull-up resistors be used on each of the
four mandatory signals. Letting these signals float can
cause the voltage on TMS to come close to ground, which
could cause the device to enter JTAG/ISP mode at unspecified times. See the application notes JTAG and ISP Overview for Xilinx XPLA1 and XPLA2 CPLDs and Terminating
Unused I/O Pins in Xilinx XPLA1 and XPLA2
CoolRunner™ CPLDs for more information.
JTAG and ISP Interfacing
A number of industry-established methods exist for
JTAG/ISP interfacing with CPLD’s and other integrated circuits. The Xilinx XCR5064C supports the following methods:
•
•
•
•
•
•
PC parallel port
Workstation or PC serial port
Embedded processor
Automated test equipment
Third party programmers
High-End ISP Tools
For more details on JTAG and ISP for the XCR5064C, refer
to the related application note: JTAG and ISP Overview for
Xilinx XPLA1 and XPLA2 CPLDs.
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XCR5064C: 64 Macrocell CPLD with Enhanced Clocking
Programming Specifications
Symbol
Parameter
DC Parameters
VCCP
VCC supply program/verify
ICCP
ICC limit program/verify
VIH
Input voltage (High)
VIL
Input voltage (Low)
VSOL
Output voltage (Low)
Output voltage (High)
VSOH
TDO_IOL Output current (Low)
TDO_IOH Output current (High)
AC Parameters
fMAX
TCK maximum frequency
PWE
Pulse width erase
PWP
Pulse width program
PWV
Pulse width verify
INIT
Initialization time
TMS_SU TMS setup time before TCK ↑
TDI_SU
TDI setup time before TCK ↑
TMS_H
TMS hold time after TCK ↑
TDI_H
TDI hold time after TCK ↑
TDO_CO TDO valid after TCK ↓
9
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Min.
Max.
Unit
4.5
5.5
200
V
mA
V
V
V
V
mA
mA
2.0
0.8
0.5
2.4
8
8
10
100
10
10
100
10
10
25
25
40
MHz
ms
ms
µs
µs
ns
ns
ns
ns
ns
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XCR5064C: 64 Macrocell CPLD with Enhanced Clocking
Absolute Maximum Ratings1
Symbol
VCC
VI
VOUT
IIN
IOUT
TJ
Tstr
Parameter
Supply voltage2
Input voltage
Output voltage
Input current
Output current
Maximum junction temperature
Storage temperature
Min.
-0.5
-1.2
-0.5
-30
-100
-40
-65
Max.
7.0
VCC+0.5
VCC+0.5
30
100
150
150
Unit
V
V
V
mA
mA
°C
°C
Note:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only.
Functional operation at these or any other condition above those indicated in the operational and programming specification
is not implied.
2. The chip supply voltage must rise monotonically.
Operating Range
Product Grade
Temperature
Voltage
Commercial
0 to +70°C
5.0V +5%
Industrial
-40 to +85°C
5.0V +10%
DC Electrical Characteristics For Commercial Grade Devices
Commercial: 0°C ≤ TAMB ≤ +70°C; 4.75V ≤ VCC ≤ 5.25V
Symbol
VIL
VIH
VI
VOL
VOH
II
IOZ
ICCQ1
ICCD1, 2
Parameter
Input voltage low
Input voltage high
Input clamp voltage3
Output voltage low
Output voltage high
Input leakage current
3-stated output leakage current
Standby current
Dynamic current
IOS
Short circuit output current3
CIN
CCLK
CI/O
Input pin capacitance3
Clock input capacitance3
I/O pin capacitance3
Test Conditions
VCC = 4.75V
VCC = 5.25V
VCC = 4.75V, IIN = -18 mA
VCC = 4.75V, IOL = 12 mA
VCC = 4.75V, IOH = -12 mA
VIN = 0 to VCC
VIN = 0 to VCC
VCC = 5.25V, TAMB = 0°C
VCC = 5.25V, TAMB = 0°C at 1 MHz
VCC = 5.25V, TAMB = 0°C at 50 MHz
One pin at a time for no longer than 1
second
TAMB = 25°C, f = 1 MHz
TAMB = 25°C, f = 1 MHz
TAMB = 25°C, f = 1 MHz
Min.
Max.
0.8
10
10
80
1
25
-200
Unit
V
V
V
V
V
µA
µA
µA
mA
mA
mA
84
12
10
pF
pF
pF
2.0
-1.2
0.5
2.4
-10
-10
-50
5
Notes:
1. See Table 1 on page 5 for typical values.
2. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled
and unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing.
3. This parameter guaranteed by design and characterization, not by test.
4. Except IN1 and IN2 = 10 pF.
DS044 (v1.1) February 10, 2000
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xcr5064c.fm Page 11 Tuesday, February 15, 2000 3:51 PM
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XCR5064C: 64 Macrocell CPLD with Enhanced Clocking
AC Electrical Characteristics1 For Commercial Grade Devices
Commercial: 0°C ≤ TAMB ≤ +70°C; 4.75V ≤ VCC ≤ 5.25V
Symbol
tPD_PAL
tPD_PLA
tCO
tSU_PAL
tSU_PLA
tH
tCH
tCL
tR
tF
fMAX1
fMAX2
fMAX3
tBUF
tPDF_PAL
tPDF_PLA
tCF
tINIT
tER
tEA
tRP
tRR
Parameter
-7
Min.
Propagation delay time, input (or feedback node) to output through PAL
2
Propagation delay time, input (or feedback node) to output through PAL
3
& PLA
Clock to out (global synchronous clock from pin)
2
Setup time (from input or feedback node) through PAL
4.5
Setup time (from input or feedback node) through PAL + PLA
6
Hold time2
Clock High time2
3
Clock Low time2
3
Input Rise time
Input Fall time
Maximum FF toggle rate2 (1/tCH + tCL)
167
Maximum internal frequency2 (1/tSUPAL + tCF)
133
Maximum external frequency2 (1/tSUPAL + tCO)
105
Output buffer delay time2
Input (or feedback node) to internal feedback node delay time through
PAL
Input (or feedback node) to internal feedback node delay time through
PAL+PLA
Clock to internal feedback node delay time
Delay from valid VCC to valid reset
Input to output disable2, 3
Input to output valid2
Input to register preset2
Input to register reset2
Max.
7.5
9
Min.
2
3
5
2
6
8
-10
Max.
10
12
ns
ns
2.5
5
2.5
7.5
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
6.5
9.5
ns
3
50
7.5
7.5
9
9
4.5
50
10
10
11
11
ns
µs
ns
ns
ns
ns
0
6.5
Unit
0
4
4
20
20
20
20
125
95
80
Notes:
1. Specifications measured with one output switching. See Figure 6 and Table 6 for derating.
2. This parameter guaranteed by design and characterization, not by test.
3. Output CL = 5 pF.
11
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XCR5064C: 64 Macrocell CPLD with Enhanced Clocking
DC Electrical Characteristics For Industrial Grade Devices
Industrial: -40°C ≤ TAMB ≤ +85°C; 4.5V ≤ VCC ≤ 5.5V
Symbol
VIL
VIH
VI
VOL
VOH
II
IOZ
ICCQ1
ICCD1, 2
Parameter
Input voltage low
Input voltage high
Input clamp voltage3
Output voltage low
Output voltage high
Input leakage current
3-stated output leakage current
Standby current
Dynamic current
IOS
Short circuit output current3
CIN
CCLK
CI/O
Input pin capacitance
Clock input capacitance
I/O pin capacitance
Test Conditions
VCC = 4.5V
VCC = 5.5V
VCC = 4.5V, IIN = -18 mA
VCC = 4.5V, IOL = 12 mA
VCC = 4.5V, IOH = -12 mA
VIN = 0 to VCC
VIN = 0 to VCC
VCC = 5.5V, TAMB = -40°C
VCC = 5.5V, TAMB = -40°C at 1 MHz
VCC = 5.5V, TAMB = -40°C at 50 MHz
One pin at a time for no longer than 1
second
TAMB = 25°C, f = 1 MHz
TAMB = 25°C, f = 1 MHz
TAMB = 25°C, f = 1 MHz
Min.
Max.
0.8
10
10
100
1
30
-230
Unit
V
V
V
V
V
µA
µA
µA
mA
mA
mA
84
12
10
pF
pF
pF
2.0
-1.2
0.5
2.4
-10
-10
-50
5
Notes:
1. See Table 1 on page 5 for typical values.
2. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled
and unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing.
3. This parameter guaranteed by design and characterization, not by test.
4. Except IN1 and IN2 = 10 pF.
DS044 (v1.1) February 10, 2000
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xcr5064c.fm Page 13 Tuesday, February 15, 2000 3:51 PM
R
XCR5064C: 64 Macrocell CPLD with Enhanced Clocking
AC Electrical Characteristics1 For Industrial Grade Devices
Industrial: -40°C ≤ TAMB ≤ +85°C; 4.5V ≤ VCC ≤ 5.5V
Symbol
tPD_PAL
tPD_PLA
tCO
tSU_PAL
tSU_PLA
tH
tCH
tCL
tR
tF
fMAX1
fMAX2
fMAX3
tBUF
tPDF_PAL
tPDF_PLA
tCF
tINIT
tER
tEA
tRP
tRR
Parameter
Min.
Propagation delay time, input (or feedback node) to output through PAL
2
Propagation delay time, input (or feedback node) to output through
3
PAL + PLA
Clock to out (global synchronous clock from pin)
2
Setup time (from input or feedback node) through PAL
6
Setup time (from input or feedback node) through PAL + PLA
8
Hold time
Clock High time
4
Clock Low time
4
Input Rise time
Input Fall time
Maximum FF toggle rate2 (1/tCH + tCL)
125
Maximum internal frequency2 (1/tSUPAL + tCF)
95
Maximum external frequency2 (1/tSUPAL + tCO)
77
Output buffer delay time
Input (or feedback node) to internal feedback node delay time through
PAL
Input (or feedback node) to internal feedback node delay time through
PAL+PLA
Clock to internal feedback node delay time
Delay from valid VCC to valid reset
Input to output disable2, 3
Input to output valid2
Input to register preset2
Input to register reset2
I10
Max.
10
12
7
Min.
2
3
2
7
9
I12
Max.
12
14
ns
ns
2.5
7.5
2.5
9.5
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
9.5
11.5
ns
4.5
50
10
10
11
11
5.5
50
12
12
12.5
12.5
ns
µs
ns
ns
ns
ns
0
8
Unit
0
5
5
20
20
20
20
100
80
67
Notes:
1. Specifications measured with one output switching. See Figure 6 and Table 6 for derating.
2. This parameter guaranteed by design and characterization, not by test.
3. Output CL = 5 pF.
13
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XCR5064C: 64 Macrocell CPLD with Enhanced Clocking
Switching Characteristics
The test load circuit and load values for the AC Electrical Characteristics are illustrated below.
VCC
S1
R1
COMPONENT
VALUES
R1
390Ω
R2
390Ω
C1
35 pF
VIN
VOUT
R2
C1
S2
MEASUREMENT
S1
S2
tPZH
Open
Closed
tPZL
Closed
Closed
tP
Closed
Closed
Note: For tPHZ and tPLZ C = 5 pF, and 3-state levels are
measured 0.5V from steady state active level.
SP00618
Voltage Waveform
VCC = 5V, 25°C
5.80
5.70
+3.0V
90%
5.60
10%
0V
5.50
tPD_PAL
(ns)
tR
tF
1.5ns
5.40
1.5ns
SP00368
5.30
MEASUREMENTS:
All circuit delays are measured at the +1.5V level of
inputs and outputs, unless otherwise specified.
5.20
Input Pulses
5.10
1
2
4
8
12
16
NUMBER OF OUTPUTS SWITCHING
SP00664
Figure 6:
tPD_PAL vs. Outputs Switching
DS044 (v1.1) February 10, 2000
Table 6: tPD_PAL vs. Number of Outputs Switching
(VCC = 5.0V)
Number Of
Outputs
Typical (ns)
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1
2
4
8
12
16
5.10
5.22
5.30
5.35
5.36
5.38
14
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XCR5064C: 64 Macrocell CPLD with Enhanced Clocking
Pin Descriptions
XCR5064C - 100-pin VQFP
XCR5064C - 44-pin PLCC
100
6
1
76
40
75
1
7
39
VQFP
PLCC
25
17
51
29
26
18
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Function
IN1
IN3
VDD
I/O-A0/CK3
I/O-A2
I/O-A5
I/O-A8 (TDI)
I/O-A11
I/O-A12
GND
I/O-A13
I/O-A15
I/O-B15 (TMS)
I/O-B13
VDD
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Function
I/O-B10
I/O-B8
I/O-B4
I/O-B3
I/O-B2
I/O-B0/CK2
GND
VDD
I/O-C0/CK1
I/O-C2
I/O-C3
I/O-C4
I/O-C7
I/O-C8
GND
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Function
I/O-C13
I/O-C15 (TCK)
I/O-D15
I/O-D13
VDD
I/O-D12
I/O-D11
I/O-D8 (TDO)
I/O-D7
I/O-D2
I/O-D0
GND
IN0-CK0
IN2-gtsn
SP00554
XCR5064C - 44-pin VQFP
44
34
1
33
VQFP
23
11
12
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Function
I/O-A8 (TDI)
I/O-A11
I/O-A12
GND
I/O-A13
I/O-A15
I/O-B15 (TMS)
I/O-B13
VDD
I/O-B10
I/O-B8
I/O-B4
I/O-B3
I/O-B2
I/O-B0/CK2
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
50
28
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Pin
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
Function
I/O-B3
VDD
I/O-B2
I/O-B1
I/O-B0/CK2
GND
VDD
I/O-C0/CK1
I/O-C1
I/O-C2
GND
I/O-C3
I/O-C4
I/O-C5
I/O-C6
I/O-C7
NC
NC
VDD
I/O-C8
NC
I/O-C9
NC
I/O-C10
I/O-C11
I/O-C12
GND
I/O-C13
I/O-C14
I/O-C15 (TCK)
I/O-D15
I/O-D14
I/O-D13
VDD
Pin
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Function
I/O-D12
I/O-D11
I/O-D10
NC
I/O-D9
NC
I/O-D8 (TDO)
GND
I/O-D7
I/O-D6
NC
NC
I/O-D5
I/O-D4
I/O-D3
VDD
I/O-D2
I/O-D1
I/O-D0
GND
IN0/CK0
IN2-gtsn
IN1
IN3
VDD
I/O-A0/CK3
I/O-A1
I/O-A2
GND
I/O-A3
I/O-A4
I/O-A5
NC
NC
SP00556
22
Function
GND
VDD
I/O-C0/CK1
I/O-C2
I/O-C3
I/O-C4
I/O-C7
I/O-C8
GND
I/O-C13
I/O-C15 (TCK)
I/O-D15
I/O-D13
VDD
I/O-D12
Function
I/O-A6
I/O-A7
VDD
I/O-A8 (TDI)
NC
I/O-A9
NC
I/O-A10
I/O-A11
I/O-A12
GND
I/O-A13
I/O-A14
I/O-A15
I/O-B15 (TMS)
I/O-B14
I/O-B13
VDD
I/O-B12
I/O-B11
I/O-B10
NC
I/O-B9
NC
I/O-B8
GND
NC
NC
I/O-B7
I/O-B6
I/O-B5
I/O-B4
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Function
I/O-D11
I/O-D8 (TDO)
I/O-D7
I/O-D2
I/O-D0
GND
IN0/CK0
IN2-gtsn
IN1
IN3
VDD
I/O-A0/CK3
I/O-A2
I/O-A5
SP00555
15
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XCR5064C: 64 Macrocell CPLD with Enhanced Clocking
Ordering Information
Example: XCR5064C -7 PC 44 C
Temperature Range
Device Type
Number of Pins
Speed Options
Package Type
Temperature Range
C = Commercial, TA = 0°C to +70°C
I = Industrial, TA = –40°C to +85°C
Speed Options
-12: 12 ns pin-to-pin delay
-10: 10 ns pin-to-pin delay
-7: 7.5 ns pin-to-pin delay
Packaging Options
VQ44: 44-pin VQFP
PC44: 44-pin PLCC
VQ100: 100-pin VQFP
Component Availability
Pins
Type
Code
XCR5064C
44
-12
-10
-7
Plastic VQFP
VQ44
I
C, I
C
Plastic PLCC
PC44
I
C, I
C
100
Plastic VQFP
VQ100
I
C, I
C
Revision History
Date
8/5/99
2/10/00
Version $
1.0
1.1
Revision
Initial Xilinx release.
Converted to Xilnx format and updated.
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