0 QPro Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR) R DS062 (v3.1) November 5, 2001 0 2 Preliminary Product Specification Features Description • XQ1701L/XQR1701L • QML Certified • Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGA devices The QPro™ series XQ1701L are Xilinx 3.3V high-density configuration PROMs. The XQR1701L are radiation hardened. These devices are manufactured on Xilinx QML certified manufacturing lines utilizing epitaxial substrates and TID lot qualification (per method 1019). • Simple interface to the FPGA; requires only one user I/O pin • Cascadable for storing longer or multiple bitstreams • Programmable reset polarity (active High or active Low) for compatibility with different FPGA solutions • Supports XQ4000XL/Virtex fast configuration mode (15.0 MHz) • Available in 44-pin ceramic LCC (M grade) package • Available in 20-pin SOIC package (XQ1701L only) • Programming support by leading programmer manufacturers. • Design support using the Xilinx Allianc™ and Foundation™ series software packages. • XQR1701L (only) • Fabricated on Epitaxial Silicon to improve latch performance (parts are immune to Single Event Latch-up) • Single Event Bit Upset immune • Total Dose tolerance in excess of 50 krad(Si) • All lots subjected to TID Lot Qualification in accordance with method 1019 (dose rate ~9.0 rad(Si)/sec) • XQ1701L (only) • Also available under the following Standard Microcircuit Drawing (SMD): 5962-9951401. For more information contact hte Defense Supply Center Columbus (DSCC): http://www.dscc.dla.mil/Programs/Smcr/ When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising clock edge, data appears on the PROM DATA output pin that is connected to the FPGA D IN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. Once configured, it disables the PROM. When the FPGA is in Slave Serial mode, the PROM and the FPGA must both be clocked by an incoming signal. Figure 1 shows a simplied block diagram. Multiple devices can be concatenated by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are interconnected. All devices are compatible and can be cascaded with other members of the family. For device programming, either the Xilinx Alliance or Foundation series development system compiles the FPGA design file into a standard Hex format, which is then transferred to most commercial PROM programmers. © 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS062 (v3.1) November 5, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 1 R QPro Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR) VCC RESET/ OE or OE/ RESET VPP GND CEO CE CLK Address Counter EPROM Cell Matrix TC Output OE DATA DS027_01_021500 Figure 1: Simplified Block Diagram (does not show programming circuit) Pin Description CE DATA When High, this pin disables the internal address counter, puts the DATA output in a high-impedance state, and forces the device into low-ICC standby mode. Data output is in a high-impedance state when either CE or OE are inactive. During programming, the DATA pin is I/O. Note that OE can be programmed to be either active High or active Low. CLK Each rising edge on the CLK input increments the internal address counter, if both CE and OE are active. RESET/OE When High, this input holds the address counter reset and puts the DATA output in a high-impedance state. The polarity of this input pin is programmable as either RESET/OE or OE/RESET. To avoid confusion, this document describes the pin as RESET/OE, although the opposite polarity is possible on all devices. When RESET is active, the address counter is held at "0", and puts the DATA output in a high-impedance state. The polarity of this input is programmable. The default is active High RESET, but the preferred option is active Low RESET, because it can be driven by the FPGAs INIT pin. The polarity of this pin is controlled in the programmer interface. This input pin is easily inverted using the Xilinx HW-130 Programmer. Third-party programmers have different methods to invert this pin. 2 CEO Chip Enable output, to be connected to the CE input of the next PROM in the daisy chain. This output is Low when the CE and OE inputs are both active AND the internal address counter has been incremented beyond its Terminal Count (TC) value. In other words: when the PROM has been read, CEO will follow CE as long as OE is active. When OE goes inactive, CEO stays High until the PROM is reset. Note that OE can be programmed to be either active High or active Low. VPP Programming voltage. No overshoot above the specified max voltage is permitted on this pin. For normal read operation, this pin must be connected to VCC. Failure to do so may lead to unpredictable, temperature-dependent operation and severe problems in circuit debugging. Do not leave VPP floating! VCC and GND Positive supply and ground pins. www.xilinx.com 1-800-255-7778 DS062 (v3.1) November 5, 2001 Preliminary Product Specification R QPro Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR) PROM Pinouts Pin Name • The RESET/OE input of all PROMs is best driven by the INIT output of the lead FPGA device. This connection assures that the PROM address counter is reset before the start of any (re)configuration, even when a reconfiguration is initiated by a VCC glitch. Other methods—such as driving RESET/OE from LDC or system reset—assume the PROM internal power-on-reset is always in step with the FPGAs internal power-on-reset. This may not be a safe assumption. • The PROM CE input can be driven from either the LDC or DONE pins. Using LDC avoids potential contention on the DIN pin. • The CE input of the lead (or only) PROM is driven by the DONE output of the lead FPGA device, provided that DONE is not permanently grounded. Otherwise, LDC can be used to drive CE, but must then be unconditionally High during user operation. CE can also be permanently tied Low, but this keeps the DATA output active and causes an unnecessary supply current of 10 mA maximum. 44-Pin CLCC DATA 2 CLK 5 RESET/OE (OE/RESET) 19 CE 21 GND 3, 24 CEO 27 VPP 41 VCC 44 Capacity Devices Configuration Bits XQR1701L 1,048,576 XQ1701L 1,048,576 FPGA Master Serial Mode Summary Xilinx FPGAs and Compatible PROMs. Device Configuration Bits XQ(R)1701L PROMs XQ(R)4013XL 393,632 1 XQ(R)4036XL 832,528 1 XQ(R)4062XL 1,433,864 2 XQ(R)4013XL 393,632 1 XQ(R)4036XL 832,528 1 XQ(R)4062XL 1,433,864 2 XQV(R)300 1,751,840 2 XQV(R)600 3,608,000 4 XQV(R)1000 6,127,776 6 Upon power-up or reconfiguration, an FPGA enters the Master Serial mode whenever all three of the FPGA mode-select pins are Low (M0=0, M1=0, M2=0). Data is read from the PROM sequentially on a single data line. Synchronization is provided by the rising edge of the temporary signal CCLK, which is generated during configuration. Controlling PROMs Connecting the FPGA device with the PROM. • The DATA output(s) of the of the PROM(s) drives the DIN input of the lead FPGA device. • The Master FPGA CCLK output drives the CLK input(s) of the PROM(s). • The CEO output of a PROM drives the CE input of the next PROM in a daisy chain (if any). DS062 (v3.1) November 5, 2001 Preliminary Product Specification The I/O and logic functions of the Configurable Logic Block (CLB) and their associated interconnections are established by a configuration program. The program is loaded either automatically upon power up, or on command, depending on the state of the three FPGA mode pins. In Master Serial mode, the FPGA automatically loads the configuration program from an external memory. The Xilinx PROMs have been designed for compatibility with the Master Serial mode. Master Serial Mode provides a simple configuration interface. Only a serial data line and two control lines are required to configure an FPGA. Data from the PROM is read sequentially, accessed via the internal address and bit counters which are incremented on every valid rising edge of CCLK. If the user-programmable, dual-function DIN pin on the FPGA is used only for configuration, it must still be held at a defined level during normal operation. The Xilinx FPGA families take care of this automatically with an on-chip default pull-up resistor. www.xilinx.com 1-800-255-7778 3 R QPro Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR) Programming the FPGA With Counters Unchanged Upon Completion When multiple FPGA-configurations for a single FPGA are stored in a PROM, the OE pin should be tied Low. Upon power-up, the internal address counters are reset and configuration begins with the first program stored in memory. Since the OE pin is held Low, the address counters are left unchanged after configuration is complete. Therefore, to reprogram the FPGA with another program, the DONE line is pulled Low and configuration begins at the last value of the address counters. This method fails if a user applies RESET during the FPGA configuration process. The FPGA aborts the configuration and then restarts a new configuration, as intended, but the PROM does not reset its address counter, since it never saw a High level on its OE input. The new configuration, therefore, reads the remaining data in the PROM and interprets it as preamble, length count etc. Since the FPGA is the master, it issues the necessary number of CCLK pulses, up to 16 million (224) and DONE goes High. However, the FPGA configuration will be completely wrong, with potential 4 contentions inside the FPGA and on its output pins. This method must, therefore, never be used when there is any chance of external reset during configuration. Cascading Configuration PROMs For multiple FPGAs configured as a daisy-chain, or for future FPGAs requiring larger configuration memories, cascaded PROMs provide additional memory. After the last bit from the first PROM is read, the next clock signal to the PROM asserts its CEO output Low and disables its DATA line. The second PROM recognizes the Low level on its CE input and enables its DATA output. See Figure 2. After configuration is complete, the address counters of all cascaded PROMs are reset if the FPGA RESET pin goes Low, assuming the PROM reset polarity option has been inverted. To reprogram the FPGA with another program, the DONE line goes Low and configuration begins where the address counters had stopped. In this case, avoid contention between DATA and the configured I/O use of DIN. www.xilinx.com 1-800-255-7778 DS062 (v3.1) November 5, 2001 Preliminary Product Specification R QPro Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR) Vcc DOUT OPTIONAL Daisy-chained FPGAs with Different configurations OPTIONAL Slave FPGAs with Identical Configurations FPGA MODES* VCC 3.3V VPP 4.7K DIN RESET RESET VPP VCC DATA CCLK CLK DONE CE INIT DATA PROM OE/RESET CEO CLK CE Cascaded Serial Memory OE/RESET * For mode pin connections, refer to the appropriate FPGA data sheet. (Low Resets the Address Pointer) CCLK (Output) DIN DOUT (Output) DS027_02_060100 Figure 2: Master Serial Mode. The one-time-programmable PROM supports automatic loading of configuration programs. Multiple devices can be cascaded to support additional FPGAs. An early DONE inhibits the PROM data output one CCLK cycle before the FPGA I/Os become active. DS062 (v3.1) November 5, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 5 R QPro Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR) Standby Mode Programming The PROM enters a low-power standby mode whenever CE is asserted High. The output remains in a high-impedance state regardless of the state of the OE input. The devices can be programmed on programmers supplied by Xilinx or qualified third-party vendors. The user must ensure that the appropriate programming algorithm and the latest version of the programmer software are used. The wrong choice can permanently damage the device. Table 1: Truth Table for Control Inputs Control Inputs Outputs RESET CE Internal Address DATA CEO ICC Inactive Low If address < TC(1): increment If address > TC(1): don’t change Active High-Z High Low Active Reduced Active Low Held reset High-Z High Active Inactive High Not changing High-Z High Standby Active High Held reset High-Z High Standby Notes: 1. The XC1700 RESET input has programmable polarity 2. TC = Terminal Count = highest address value. TC + 1 = address 0. Radiation Characteristics (XQR1701L only) Symbol Description Min Max Units TID Total ionizing dose, Method 1019 50 - krad(Si) SEL Single event latch-up. Heavy ion saturation cross section, LET1 > 120 MeV cm2/mg - 0 (cm2/Device) SEU Single event bit upset. Heavy ion saturation cross section LET > 120 MeV cm2/mg - 0 (cm2/Bit) SEFI2 Single event functional interupt, Heavy ion saturation cross section, 10% saturated intercept at LET = 6.0 MeV cm2/mg - 1.2e–5 (cm2/Device) Notes: 1. Single Event Effects testing was performed with heavy ion to a maximum LET of 120 MeV cm2/mg. 6 www.xilinx.com 1-800-255-7778 DS062 (v3.1) November 5, 2001 Preliminary Product Specification R QPro Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR) Absolute Maximum Ratings Symbol Description Conditions Units VCC Supply voltage relative to GND –0.5 to +4.0 V VPP Supply voltage relative to GND –0.5 to +12.5 V VIN Input voltage relative to GND –0.5 to VCC +0.5 V VTS Voltage applied to High-Z output –0.5 to VCC +0.5 V TSTG Storage temperature (ambient) –65 to +150 °C Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Operating Conditions Symbol VCC(1) Description Supply voltage relative to GND ceramic package (TC = –55°C to +125°C) plastic package (TJ = –55°C to +125°C) Military Min Max Units 3.0 3.6 V Min Max Units Notes: 1. During normal read operation VPP MUST be connected to VCC. DC Characteristics Over Operating Condition Symbol Description VIH High-level input voltage 2 VCC V VIL Low-level input voltage 0 0.8 V VOH High-level output voltage (IOH = –3 mA) 2.4 - V VOL Low-level output voltage (IOL = +3 mA) - 0.4 V ICCA Supply current, active mode (at maximum frequency) - 10 mA ICCS Supply current, standby mode (XQ1701L) - 100 µA Pre-rad (TID) - 300 µA Post-rad (TID) - 3 mA –10 10 µA Input capacitance (VIN = GND, f = 1.0 MHz) - 10 pF Output capacitance (VIN = GND, f = 1.0 MHz) - 10 pF ICCS(1) IL CIN COUT Supply current, standby mode (XQR1701L ) Input or output leakage current Notes: 1. ICCS, Standby Current is measured at +125°C for pre-radiation specifications and at room temperature for post-radiation specifications. DS062 (v3.1) November 5, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 7 R QPro Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR) AC Characteristics Over Operating Condition CE TSCE TSCE THCE RESET/OE THOE THC TLC TCYC CLK TOE TCE TCAC TDF TOH DATA TOH DS027_03_021500 XQ(R)1701L Symbol Description Min Max Units TOE OE to data delay - 30 ns TCE CE to data delay - 45 ns TCAC CLK to data delay - 45 ns - 50 ns delay(2,3) TDF CE or OE to data float TOH Data hold from CE, OE, or CLK(3) 0 - ns TCYC Clock periods 67 - ns TLC CLK Low time(3) 25 - ns THC CLK High time(3) 25 - ns TSCE CE setup time to CLK (to guarantee proper counting) 25 - ns THCE CE hold time to CLK (to guarantee proper counting) 0 - ns THOE OE hold time (guarantees counters are reset) 25 - ns Notes: 1. AC test load = 50 pF 2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. 8 www.xilinx.com 1-800-255-7778 DS062 (v3.1) November 5, 2001 Preliminary Product Specification R QPro Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR) AC Characteristics Over Operating Condition When Cascading RESET/OE CE CLK TCDF DATA Last Bit First Bit TOCK TOOE CEO TOCE TOCE DS027_04_021500 Symbol Description Min Max Units TCDF CLK to data float delay(2,3) - 50 ns TOCK CLK to CEO delay(3) - 30 ns TOCE CE to CEO delay(3) - 35 ns TOOE RESET/OE to CEO delay(3) - 30 ns Notes: 1. AC test load = 50 pF 2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. DS062 (v3.1) November 5, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 9 R QPro Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR) Ordering Information XQR1701L CC44 V Device Number Grade (Manufacturing Flow/ Temperature Range) Package Type Device Ordering Options Device Type Package Grade XQ1701L CC44 44-pin Ceramic Chip Carrier Package M Military Ceramic TC = – 55°C to +125°C XQR1701L(1) SO20 20-column Plastic Small Outline Package N Military Plastic TJ = –55°C to +125°C V QPro-Plus TC = – 55°C to +125°C Notes: 1. Radiation Hardened. 5962 9951401 Q Y A Generic Standard Microcircuit Drawing (SMD) Lead Finish Package Type Device Type QML Certified MIL-PRF-38535 SMD Ordering Options Device Type 9951401 - Package QML XQ1701L QYA 44-pin Ceramic Chip Carrier Package XQR1701L NXB 20-column Plastic Small Outline Package Lead Finish Solder Dip Solder Plate Valid Ordering Combinations 10 Mil-Std SMD Rad Hard SMD XQ1701LCC44M 5962-9951401QYA XQR1701LCC44M - XQ1701LSO20N 5962-9951401NXB XQR1701LCC44V www.xilinx.com 1-800-255-7778 DS062 (v3.1) November 5, 2001 Preliminary Product Specification R QPro Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR) Revision History The following table shows the revision history for this document. Date Version Revision 04/20/00 1.0 Initial Release 06/01/00 2.0 Combined XQR1700L Rad-Hard and XQ1701L devices, added XQ1704L and updated format. 02/08/01 3.0 Removed the XQ1704L and XQR1704L 11/05/01 3.1 Added V Grade to ordering combinations for Rad Hard version. DS062 (v3.1) November 5, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 11