YMF752 Preliminary AC’97 Rev2.1 Audio CODEC with SRC OVERVIEW YMF752 is an AC’97 Audio CODEC LSI, which is fully compliant with the industry standard “Audio CODEC ’97” component specification (Revision 2.1). YMF752 includes a SRC (Sampling Rate Converter) for supporting variable sampling rate and an AC-Link serial interface. Therefore, YMF752 is the best audio solution for both laptops and desktop PCs as well as AMR (Audio Modem Riser) and MDC (Mobile Daughter Card). YMF752 also supports low power consumption while normal operating and allows for controlling the power down mode. FEATURES • AC’97 Revision 2.1 Compliant • Exceeds PC98 / PC99 Audio Performance Requirements • Analog Inputs: - 4 Stereo Inputs: LINE, CD, VIDEO, AUX - 2 Monaural Inputs: Speakerphone and PC BEEP Inputs - 2 Independent Microphone Inputs • PC BEEP can directly output to Line Out • Internal +20dB amplifier circuitry for microphone • Analog Outputs: Stereo LINE Output, True LINE Level and Monaural Output • Supports 3D Enhancement (Wide Stereo) • Supports Variable Sampling Rate (48k/44.1k/22.05k/16k/11.025k/8kHz) • Programmable Power Down Mode • Supports EAPD (External Amplifier Power Down) • Power Supplies: Analog 5.0V, Digital 3.3V • 48-Pin SQFP Package (YMF752-S) The following functions are supported by using the software driver from YAMAHA. • XG Wave Table Synthesizer • Downloadable Sound (DLS) • Legacy Audio (Sound Blaster Pro compatibility and FM Synthesizer) on Pure DOS GENERAL MIDI logo is a trademark of Association of Musical Electronics Industry (AMEI), and indicates GM system level 1 compliant. XG logo is a trademark of YAMAHA Corporation. The contents of this catalog are target specifications and are subject to change without prior notice. When using this device, please recheck the specifications. YAMAHA CORPORATION YMF752 CATALOG Decembe 3, 1998 CATALOG No.:LSI-4MF752A02 July 2, 1999 YMF752 TEST EAPD CODEC ID1# CODEC ID0# (N.C.) (N.C.) AVss2 LNLVL_OUT_R (N.C.) LNLVL_OUT_L AVdd2 MONO_OUT 48 47 46 45 44 43 42 41 40 39 38 37 PIN CONFIGURATION DVss2 7 30 CAP2 SDATA_IN 8 29 CAP1 DVdd2 9 28 Vrefout SYNC 10 27 Vref RESET# 11 26 AVss1 PC_BEEP 12 25 AVdd1 24 CAP3 LINE_IN_R 31 23 6 LINE_IN_L BIT_CLK 22 CAP4 MIC2 32 21 5 MIC1 SDATA_OUT 20 ENABLE CD_R 33 19 4 CD_GND DVss1 18 TEST CD_L 34 17 3 VIDEO_R XTL_OUT 16 LINE_OUT_L VIDEO_L 35 15 2 AUX_R XTL_IN 14 LINE_OUT_R AUX_L 36 13 1 PHONE DVdd1 48-Pin SQFP Top View 2 July 2, 1999 YMF752 PIN DESCRIPTION No. Name I/O Function Digital power supply (+3.3V) 1 DVdd1 - Connect to the digital ground with 0.1mF and 47mF capacitors. 2 XTL_IN I 24.576MHz Clock Input 3 XTL_OUT O 24.576MHz Clock Output 4 DVss1 - Digital ground. Connect this pin to DVss2. 5 SDATA_OUT I AC’97 Serial Input Stream 6 BIT_CLK I/O 7 DVss2 - Digital ground. Connect this pin to DVss1. 8 SDATA_IN O AC’97 Serial Output Stream Connect this pin to DVdd2. AC’97 Bit Clock Digital power supply (+3.3V) 9 DVdd2 - Connect to the digital ground with 0.1mF and 47mF capacitors. Connect this pin to DVdd1. 10 SYNC I SYNC Input (Fixed at 48kHz) 11 RESET# I Hardware Reset 12 PC_BEEP AI PC Speaker Beep 13 PHONE AI Telephony Input 14 AUX_L AI AUX Input Left Channel 15 AUX_R AI AUX Input Right Channel 16 VIDEO_L AI Video Audio Input Left Channel 17 VIDEO_R AI Video Audio Input Right Channel 18 CD_L AI CD Audio Input Left Channel 19 CD_GND AI 20 CD_R AI CD Audio Input Right Channel 21 MIC1 AI Microphone Input 1 22 MIC2 AI Microphone Input 2 23 LINE_IN_L AI Line Input Left Channel 24 LINE_IN_R AI Line Input Right Channel CD Audio Analog Ground Connect this pin to CD Ground or Analog Ground. Analog Power Supply (+5.0V) 25 AVdd1 - Connect to the analog ground with 0.1mF and 47mF capacitors. Connect this pin to AVdd2. 26 AVss1 - 27 Vref AO 28 Vrefout AO Analog ground. Connect this pin to AVss2. Analog Reference Voltage Connect to the analog ground with 0.1mF and 10mF capacitors. Analog Reference Voltage Output 3 July 2, 1999 YMF752 No. Name I/O 29 CAP1 A 30 CAP2 A 31 CAP3 A 32 CAP4 A 33 ENABLE I+ Function Capacitor Connection Pin Connect to the analog ground with a 560pF capacitor. Capacitor Connection Pin Connect to the analog ground with a 560pF capacitor. Capacitor Connection Pin Connect to the analog ground with a 1000pF capacitor. Capacitor Connection Pin Connect to the analog ground with 0.1mF and 10mF capacitors. Normally, do not connect externally. In case of “low” level, YMF752 do not operate. 34 TEST I+ 35 LINE_OUT_L AO Line Output Left Channel LSI Test Pin (Do not connect externally.) 36 LINE_OUT_R AO Line Output Right Channel 37 MONO_OUT AO Monaural Output Analog power supply (+5.0V) 38 AVdd2 - Connect to the digital ground with 0.1mF and 47mF capacitors. Connect this pin to Avdd1. 39 LNLVL_OUT_L AO True LINE Level Output Left Channel 40 (N.C.) - 41 LNLVL_OUT_R AO 42 AVss2 - Analog ground. Connect to Avss1. 43 (N.C.) - Do not connect externally. 44 (N.C.) - Do not connect externally. 45 CODEC ID0# I+ CODEC ID (Do not connect externally.) 46 CODEC ID1# I+ CODEC ID (Do not connect externally.) 47 EAPD O External Amplifier Power Down 48 TEST O LSI Test Pin (Do not connect externally.) Do not connect externally. True LINE Level Output Right Channel Note) AI: Analog Input Pin, AO: Analog Output Pin, I+: Input Pin with a Pull-up resistor 4 July 2, 1999 YMF752 EAPD 0dB/ +20dB Power down Control ENABLE MUX VREF AVdd(2) AVss(2) CAP1 CAP2 CAP3 CAP4 Vrefout Vref DVss(2) DVdd(2) BLOCK DIAGRAM MIC1 MIC2 LINE_IN_R LINE_IN_L CD_R CD_GND CD_L VIDEO_R VIDEO_L AUX_R AUX_L PHONE CD Right BUF A/D SYNC SDATA_OUT SDATA_IN A/D AC’97 CD Left SRC digital MUX BIT_CLK Record R 16step Record L 16step MUX RESET# I/F D/A D/A PCM L 32step PCM R 32step Left Right 3D 5 MUX Master L 32step Master R 32step LNLVL L 32step LNLVL R 32step MUX XTL_OUT PC_BEEP LINE_OUT_L LINE_OUT_R LNLVL_OUT_L LNLVL_OUT_R Monaural 32step MONO_OUT MUX XTL_IN PC Beep 16step PHONE 32step AUX 32step VIDEO 32step CD 32step LINE 32step MIC 32step Timing Generator CODEC ID1# Volume Control CODEC ID0# July 2, 1999 YMF752 MIXER REGISTERS NAME D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 00h Reset 02h Master vol. Mute - ML5-0 - - MR5-0 8000h 04h LNLVL vol. Mute - ML5-0 - - MR5-0 8000h Master vol. Mono Mute - - - - - - - - - MM5-0 8000h 06h Reset 0Ah PC_BEEP vol. Mute - - - - - - - - - - 0Ch Phone vol. Mute - - - - - - - - - - GN4-0 8008h 0Eh Mic vol. Mute - - - - - - - - 20dB - GN4-0 8008h 10h Line in vol. Mute - - GL4-0 - - - GR4-0 8808h 12h CD vol. Mute - - GL4-0 - - - GR4-0 8808h 14h Video vol. Mute - - GL4-0 - - - GR4-0 8808h 16h Aux vol. Mute - - GL4-0 - - - GR4-0 8808h 18h PCM out vol. Mute - - GL4-0 - - - GR4-0 8808h 1Ah Record Select - - - - - - - - 1Ch Record Gain Mute - - - - - - - 20h General Purpose POP - 3D - - - MIX - - - 22h 3D Control - - - - - - - - - - - DP3-0 0000h 26h Power Down EAPD PR6 PR5 PR4 PR3 PR2 PR1 PR0 - - - - REF ANL DAC ADC N/A ID0 - - - - AMAP - - - - - - - - VRA x201h - - - - - - - - - - - - - - VRA 0000h 28h Extended Audio ID ID1 2Ah Ext’d audio Stat/Ctrl - - SL2-0 GL3-0 MS LPBK - PV3-0 - - SR2-0 0000h GR3-0 - - - 0000h 8000h - 0000h 2Ch PCM DAC Rate SR15-0 BB80h 32h PCM ADC Rate SR15-0 BB80h 7Ch Vendor ID 1 7Eh Vendor ID 2 Vendor ID 6 July 2, 1999 YMF752 SYSTEM CONNECTION DIAGRAM PC_BEEP PHONE AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND CD_R MIC1 LINE_IN_L LINE_IN_R Vrefout PC Beep Phone L-ch AUX R-ch AUX L-ch Video R-ch Video L-ch CD CD Ground R-ch CD MIC L-ch Line IN R-ch Line IN MONO_OUT LNLVL_OUT_L LNLVL_OUT_R LINE_OUT_L LINE_OUT_R Mono Out L-ch LNLVL Out R-ch LNLVL Out L-ch LINE Out R-ch LINE Out CAP1 CAP2 CAP3 CAP4 Vref YMF752-S AVdd1,2 AVss1,2 +5.0V DVdd1,2 +3.3V EAPD SDATA_IN SDATA_OUT BIT_CLK SYNC RESET# ID1# ID0# ENABLE XTL_IN XTL_OUT MIC2 DVss1,2 EAPD SDATA IN SDATA OUT BIT CLK SYNC RESET# 1) DGND AGND Power and Ground To get the most out of analog performance, it is necessary to split the ground into analog and digital blocks. Analog ground and digital ground earth at one point closed to the initial ground supply of the board. The layout of the ground pattern should be designed as large as possible and the impudence should be reduced to prevent from receiving ambient noise. In addition, use 0.1mF and 47mF capacitors to connect between the analog voltage pin and the analog ground as well as between the digital supply pin and the digital ground. 2) Reference Voltage As the reference voltage determines all analog signals’ reference levels of YMF752, noise generated from the reference voltage could affect the YMF752’s analog performance. To stabilize the YMF752’s reference voltage, insert a 0.1mF ceramic capacitor in parallel with a 10mF capacitor between Vref pin and the ground. The 0.1mF ceramic capacitor should be designed as close to the Vref pin as possible 3) Master Clock To suppress the master clock from affecting its surroundings, it is recommended to keep the master clock guarded on the ground so the noise can be reduced. 4) Unused Analog Input / Output pins For the unused analog input pins, short them through a 0.1mF ceramic capacitor to the analog ground. For the unused analog output pins, they should be left opened. 7 July 2, 1999 YMF752 ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Symbol Min. Max. Unit Analog Supply Voltage AVDD -0.3 7.0 V Digital Supply Voltage DVDD -0.3 4.6 V Analog Input Voltage VINA -0.3 AVDD+0.3 V Digital Input Voltage VIND -0.3 DVDD+0.3 V Ambient Temperature TOP 0 70 °C Storage Temperature TSTG -50 125 °C Note) DVSS = AVSS = 0V 2. Recommended Operating Conditions Parameter Symbol Min. Typ. Max. Unit Analog Operating Voltage AVDD 4.75 5.00 5.25 V Digital Operating Voltage DVDD 3.135 3.30 3.465 V TOP 0 25 70 °C Operating Ambient Temperature Note) DVSS = AVSS = 0V 3. DC Characteristics Parameter Symbol Condition Min. Typ. Max. Unit High Level 1 Input Voltage VIH1 *1 0.7 ´ DVDD - - V Low Level 1 Input Voltage VIL1 *1 - - 0.3 ´ DVDD V High Level 2 Input Voltage VIH2 *2 0.8 ´ DVDD - - V Low Level 2 Input Voltage VIL2 *2 - - 0.2 ´ DVDD V High Level Output Voltage VOH IOUT = -1mA DVDD - 0.55 - - V Low Level Output Voltage VOL IOUT = 1mA - - 0.55 V Input Leakage Current ILI -10 - 10 µA Pull-up Resistance RUP 50 100 200 kW Note) TOP=0~70°C, DVDD=3.3±0.165V, AVDD=5.0±0.25V, Capacitor load=50pF *1 : Apply to XTL_IN, RESET#, SYNC, SDATA_OUT and BIT_CLK *2 : Apply to CODEC ID0# and CODEC ID1# 8 July 2, 1999 YMF752 4. AC Characteristics 4-1. Reset Parameter Symbol Min. Typ. Max. Unit RESET# active low pulse width Trst_low 1.0 - - µs RESET# inactive to BIT_CLK start up delay Trst2clk 162.8 - - ns SYNC active high pulse width Tsync_high 1.0 1.3 - µs SYNC inactive to BIT_CLK start up delay Tsync2clk 162.8 - - ns Cold Reset (SDATA_OUT=“L”, SYNC=“L”) Warm Reset Note) TOP=25°C, AVDD=5.0V, Capacitor load=50pF Cold Reset Trst2clk Trst_low RESET# VIL BIT_CLK Warm Reset Tsync2clk Tsync_high SYNC VIH BIT_CLK 9 July 2, 1999 YMF752 4-2. AC-link Interface Parameter Symbol Min. Typ. Max. Unit Tclk_period - 81.38 - ns BIT_CLK low pulse width Tclk_low 36.0 40.7 45.0 ns BIT_CLK high pulse width Tclk_high 36.0 40.7 45.0 ns BIT_CLK rise time Trise_clk - - 6 ns BIT_CLK fall time Tfall_clk - - 6 ns Tsync_period - 20.8 - µs SYNC low pulse width Tsync_low - 19.5 - µs SYNC high pulse width Tsync_high - 1.3 - µs SYNC rise time Trise_sync - - 6 ns SYNC fall time Tfall_sync - - 6 ns SDATA_IN, SDATA_OUT setup time Tsetup 10.0 - - ns SDATA_IN, SDATA_OUT hold time Thold 10.0 - - ns SDATA_IN delay time Tdelay - - 15.0 ns SDATA_IN rise time Trise_din - - 6 ns SDATA_IN fall time Tfall_din - - 6 ns SDATA_OUT rise time Trise_dout - - 6 ns SDATA_OUT fall time Tfall_dout - - 6 ns Ts2_pdwn - - 1.0 µs Tsetup2rst 15.0 - - ns Toff - - 50 ns BIT_CLK clock period SYNC period AC-link Low Power Mode End of slot 2 to BIT_CLK, SDATA_IN low Active Test Mode Setup to trailing edge of RESET# Rising edge of RESET# to Hi-Z Note) TOP=25°C, AVDD=5.0V, Capacitor load=50pF BIT_CLK Tclk_high Tclk_low BIT_CLK Tclk_period SYNC Tsync_high Tsync_low SYNC Tsync_period 10 July 2, 1999 YMF752 Setup and Hold Tdelay Tsetup BIT_CLK SDATA_IN Thold SDATA_OUT, SYNC Signal Rise and Fall Trise_clk Tfall_clk BIT_CLK Trise_din Tfall_din Trise_dout Tfall_dout SDATA_IN Trise_sync Tfall_sync SYNC SDATA_OUT AC-link Low Power Mode Slot2 Slot1 BIT_CLK SDATA_OUT Write to 26h Data PR4 Don’t Care Ts2_pdown SDATA_IN Activate Test Mode Tsetup2rst RESET# SDATA_OUT Toff SDATA_IN, BIT_CLK Hi-Z 11 July 2, 1999 YMF752 5. Power Consumption Parameter Min. Typ. Max. Unit Normal Operating (26h : PR6-0 = “0”) AVDD mA DVDD mA Power Down Mode (26h : PR6-0 = “1”) AVDD mA DVDD mA Note) TOP=25°C, DVDD=3.3±0.165V, AVDD=5.0±0.25V 6. Analog Characteristics Parameter Min. Typ. Max. Unit Full Scale Line Input 1.0 Vrms Full Scale Microphone Input (0dB) 1.0 Vrms Full Scale Microphone Input (+20dB) 0.1 Vrms Full Scale Line Output 1.0 Vrms 102 dB 102 dB Analog S/N : CD to LINE_OUT 90 Analog S/N : Others to LINE_OUT Analog Frequency Response 20 20,000 S/N : D/A converter 85 96 dB S/N : A/D converter 75 86 dB THD : Line Output Hz 0.02 % 20 19,200 Hz Transition Band 19,200 28,800 Hz Stop Band 28,800 Hz 85 dB D/A & A/D Frequency Response Stop Band Rejection Out-of-Band Rejection 40 Group Delay dB 1 Power Supply Rejection Rate (1kHz) 40 Crosstalk between Inputs Channels ms dB -70 dB Attenuation & Gain Step PC_BEEP 3.0 dB Other than PC_BEEP 1.5 dB Input Impedance 10 VREF Output Voltage kW 2.5 V Note) TOP=25°C, DVDD=3.3±0.165V, AVDD=5.0±0.25V, 1kHz input sine wave 12 July 2, 1999 YMF752 EXTERNAL DIMENSIONS YMF752-S 9.00±0.40 7.00±0.30 25 24 48 13 7.00±0.30 37 1 12 P-0.5TYP 1.40TYP or 1.45TYP 1.85MAX. (Installation height) 0.20±0.10 or 0.18±0.10 0 MIN. (STAND OFF) 9.00±0.40 36 (1.0) 0-10˚ 0.50±0.20 LEAD THICKNESS : 0.125TYP or 0.15TYP The actual shape of the molded corner may slightly differ from the shape in this diagram. The figures in the parenthesis ( ) should be used as reference values. The dimensions of plastic body do not include burr of resin. Unit : mm (millimeters) Note : The LSIs for surface mounting need for special care on storage and soldering conditions. For detailed information, please contact your nearest agent of Yamaha. 13 July 2, 1999 YMF752 IMPORTANT NOTICE 1. Yamaha reserves the right to make changes to its Products and to this document without notice. The information contained in this document has been carefully checked and is believed to be reliable. However, Yamaha assumes no responsibilities for inaccuracies and makes no commitment to update or to keep current the information contained in this document. 2. These Yamaha Products are designed only for commercial and normal industrial applications, and are not suitable for other uses, such as medical life support equipment, nuclear facilities, critical care equipment or any other application the failure of which could lead to death, personal injury or environmental or property damage. Use of the Products in any such application is at the customer's sole risk and expense. 3. YAMAHA ASSUMES NO LIABILITY FOR INCIDENTAL, CONSEQUENTIAL OR SPECIAL DAMAGES OR INJURY THAT MAY RESULT FROM MISAPPLICATION OR IMPROPER USE OR OPERATION OF THE PRODUCTS. 4. YAMAHA MAKES NO WARRANTY OR REPRESENTATION THAT THE PRODUCTS ARE SUBJECT TO INTELLECTUAL PROPERTY LICENSE FROM YAMAHA OR ANYTHIRD PARTY, AND YAMAHA MAKES NO WARRANTY OR REPRESENTATION OF NON-INFRINGEMENT WITH RESPECT TO THE PRODUCTS. YAMAHA SPECIFICALLY EXCLUDES ANY LIABILITY TO THE CUSTOMER OR ANY THIRD PARTY ARISING FROM OR RELATED TO THE PRODUCTS' INFRINGEMENT OF ANY THIRD PARTY'S INTELLECTUAL PROPERTY RIGHTS, INCLUDING THE PATENT, COPYRIGHT, TRADEMARK OR TRADE SECRET RIGHTS OF ANY THIRD PARTY. 5. EXAMPLES OF USE DESCRIBED HEREIN ARE MERELY TO INDICATE THE CHARACTERISTICS AND PERFORMANCE OF YAMAHA PRODUCTS. YAMAHA ASSUMES NO RESPONSIBILITY FOR ANY INTELLECTUAL PROPERTY CLAIMS OR OTHER PROBLEMS THAT MAY RESULT FROM APPLICATIONS BASED ON THE EXAMPLES DESCRIBED HEREIN. YAMAHA MAKES NO WARRANTY WITH RESPECT TO THE PRODUCTS, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR USE AND TITLE. Note) The specifications of this product are subject to improvement change without prior notice. AGENCY YAMAHA CORPORATION Address inquires to : Semi-conductor Sales Department - Head Office - Tokyo Office - Osaka Office - U.S.A. Office 14 203, MatsunokiJima, Toyooka-mura. Iwata-gun, Shizuoka-ken, 438-0192 Tel. +81-539-62-4918 Fax. +81-539-62-5054 2-17-11, Takanawa, Minato-ku, Tokyo, 108-8568 Tel. +81-3-5488-5431 Fax. +81-3-5488-5088 1-13-17, Namba Naka, Naniwa-ku, Osaka City, Osaka, 556-0011 Tel. +81-6-6633-3690 Fax. +81-6-6633-3691 YAMAHA System Technology. 100 Century Center Court, San Jose, CA 95112 Tel. +1-408-467-2300 Fax. +1-408-437-8791 July 2, 1999