ISO2-CMOS MT8960/61/62/63/64/65/66/67 Integrated PCM Filter Codec Data Sheet Features February 2005 • ST-BUS compatible • Transmit/Receive filters & PCM Codec in one I.C • Meets AT&T D3/D4 and CCITT G711 and G712 • µ-Law: MT8960/62/64/67 • A-Law: MT8961/63/65/67 • Low power consumption: • Op.: 30 mW typ. Stby.: 2.5 mW typ. Digital Coding Options: • MT8964/65/66/67 CCITT Code MT8960/61/62/63 Alternative Code Digitally controlled gain adjust of both filters • Analog and digital loopback • Filters and codec independently user accessible for testing • Powerdown mode available • 2.048 MHz master clock input • Up to six uncommitted control outputs • ±5 V ±5% power supply Ordering Information MT8960/61/64/65AE MT8962/63AE MT8962/63/66/67AS MT8963ASR MT8960AE1 MT8962/63AE1 MT8962AS1 MT8963AS1 18 20 20 20 18 20 20 20 Pin Pin Pin Pin Pin Pin Pin Pin PDIP PDIP SOIC SOIC PDIP* PDIP* SOIC* SOIC* Tubes Tubes Tubes Tape & Reel Tubes Tubes Tubes Tubes *Pb Free Matte Tin -40°C to +85°C Description Manufactured in ISO2-CMOS, these integrated filter/codecs are designed to meet the demanding performance needs of the digital telecommunications industry, e.g., PABX, Central Office, Digital telephones. ANUL VX Analog to Digital PCM Encoder Transmit Filter SD0 SD1 SD2 SD3 Output Register SD4 SD5 VR CSTi CA A Register 8-Bits Output Register Control Logic F1i Input Register DSTi B-Register 8-Bits PCM Digital to Analog Decoder Receive Filter VRef GNDA GNDD VDD DSTo VEE Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved. C2i MT8960/61/62/63/64/65/66/67 MT8962/63/66/67 MT8960/61/64/65 CSTi DSTi C2i DSTo VDD F1i CA SD3 SD2 18 17 16 15 14 13 12 11 10 1 2 3 4 5 6 7 8 9 Data Sheet CSTi DSTi C2i DSTo VDD SD5 SD4 F1i CA SD3 GNDD VRef GNDA VR ANUL VX VEE SD0 SD1 18 PIN PDIP 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 GNDD VRef GNDA VR ANUL VX VEE SD0 SD1 SD2 20 PIN PDIP/SOIC Figure 2 - Pin Connections Pin Description Pin Name Description CSTi Control ST-BUS In is a TTL-compatible digital input used to control the function of the filter/codec. Three modes of operation may be effected by applying to this input a logic high (VDD), logic low (GNDD), or an 8-bit serial word, depending on the logic states of CA and F1i. Functions controlled are: powerdown, filter gain adjust, loopback, chip testing, SD outputs. DSTi Data ST-BUS In accepts the incoming 8-bit PCM word. Input is TTL-compatible. C2i DSTo Clock Input is a TTL-compatible 2.048 MHz clock. Data ST-BUS Out is a three-state digital output driving the PCM bus with the outgoing 8-bit PCM word. VDD Positive power Supply (+5 V). F1i Synchronization Input is an active low digital input enabling (in conjunction with CA) the PCM input, PCM output and digital control input. It is internally sampled on every positive edge of the clock, C2i, and provides frame and channel synchronization. CA Control Address is a three-level digital input which enables PCM input and output and determines into which control register (A or B) the serial data, presented to CSTi, is stored. SD3 System Drive Output is an open drain output of an N-channel transistor which has its source tied to GNDA. Inactive state is open circuit. SD4-5 System Drive Outputs are open drain outputs of N-channel transistors which have their source tied to GNDD. Inactive state is open circuit. SD0-2 System Drive Outputs are “Totempole“ CMOS outputs switching between GNDD and VDD. Inactive state is logic low. VEE Negative power supply (-5 V). VX Voice Transmit is the analog input to the transmit filter. ANUL VR GNDA VRef GNDD Auto Null is used to integrate an internal auto-null signal. A 0.1 µF capacitor must be connected between this pin and GNDA. Voice Receive is the analog output of the receive filter. Analog ground (0 V). Voltage Reference input to D to A converter. Digital ground (0 V). 2 Zarlink Semiconductor Inc. MT8960/61/62/63/64/65/66/67 MT8960/62 MT8964/66 Digital Output Digital Output 11111111 10000000 11110000 10001111 11100000 10011111 11010000 11000000 10101111 10110000 11001111 10100000 10010000 10000000 00000000 00010000 00100000 11011111 11101111 11111111 01111111 01101111 00110000 01001111 01000000 01010000 00111111 00101111 01100000 00011111 01110000 00001111 00000000 01111111 Bit 7... 0 MSB LSB 10111111 01011111 -2.415V -1.207V 0V +1.207V +2.415V Analog Input Voltage (VIN) Figure 3 - µ-Law Encoder Transfer Characteristic 3 Zarlink Semiconductor Inc. Data Sheet MT8960/61/62/63/64/65/66/67 MT8961/63 MT8965/67 Digital Output Digital Output 11111111 10101010 11110000 10100101 11100000 10110101 11010000 11000000 10000101 10110000 11100101 10100000 10010000 10000000 00000000 00010000 00100000 11110101 11000101 11010101 01010101 01000101 00110000 01100101 01000000 01010000 00010101 00000101 01100000 00110101 01110000 00100101 00101010 01111111 Bit 7... 0 MSB LSB Data Sheet 10010101 01110101 -2.5V -1.25V 0V +1.25V +2.5V Analog Input Voltage (VIN) Figure 4 - A-Law Encoder Transfer Characteristic Functional Description Figure 1 shows the functional block diagram of the MT8960-67. These devices provide the conversion interface between the voiceband analog signals of a telephone subscriber loop and the digital signals required in a digital PCM (pulse code modulation) switching system. Analog (voiceband) signals in the transmit path enter the chip at VX, are sampled at 8 kHz, and the samples quantized and assigned 8-bit digital values defined by logarithmic PCM encoding laws. Analog signals in the receive path leave the chip at VR after reconstruction from digital 8-bit words. Separate switched capacitor filter sections are used for bandlimiting prior to digital encoding in the transmit path and after digital decoding in the receive path. All filter clocks are derived from the 2.048 MHz master clock input, C2i. Chip size is minimized by the use of common circuitry performing the A to D and D to A conversion. A successive approximation technique is used with capacitor arrays to define the 16 steps and 8 chords in the signal conversion process. Eight-bit PCM encoded digital data enters and leaves the chip serially on DSTi and DSTo pins, respectively. Transmit Path Analog signals at the input (Vx) are firstly bandlimited to 508 kHz by an RC lowpass filter section. This performs the necessary anti-aliasing for the following first-order sampled data lowpass pre-filter which is clocked at 512 kHz. This further bandlimits the signal to 124 kHz before a fifth-order elliptic lowpass filter, clocked at 128 kHz, provides the 3.4 kHz bandwidth required by the encoder section. A 50/60 Hz third-order highpass notch filter clocked at 8 kHz completes the transmit filter path. Accumulated DC offset is cancelled in this last section by a switchedcapacitor auto-zero loop which integrates the sign bit of the encoded PCM word, fed back from the codec and 4 Zarlink Semiconductor Inc. MT8960/61/62/63/64/65/66/67 Data Sheet injects this voltage level into the non-inverting input of the comparator. An integrating capacitor (of value between 0.1 and 1 µF) must be externally connected from this point (ANUL) to the Analog Ground (GNDA). The absolute gain of the transmit filter (nominally 0 dB at 1 kHz) can be adjusted from 0 dB to 7 dB in 1 dB steps by means of three binary controlled gain pads. The resulting bandpass characteristics with the limits shown in Figure 10 meet the CCITT and AT&T recommended specifications. Typical attenuations are 30 dB for 0-60 Hz and 35 dB for 4.6 kHz and above. The filter output signal is an 8 kHz staircase waveform which is fed into the codec capacitor array, or alternatively, into an external capacitive load of 250 pF when the chip is in the test mode. The digital encoder generates an eightbit digital word representation of the 8 kHz sampled analog signal. The first bit of serial data stream is bit 7 (MSB) and represents the sign of the analog signal. Bits 4-6 represent the chord which contains the analog sample value. Bits 0-3 represent the step value of the analog sample within the selected chord. The MT8960-63 provide a sign plus magnitude PCM output code format. The MT8964/66 PCM output code conforms to the AT &T D3 specification, i.e., true sign bit and inverted magnitude bits. The MT8965/67 PCM output code conforms to the CCITT specifications with alternate digit inversion (even bits inverted). See Figs. 3 and 4 for the digital output code corresponding to the analog voltage, VIN, at VX input. The eight-bit digital word is output at DSTo at a nominal rate of 2.048 MHz, via the output buffer as the first 8-bits of the 125 µs sampling frame. Receive Path An eight-bit PCM encoded digital word is received on DSTi input once during the 125 µs period and is loaded into the input register. A charge proportional to the received PCM word appears on the capacitor array and an 8 kHz sample and hold circuit integrates this charge and holds it for the rest of the sampling period. The receive (D/A) filter provides interpolation filtering on the 8 kHz sample and hold signal from the codec. The filter consists of a 3.4 kHz lowpass fifth-order elliptic section clocked at 128 kHz and performs bandlimiting and smoothing of the 8 kHz "staircase" waveform. In addition, sinx/x gain correction is applied to the signal to compensate for the attenuation of higher frequencies caused by the capacitive sample and hold circuit. The absolute gain of the receive filter can be adjusted from 0 dB to -7 dB in 1 dB steps by means of three binary controlled gain pads. The resulting lowpass characteristics, with the limits shown in Figure 11, meet the CCITT and AT & T recommended specifications. Typical attenuation at 4.6 kHz and above is 30 dB. The filter is followed by a buffer amplifier which will drive 5V peak/peak into a 10k ohm load, suitable for driving electronic 2-4 wire circuits. VRef An external voltage must be supplied to the VRef pin which provides the reference voltage for the digital encoding and decoding of the analog signal. For VRef = 2.5 V, the digital encode decision value for overload (maximum analog signal detect level) is equal to an analog input VIN = 2.415 V (µ-Law version) or 2.5 V (A-Law version) and is equivalent to a signal level of 3.17 dBm0 or 3.14 dBm0 respectively, at the codec. The analog output voltage from the decoder at VR is defined as: µ-Law: V Ref X A-Law: V Ref X [( -0.5 128 ) ( )(16.533+ S)]± + 2C 128 [( )( 0.532+ S )] ± 2C+1 128 V V OFFSET OFFSETC=0 5 Zarlink Semiconductor Inc. MT8960/61/62/63/64/65/66/67 V Ref X 2 [( 128 )(16.532+ S )] ± C V Data Sheet OFFSETC≠0 where C = chord number (0-7) S = step number (0-15) VRef is a high impedance input with a varying capacitive load of up to 40 pF. The recommended reference voltage for the MT8960 series of codecs is 2.5 V ±0.5%. The output voltage from the reference source should have a maximum temperature coefficient of 100 ppm/C°. This voltage should have a total regulation tolerance of ±0.5% both for changes in the input voltage and output loading of the voltage reference source. A voltage reference circuit capable of meeting these specifications is shown in Figure 5. Analog Devices’AD1403A voltage reference circuit is capable of driving a large number of codecs due to the high input impedance of the VRef input. Normal precautions should be taken in PCB layout design to minimize noise coupling to this pin. A 0.1 µF capacitor connected from VRef to ground and located as close as possible to the codec is recommended to minimize noise entering through VRef. This capacitor should have good high frequency characteristics. NC NC NC NC 8 7 6 5 VRef 0.1 µF AD1403A 1 2 3 MT8960-67 FILTER/CODEC 4 NC +5 V 2.5 V Figure 5 - Typical Voltage Reference Circuit Timing The codec operates in a synchronous manner (see Figure 9a). The codec is activated on the first positive edge of C2i after F1i has gone low. The digital output at DSTo (which is a three-state output driver) will then change from a high impedance state to the sign bit of the encoded PCM word to be output. This will remain valid until the next positive edge, when the next most significant bit will be output. On the first negative clock edge (after F1i signal has been internally synchronized and CA is at GNDD or VEE) the logic signal present at DSTi will be clocked into the input shift register as the sign bit of the incoming PCM word. The eight-bit word is thus input at DSTi on negative edges of C2i and output at DSTo on positive edges of C2i. F1i must return to a high level after the eighth clock pulse causing DSTo to enter high impedance and preventing further input data to DSTi. F1i will continue to be sampled on every positive edge of C2i. (Note: F1i may subsequently be taken low during the same sampling frame to enable entry of serial data into CSTi. This occurs usually mid-frame, in conjunction with CA=VDD, in order to enter an 8-bit control word into Register B. In this case, PCM input and output are inhibited by CA at VDD.) Internally the codec will then perform a decode cycle on the newly input PCM word. The sampled and held analog signal thus decoded will be updated 25 µs from the start of the cycle. After this the analog input from the filter is sampled for 18 µs, after which digital conversion takes place during the remaining 82 µs of the sampling cycle. 6 Zarlink Semiconductor Inc. MT8960/61/62/63/64/65/66/67 Data Sheet Since a single clock frequency of 2.048 MHz is required, all digital data is input and output at this rate. DSTo, therefore, assumes a high impedance state for all but 3.9 µs of the 125 µs frame. Similarly, DSTi input data is valid for only 3.9 µs. Digital Control Functions CSTi is a digital input (levels GNDD to VDD) which is used to control the function of the filter/codec. It operates in three different modes depending on the logic levels applied to the Control Address input (CA) and chip enable input (F1i) (see Table 1). Mode 1 CA=-5V (VEE); CSTi=0V (GNDD) The filter/codec is in normal operation with nominal transmit and receive gain of 0dB. The SD outputs are in their active states and the test modes cannot be entered. CA = -5V (VEE); CSTi = +5V (VDD) A state of powerdown is forced upon the chip whereby DSTo becomes high impedance, VR is connected to GNDA and all analog sections have power removed. Mode 2 CA= -5V (VEE); CSTi receives an eight-bit control word CSTi accepts a serial data stream synchronously with DSTi (i.e., it accepts an eight-bit serial word in a 3.9 µs timeslot, updated every 125 µs, and is specified identically to DSTi for timing considerations). This eight-bit control word is entered into Control Register A and enables programming of the following functions: transmit and receive gain, powerdown, loopback. Register B is reset to zero and the SD outputs assume their inactive state. Test modes cannot be entered. Mode 3 CA=0V (GNDD); CSTi receives an eight-bit control word As in Mode 2, the control word enters Register A and the aforementioned functions are controlled. In this mode, however, Register B is not reset, thus not affecting the states of the SD outputs. CA=+5V (VDD); CSTi receives an 8-bit control word In this case the control word is transferred into Register B. Register A is unaffected. The input and output of PCM data is inhibited. The contents of Register B controls the six uncommitted outputs SD0-SD5 (four outputs, SD0-SD3, on MT8960/61/64/65 versions of chip) and also provide entry into one of the three test modes of the chip. Note: For Modes 1 and 2, F1i must be at logic low for one period of 3.9 µs, in each 125 µs cycle, when PCM data is being input and output, and the control word at CSTi enters Register A. For Mode 3, F1i must be at a logic low for two periods of 3.9 µs, in each 125 µs cycle. In the first period, CA must be at GNDD or VEE, and in the second period CA must be high (VDD). 7 Zarlink Semiconductor Inc. MT8960/61/62/63/64/65/66/67 Mode CA CSTi 1 (Note 1) VEE GNDD 2 VEE VDD Data Sheet Function Normal chip operation. Powerdown. Serial Eight-bit control word into Register A. Register B is reset. Data 3 (Note 2) GNDD Serial Eight-bit control word into register A. Register B is unaffected. Data VDD Serial Eight-bit control word into register A. Register B is unaffected. Data Note 1: When operating in Mode 1, there should be only one frame pulse (F1i) per 125 µs frame Note 2: When operating in Mode 3, PCM input and output is inhibited by CA=VDD. Table 1 - Digital Control Modes BIT 2 BIT 1 BIT 0 TRANSMIT (A/D) FILTER GAIN (dB) 0 0 0 0 0 0 1 +1 0 1 0 +2 0 1 1 +3 1 0 0 +4 1 0 1 +5 1 1 0 +6 1 1 1 +7 BIT 5 BIT 4 BIT 3 RECEIVE (D/A) FILTER GAIN (dB) 0 0 0 0 0 0 1 -1 0 1 0 -2 0 1 1 -3 1 0 0 -4 1 0 1 -5 1 1 0 -6 1 1 1 -7 8 Zarlink Semiconductor Inc. MT8960/61/62/63/64/65/66/67 BIT 0 Data Sheet TRANSMIT (A/D) FILTER GAIN (dB) BIT 2 BIT 1 BIT 7 BIT 6 FUNCTION CONTROL 0 0 Normal operation 0 1 Digital Loopback 1 0 Analog Loopback 1 1 Powerdown Table 2 - Control States - Register A Control Registers A, B The contents of these registers control the filter/codec functions as described in Tables 2 and 3. Bit 7 of the registers is the MSB and is defined as the first bit of the serial data stream input (corresponding to the sign bit of the PCM word). On initial power-up these registers are set to the powerdown condition for a maximum of 25 clock cycles. During this time it is impossible to change the data in these registers. Chip Testing By enabling Register B with valid data (eight-bit control word input to CSTi when F1i=GNDD and CA= VCC) the chip testing mode can be entered. Bits 6 and 7 (most sign bits) define states for testing the transmit filter, receive filter and the codec function. The input in each case is VX input and the output in each case is VR output. (See Table 3 for details.) Loopback Loopback of the filter/codec is controlled by the control word entered into Register A. Bits 6 and 7 (most sign bits) provide either a digital or analog loopback condition. Digital loopback is defined as follows: • PCM input data at DSTi is latched into the PCM input register and the output of this register is connected to the input of the 3-state PCM output register. • The digital input to the PCM digital-to-analog decoder is disconnected, forced to zero (0). • The output of the PCM encoder is disabled and thus the encoded data is lost. The PCM output at DSTo is determined by the PCM input data. Analog loopback is defined as follows: • PCM input data is latched, decoded and filtered as normal but not output at VR. • Analog output buffer at VR has its input shorted to GNDA and disconnected from the receive filter output. • Analog input at VX is disconnected from the transmit filter input. • The receive filter output is connected to the transmit filter input. Thus the decode signal is fed back through the receive path and encoded in the normal way. The analog output buffer at VR is not tested by this configuration. In both cases of loopback, DSTi is the input and DSTo is the output. 9 Zarlink Semiconductor Inc. MT8960/61/62/63/64/65/66/67 Data Sheet Logic Control Outputs SD0-5 These outputs are directly controlled by the logic states of bits 0-5 in Register B. A logic low (GNDD) in Register B causes the SD outputs to assume an inactive state. A logic high (VDD) in Register B causes the SD outputs to assume an active state (see Table 3). SD0-2 switch between GNDD and VDD and may be used to control external logic or transistor circuitry, for example, that employed on the line card for performing such functions as relay drive for application of ringing to line, message waiting indication, etc. SD3-5 are used primarily to drive external analog circuitry. Examples may include the switching in or out of gain sections or filter sections (e.g., ring trip filter) (Figure 7). MT8962/63/66/67 provides all six SD outputs. MT8960/61/64/65 each packaged in an 18-pin DIP provide only four control outputs, SD0-3. Telephone Set 2 Wire Analog PCM Highway Supervision Protection Battery Feed 2W/4W Converter Ringing MT8960/61 MT8962/63 MT8964/65 MT8966/67 Figure 6 - Typical Line Termination LOGIC CONTROL OUTPUTS SD0-SD2 BITS 0-2 0 Inactive state - logic low (GNDD). 1 Active state - logic high (VDD). BIT 3 LOGIC CONTROL OUTPUT SD3 0 Inactive state - High Impedance. 1 Active state - GNDA. LOGIC CONTROL OUTPUTS SD4, SD5 BITS 4,5 0 Inactive state - High Impedance. 1 Active state - GNDD. BIT 7 BIT 6 0 0 CHIP TESTING CONTROLS Normal operation. 10 Zarlink Semiconductor Inc. MT8960/61/62/63/64/65/66/67 BITS 0-2 Data Sheet LOGIC CONTROL OUTPUTS SD0-SD2 0 1 Transmit filter testing, i.e.: Transmit filter input connected to VX input Receive filter and Buffer disconnected from VR 1 0 Receive filter testing, i.e.: Receive filter input connected to VX input Receive filter input disconnected from codec 1 1 Codec testing i.e.: Codec analog input connected to VX Codec analog input disconnected from transmit filter output Codec analog output connected to VR VR disconnected from receive filter output Table 3 - Control States - Register B Powerdown Powerdown of the chip is achieved in several ways: Internal Control: 1) 2) Initial Power-up. Initial application of VDD and VEE causes powerdown for a period of 25 clock cycles and during this period the chip will accept input only from C2i. The B-register is reset to zero forcing SD0-5 to be inactive. Bits 0-5 of Register A (gain adjust bits) are forced to zero and bits 6 and 7 of Register A become logic high thus reinforcing the powerdown. Loss of C2i. Powerdown is entered 10 to 40 µs after C2i has assumed a continuous logic high (VDD). In this condition the chip will be in the same state as in (1) above. Note: If C2i stops at a continuous logic low (GNDD), the digital data and status is indeterminate. External Control: 1) 2) Register A. Powerdown is controlled by bits 6 and 7 (when both at logic high) of Register A which in turn receives its control word input via CSTi, when F1i is low and CA input is either at VEE or GNDD. Power is removed from the filters and analog sections of the chip. The analog output buffer at VR will be connected to GNDA. DSTo becomes high impedance and the clocks to the majority of the logic are stopped. SD outputs are unaffected and may be updated as normal. CSTi Input. With CA at VEE and CSTi held at continuous logic high the chip assumes the same state as described in External Control (1) above. 11 Zarlink Semiconductor Inc. MT8960/61/62/63/64/65/66/67 Data Sheet Message Waiting MT8960/61/64/65 From ST-BUS CSTi From ST-BUS DSTi Master Clock to ST-BUS 5V C2i DSTo VDD (With Relay Drive) GNDD VRef -100 V DC 2.5 V GNDA VR 0.1µF ANUL Alignment F1i VX Register Select CA VEE SD3 SD0 SD2 SD1 -5 V Ring Trip Filter (With Relay Drive) Gain Section 2/4 Wire Converter Figure 7 - Typical Use of the Special Drive Outputs 12 Zarlink Semiconductor Inc. Telephone Line Ring Feed -48 V DC (With Relay Drive) -48 V DC 90 VRMS MT8960/61/62/63/64/65/66/67 DSTi VX DSTo VR CDTi SD0 .. . SDn Speech Switch 8980 •• • Data Sheet Line Interface & Monitoring Circuitry Line 1 MT8960-67 8 8 Controlling MicroProcessor • • • • • • Repeated for Lines 2 to 255 Repeated for Lines 2 to 255 8 8 Control & Signalling 8980 DSTi VX DSTo VR CDTi SD0 .. . SDn MT8960-67 •• • Line Interface & Monitoring Circuitry Line 256 Figure 8 - Example Architecture of a Simple Digital Switching System using the MT8960-67 13 Zarlink Semiconductor Inc. MT8960/61/62/63/64/65/66/67 Data Sheet Absolute Maximum Ratings* Parameter 1 DC Supply Voltages Symbol Min. Max. Units VDD-GNDD -0.3 +6.0 V VEE-GNDD -6.0 +0.3 V VRef GNDA VDD V 2 Reference Voltage 3 Analog Input VX VEE VDD V 4 Digital Inputs Except CA GNDD-0.3 VDD+0.3 V CA VEE-0.3 VDD+0.3 V SD0-2 GNDD-0.3 VDD+0.3 V SD3 VEE-0.3 VDD+0.3 V SD4-5 VEE-0.3 VDD+0.3 V 20 mA +125 °C 500 mW 5 Output Voltage 6 Current On Any Pin II 7 Storage Temperature TS 8 Power Dissipation at 25°C (Derate 16 mW/°C above 75°C) -55 PDiss * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions Characteristics 1 Supply Voltage Voltages are with respect to GNDD unless otherwise stated Sym. Min. Typ.* Max. Units VDD 4.75 5.0 5.25 V VEE -5.25 -5.0 -4.75 V VRef 2 Voltage On Digital Ground VGNDD 2.5 0.0 +0.1 Vdc Ref. to GNDA -0.4 0.0 +0.4 Vac Ref. to GNDA 400 ns max. duration in 125 µs cycle +70 °C 4.0 4.0 mA mA All digital inputs at VDD or GNDD (or VEE for CA) µA Mean current mA mA All digital inputs at VDD or GNDD (or VEE for CA) 0 Operating Temperature TO 4 Operating Current VDD VEE IDD IEE 3.0 3.0 VRef IRef 2.0 VDD VEE IDDO IEEO Note 1: Standby Current See Note 1 -0.1 3 5 V Comments 0.25 0.25 Temperature coefficient of V Ref should be better than 100 ppm/°C. 14 Zarlink Semiconductor Inc. 1.0 1.0 MT8960/61/62/63/64/65/66/67 Data Sheet DC Electrical Characteristics - Voltages are with respect to GNDD unless otherwise stated. TA=0 to 70°C, VDD=5V±5%, VEE=-5V±5%, VRef=2.5V±0.5%, GNDA=GNDD=0V,Clock Frequency =2.048MHz. Outputs unloaded unless otherwise specified. Characteristics 1 D 2 I G I 3 T 4 A L 5 Sym. Min. Typ.* Max. Units Test Conditions Except CA II 10.0 µA VIN = GNDD to VDD CA IIC 10.0 µA VIN = VEE to VDD Input Low Except CA VIL 0.0 0.8 V Voltage CA VILC VEE VEE+1.2 V Input High Voltage All Inputs VIH 2.4 5.0 V Input Intermediate CA Voltage VIIC 0.0 0.8 V Output Leakage Current (Tristate) I0Z µA µA Output High Impedance 10.0 Input Current DSTo SD3-5 ±0.1 Output Low DSTo VOL 0.4 V IOUT =1.6 mA Voltage SD0-2 VOL 1.0 V IOUT =1 mA Output High DSTo VOH 4.0 V IOUT =-100µA Voltage SD0-2 VOH 4.0 V IOUT =-1mA Output Resistance SD3-5 ROUT 1.0 KΩ VOUT =+1V Output Capacitance DSTo COUT 4.0 pF Output High Impedance 1 0 Input Current VX IIN µA VEE ≤ VIN ≤ VCC 1 1 Input Resistance VX RIN 10.0 MΩ VX CIN 30.0 pF fIN = 0 - 4 kHz VX VOSIN +1.0 mV See Note 2 VR ROUT 100 Ω Output Offset Voltage VR VOSO 100 mV 6 D I G 7 I T 8 A L 9 A 1 N Input Capacitance 2 A 1 L Input Offset Voltage 3 O G 1 Output Resistance 4 1 5 2.0 10.0 UT Digital Input= +0 * Typical figures are at 25°C with nominal ±5V supplies. For design aid only: not guaranteed and not subject to production testing. Note 2: V OSIN specifies the DC component of the digitally encoded PCM word. 15 Zarlink Semiconductor Inc. MT8960/61/62/63/64/65/66/67 Data Sheet AC Electrical Characteristics - Voltages are with respect to GNDD unless otherwise stated. TA=0 to 70°C, VDD=5V±5%, VEE=-5V±5%, VRef=2.5V±0.5%, GNDA=GNDD=0V, Clock Frequency=2.048 MHz. Outputs unloaded unless otherwise specified. Characteristics Sym. Min. Typ.* Max Units 2.046 2.048 2.05 MHz Test Conditions 1 Clock Frequency C2i fC 2 Clock Rise Time C2i tCR 50 ns 3 Clock Fall Time C2i tCF 50 ns 4 Clock Duty Cycle C2i 60 % 5 Chip Enable Rise Time F1i tER 100 ns 6 Chip Enable Fall Time F1i tEF 100 ns 7 Chip Enable Setup Time F1i tES 50 ns See Note 4 Chip Enable Hold Time F1i tEH 25 ns See Note 4 Output Rise Time DSTo tOR 100 ns Output Fall Time DSTo tOF 100 ns Propagation Delay Clock DSTo to Output Enable tPZL tPZH 122 122 ns ns Propagation Delay Clock to Output DSTo tPLH tPHL 100 100 ns ns 13 Input Rise Time CSTi DSTi tIR 100 100 ns ns 14 Input Fall Time CSTi DSTi tIF 100 100 ns ns 15 Input Setup Time CSTi DSTi tISH tISL 25 0 ns ns 16 Input Hold Time CSTi DSTi tIH 60 60 ns ns Propagation Delay Clock to SD Output SD tPCS 400 ns CL = 100 pF SD Output Fall Time SD tSF 200 ns CL = 20 pF SD Output Rise Time SD tSR 400 ns tDL 122 ns 8 9 10 11 12 17 18 19 20 D I G I T A L D I G I T A L Digital Loopback Time DSTi to DSTo 40 50 See Note 3 RL=10 KΩ to VCC CL=100 pF (See Figures 9a, 9b, 9c) * Typical figures are at 25°C with nominal ±5V supplies. For design aid only: not guaranteed and not subject to production testing. Note 3: The filter characteristics are totally dependent upon the accuracy of the clock frequency providing F1i is synchronized to C2i. The A/D and D/A functions are unaffected by changes in clock frequency. Note 4: This gives a 75 ns period, 50 ns before and 25 ns after the 50% point of C2i rising edge, when change in F1i will give an undetermined state to the internally synchronized enable signal. 16 Zarlink Semiconductor Inc. MT8960/61/62/63/64/65/66/67 Data Sheet AC Electrical Characteristics - Transmit (A/D) Path - Voltages are with respect to GNDD unless otherwise stated. TA=0 to 70°C, VDD=5V±5%, VEE=-5V±5%, VRef=2.5V±0.5%, GNDA=GNDD=0V, Clock Frequency = 2.048MHz, Filter Gain Setting = 0dB. Outputs unloaded unless otherwise specified. Characteristics Sym. Analog Input at VX equivalent to the overload decision level at the codec VIN 2 Absolute Gain (0dB setting) GAX 3 Absolute Gain (+1dB to +7dB settings) 4 Gain Variation 1 5 A N A L O G Gain Tracking (See Figure 12) 7 Quantization Distortion (See Figure 13) Typ. * Max. 4.82 9 5.00 0 Units Level at codec: µ-Law: 3.17 dBm0 A-Law: 3.14 dBm0 See Note 6 -0.25 +0.25 dB 0 dBm0 @ 1004 Hz -0.35 +0.35 dB from nominal, @ 1004 Hz TA=0°C to 70°C GAXT 0.01 dB With Supplies GAXS 0.04 dB/V CCITT G712 (Method 1) GTX1 GTX2 DQX1 CCITT G712 (Method 1) Test Conditions VPP VPP With Temp CCITT G712 (Method 2) AT&T 6 Min. -0.25 +0.25 dB -0.25 -0.50 +0.25 +0.50 dB dB Sinusoidal Level: +3 to -20 dBm0 Noise Signal Level: -10 to -55 dBm0 -55 to -60 dBm0 -0.25 -0.50 -1.50 +0.25 +0.50 +1.50 dB dB dB Sinusoidal Level: +3 to -40 dBm0 -40 to -50 dBm0 -50 to -55 dBm0 28.00 35.60 33.90 29.30 14.20 dB dB dB dB dB Noise Signal Level: -3 dBm0 -6 to -27 dBm0 -34 dBm0 -40 dBm0 -55 dBm0 35.30 29.30 24.30 dB dB dB Sinusoidal Input Level: 0 to -30 dBm0 -40 dBm0 -45 dBm0 CCITT G712 (Method 2) AT&T DQX2 Idle Channel C-message NCX 18 dBrnC0 µ-Law Only Noise Psophometric NPX -67 dBm0p CCITT G712 NSFX -56 dBm0 CCITT G712 -46 dB Input Signal: 0 dBm0 @ 1.02 kHz 270 µs @ 1004 Hz µs µs µs Input Signal: 400-3200 Hz Sinewave at 0 dBm0 8 Single Frequency Noise 9 Harmonic Distortion (2nd or 3rd Harmonic) 10 Envelope Delay 11 Envelope Delay Variation With Frequency DAX 1000-2600 Hz 600-3000 Hz 400-3200 Hz DDX 60 150 250 17 Zarlink Semiconductor Inc. MT8960/61/62/63/64/65/66/67 Data Sheet AC Electrical Characteristics - Transmit (A/D) Path - Voltages are with respect to GNDD unless otherwise stated. TA=0 to 70°C, VDD=5V±5%, VEE=-5V±5%, VRef=2.5V±0.5%, GNDA=GNDD=0V, Clock Frequency = 2.048MHz, Filter Gain Setting = 0dB. Outputs unloaded unless otherwise specified. A N A L O G 12 Quantization Distortion (cont’d) (See Figure 13) CCITT G712 (Method 2) AT&T DQX2 Intermodulation Distortion CCITT G712 50/60 Hz IMDX CCITT G712 2 tone IMDX AT&T IMDX 35.30 29.30 24.30 dB dB dB Sinusoidal Input Level: 0 to -30 dBm0 -40 dBm0 -45 dBm0 -55 dB 50/60 Hz @ -23 dBm0 and any signal within 300-3400 Hz at -9 dBm0 -41 dB 740 Hz and 1255 Hz @ -4 to -21 dBm0. Equal Input Levels -47 dB 2nd order products -49 dB 3rd order products -25 -30 0.00 0.125 0.125 0.030 0.100 -14 -32 dB dB dB dB dB dB dB dB dB 0 dBm0 Input Signal -70 dB 0 dBm0 @ 1.02 kHz in D/A dB dB Input 50 mVRMS at 1.02 kHz 1 2 3 4 tone IMDX 4 Gain Relative to ≤50 Hz Gain @ 1004 Hz 60 Hz (See Figure 10) 200 Hz 300-3000 Hz 3200 Hz 3300 Hz 3400 Hz 4000 Hz ≥4600 Hz GRX 14 Crosstalk D/A to A/D CTRT 15 Power Supply Rejection VDD VEE 16 Overload Fig.15) (See 13 Distortion -1.8 0.125 0.275 0.350 -0.80 PSS R1 PSS R2 33 35 Transmit Filter Response Input frequency=1.02kHz * Typical figures are at 25°C with nominal ±5V supplies. For design aid only: not guaranteed and not subject to production testing Note 6: 0dBm0=1.185 V RMS for the µ-Law codec. 0dBm0=1.231 V RMS for the A-Law codec. 18 Zarlink Semiconductor Inc. MT8960/61/62/63/64/65/66/67 Data Sheet AC Electrical Characteristics - Receive (D/A) Path - Voltages are with respect to GNDD unless otherwise stated. TA=0 to 70°C, VDD=5V±5%, VEE=-5V±5%, VRef=2.5V±0.5%, GNDA=GNDD=0V, Clock Frequency = 2.048MHz, Filter Gain Setting = 0dB. Outputs unloaded unless otherwise specified. Characteristics 1 Sym. Analog output at VR equivalent to the overload decision level at codec VOUT 2 Absolute Gain (0dB setting) GAR 3 Absolute Attenuation (-1dB to -7dB settings) 4 5 6 Gain Variation Max. 4.829 5.000 Units Vpp Vpp -0.25 +0.25 dB -0.35 +0.35 dB Test Conditions Level at codec: µ-Law: 3.17 dBm0 A-Law: 3.14 dBm0 RL=10 KΩ See Note 7 0 dBm0 @ 1004Hz From nominal, @ 1004Hz GART 0.01 dB With Supplies GARS 0.04 dB/V GTR1 CCITT G712 (Method 2) AT & T GTR2 CCITT G712 (Method 1) DQR1 CCITT G712 (Method 2) AT & T 7 Typ.* With Temp. Gain Tracking CCITT G712 (See Figure 12) (Method 1) A N A L Quantization O Distortion G (See Fig. 13) Min. DQR2 TA=0°C to 70°C -0.25 +0.25 dB -0.25 -0.50 +0.25 +0.50 dB dB Sinusoidal Level: +3 to -10 dBm0 Noise Signal Level: -10 to -55 dBm0 -55 to -60 dBm0 -0.25 -0.50 -1.50 +0.25 +0.50 +1.50 dB dB dB Sinusoidal Level: +3 to -40 dBm0 -40 to -50 dBm0 -50 to -55 dBm0 28.00 35.60 33.90 29.30 14.30 dB dB dB dB dB Noise Signal Level: -3 dBm0 -6 to -27 dBm0 -34 dBm0 -40 dBm0 -55 dBm0 36.40 30.40 25.40 dB dB dB Sinusoidal Input Level: 0 to -30 dBm0 -40 dBm0 -45 dBm0 Idle Channel C-message NCR 12 dBrnC0 µ-Law Only Noise Psophometric NPR -75 dBm0p CCITT G712 NSFR -56 dBm0 -46 dB 8 Single Frequency Noise 9 Harmonic Distortion (2nd or 3rd Harmonic) 10 Intermodulation Distortion CCITT G712 Input Signal 0 dBm0 at 1.02 kHz CCITT G712 2 tone IMDR2 -41 dB AT & T IMDR3 -47 dB 2nd order products 4 tone IMDR4 -49 dB 3rd order products 19 Zarlink Semiconductor Inc. MT8960/61/62/63/64/65/66/67 Data Sheet AC Electrical Characteristics - Receive (D/A) Path - Voltages are with respect to GNDD unless otherwise stated. TA=0 to 70°C, VDD=5V±5%, VEE=-5V±5%, VRef=2.5V±0.5%, GNDA=GNDD=0V, Clock Frequency = 2.048MHz, Filter Gain Setting = 0dB. Outputs unloaded unless otherwise specified. 11 Envelope Delay DAR 12 Envelope Delay 1000-2600 Hz Variation with 600-3000 Hz Frequency 400-3200 Hz DDR 13 14 15 Gain Relative to <200 Hz Gain @ 1004 Hz 200 Hz A (See Figure 11) 300-3000 Hz N 3300 Hz A 3400 Hz L 4000 Hz O ≥4600 Hz G Crosstalk A/D to D/A Power Supply Rejection VDD VEE GRR @ 1004 Hz µs µs µs Input Signal: 400 - 3200 Hz digital sinewave at 0 dBm0 0.125 0.125 0.125 0.030 -0.100 -14.0 -28.0 dB dB dB dB dB dB dB 0 dBm0 Input Signal -70 dB 0 dBm0 @ 1.02 kHz in A/D dB dB Input 50 mVRMS at 1.02 kHz 90 170 265 -0.5 -0.125 -0.350 -0.80 CTTR PSRR3 PSRR4 µs 210 33 35 16 Receive Filter Response Overload Distortion Input frequency=1.02 (See Fig. 15) kHz * Typical figures are at 25°C with nominal ±5V supplies. For design aid only: not guaranteed and not subject to production testing. Note 7: 0dBm0=1.185 V RMS for µ-Law codec and 0dBm0=1.231 V RMS for A-Law codec. 20 Zarlink Semiconductor Inc. MT8960/61/62/63/64/65/66/67 Data Sheet 125 µs C2i INPUT F1i INTERNAL ENABLE DSTo OUTPUT DSTi INPUT 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 HIGH IMPEDANCE 7 7 6 7 6 5V CA (Mode 3) 0V CSTi INPUT 7 6 5 4 3 2 1 LOAD A-REGISTER LOAD B-REGISTER Figure 9a - Timing Diagram - 125 µs Frame Period 21 Zarlink Semiconductor Inc. 0 MT8960/61/62/63/64/65/66/67 Data Sheet 8 CLOCK CYCLES (See Note) 90% 50% 10% C2i Input tCR tEF tCF tER 90% F1i Input 10% tES DSTo Output tEH tES tEH tES high impedance tEH high-Z tPZL tPZH tPZL tPZH Figure 9b - Timing Diagram - Output Enable Note: In typical applications, F1i will remain low for 8 cycles of C2i. However, the device will function normally as long as tES and t EH are met at each positive edge of C2i. C2i Input 90% 50% 10% tCF tCR DSTo Output 90% 50% 10% tOR DSTi, CSTi Input tOF tPLH tPLH 90% 50% 10% tIF tIR tIH tISH Figure 9c - Timing Diagram - Input/Output 22 Zarlink Semiconductor Inc. tISL MT8960/61/62/63/64/65/66/67 SCALE B SCALE A 0 10 Attenuation Relative To Attenuation At 1 kHz (dB) PASSBAND ATTENUATION Data Sheet SCALE A SCALE B -0.125 -0.125 0.35 STOPBAND ATTENUATION 0.125 0.35 1 1 -14 SIN ∏(4000-F) 1200 10 -18 SIN ∏(4000-F) 1200 14 2 2 20 30 3 3 30 32 40 4 4 40 20 5060 100 200 300 3000 3200 3300 3400 4000 4600 FREQUENCY (Hz) Figure 10 - Attenuation vs Frequency for Transmit (A/D) Filter 23 Zarlink Semiconductor Inc. -7/9 Note: Above function crossover occurs at 4000Hz. 25 0 -1 5000 10000 MT8960/61/62/63/64/65/66/67 SCALE A PASSBAND ATTENUATION SCALE A Data Sheet SCALE B STOPBAND ATTENUATION -0.125 0 0.125 0.35 1 Attenuation Relative To Attenuation At 1 kHz (dB) 1 -14 SIN ∏(4000-F) -1 1200 10 14 0 2 2 20 3 3 28 30 4 4 40 100 200 300 3000 3200 3300 3400 4000 4600 FREQUENCY (Hz) Figure 11 - Attenuation vs Frequency for Receive (D/A) Filter 24 Zarlink Semiconductor Inc. 5000 10000 MT8960/61/62/63/64/65/66/67 Data Sheet 5a. CCITT Method 1 CCITT End-To-End Spec Gain Variation (dB) +1.0 +1.0 +0.5 +0.5 +0.25 +0.25 0 1 2 Channel Spec 0 -60 -55 -50 -40 -30 -20 -10 -10 -0.25 -0.25 -0.5 -0.5 -1.0 -1.0 Bandlimited White Noise Test Signal 0 -3 Input Level (dBm0) Sinusiodal Test Signal 5b. CCITT Method 2 +1.5 CCITT End-To-End Spec Gain Variation (dB) +1.0 +0.5 1 2 Channel Spec +0.25 0 -60 -50 -40 -30 -20 -10 0 +3 -0.25 -0.5 -1.0 -1.5 Sinusoidal Test Signal Figure 12 - Variation of Gain With Input Level 25 Zarlink Semiconductor Inc. Input Level (dBm0) MT8960/61/62/63/64/65/66/67 Data Sheet 6a. CCITT Method 1 40 1 2 Channel Spec 35.6 Signal to Total Distortion Ratio (dB) 33.9 30 33.9 32.2 29.3 27.6 28.0 26.3 CCITT End-To-End Spec 20 14.3 12.6 10 0 -60 -55 -40 -50 -34 -30 -27 -20 -10 -6 -3 0 +3 Input Level (dBm0) 6b. CCITT Method 2 40 1 36.4 2 Channel Spec D/A 1 35.3 2 Channel Spec A/D 36.4 35.3 Signal to Total Distortion Ratio (dB) 33.0 30.4 30 33.0 CCITT End-To-End Spec 29.3 25.4 27.0 24.3 22.0 20 10 0 -60 -50 -40 -30 Input Level (dBm0) -20 -10 Figure 13 - Signal to Total Distortion Ratio vs Input Level 26 Zarlink Semiconductor Inc. 0 MT8960/61/62/63/64/65/66/67 Data Sheet 1000 CCITT ½ Channel Spec Envelope Delay (µs) 750 (2800Hz) 500 370 (600Hz) 250 125 (2600Hz) 0 500 1000 1500 2000 2500 Figure 14 - Envelope Delay Variation Frequency 27 Zarlink Semiconductor Inc. 3000 MT8960/61/62/63/64/65/66/67 Data Sheet Fundamental Output Power (dBm0)* 5 4.5 4 3 3 4 5 6 7 8 Input Level (dBm0) *Relative to Fundamental Output power level with +3 dBm0 input signal level at a frequency of 1.02 kHz. Figure 15 - Overload Distortion (End-to-End) 28 Zarlink Semiconductor Inc. 9 For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request. Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE