ZARLINK MT8981D

ISO-CMOS ST-BUSTM Family
MT8981D
Digital Switch
Data Sheet
Features
February 2005
•
Zarlink ST-BUS compatible
•
4-line x 32-channel inputs
•
4-line x 32-channel outputs
•
128 ports non-blocking switch
•
Single power supply (+5 V)
•
Low power consumption: 30 mW Typ.
•
Microprocessor-control interface
•
Three-state serial outputs
Ordering Information
MT8981DE
40 Pin PDIP
MT8981DP
44 Pin PLCC
MT8981DPR
44 Pin PLCC
MT8981DP1 44 Pin PLCC*
MT8981DPR1 44 Pin PLCC*
*Pb Free Matte Tin
Tubes
Tubes
Tape & Reel
Tubes
Tape & Reel
-40°C to +85°C
Description
This VLSI ISO-CMOS device is designed for switching
PCM-encoded voice or data, under microprocessor
control, in a modern digital exchange, PBX or Central
Office. It provides simultaneous connections for up to
128 64 kbit/s channels. Each of the four serial inputs
and outputs consist of 32 64 kbit/s channels
multiplexed to form a 2048 kbit/s ST-BUS stream. In
addition, the MT8981 provides microprocessor read
and write access to individual ST-BUS channels.
C4i
STi2
VSS
Frame
Counter
STi0
STi1
VDD
F0i
Serial
to
Parallel
Converter
ODE
Output
MUX
Data
Memory
Control Register
STi3
Connection
Memory
STo0
Parallel
to
Serial
Converter
Control Interface
DS CS
R/W A5/
A0
DTA D7/
D0
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1997-2005, Zarlink Semiconductor Inc. All Rights Reserved.
STo1
STo2
STo3
NC
STi2
STi1
STi0
DTA
IC
ODE
STo0
STo1
STo2
NC
MT8981D
DTA
STi0
STi1
STi2
STi3
IC
IC
IC
IC
VDD
F0i
C4i
A0
A1
A2
A3
A4
A5
DS
R/W
6
5
4
3
2
1
44
43
42
41
40
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
STo3
IC
IC
IC
IC
VSS
D0
D1
D2
D3
D4
NC
A3
A4
A5
DS
R/W
CS
D7
D6
D5
NC
18
19
20
21
22
23
24
25
26
27
28
STi3
IC
IC
IC
IC
VDD
F0i
C4i
A0
A1
A2
Data Sheet
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
IC
ODE
STo0
STo1
STo2
STo3
IC
IC
IC
IC
VSS
D0
D1
D2
D3
D4
D5
D6
D7
CS
40 PIN PLASTIC DIP
44 PIN PLCC
Figure 2 - Pin Connections
Pin Description
Pin #
40
44
DIP PLCC
Name
DTA
Description
1
2
Data Acknowledgement (Open Drain Output). This is the data acknowledgement on the
microprocessor interface. This pin is pulled low to signal that the chip has processed the data. A
909 Ω, 1/4 W, resistor is recommended to be used as a pullup.
2-4
3-5
5
7
STi3
6-9
8-11
IC
10
12
VDD
Power Input. Positive Supply.
11
13
F0i
Framing 0-Type (Input). This is the input for the frame synchronization pulse for the 2048 kbit/s
ST-BUS streams. A low on this input causes the internal counter to reset on the next negative
transition of C4i.
12
14
C4i
4.096 MHz Clock (Input). ST-BUS bit cell boundaries lie on the alternate falling edges of this clock.
STi0- ST-BUS Input 0 to 2 (Inputs). These are the inputs for the 2048 kbit/s ST-BUS input streams.
STi2
ST-BUS Input 3 (Input). These are the inputs for the 2048 kbit/s ST-BUS input streams.
Internal Connections. Must be connected to VDD.
13-15 15-17 A0-A2 Address 0 to 2 (Inputs). These are the inputs for the address lines on the microprocessor interface.
16-18 19-21 A3-A5 Address 3 to 5 (Inputs). These are the inputs for the address lines on the microprocessor interface
19
22
DS
Data Strobe (Input). This is the input for the active high data strobe on the microprocessor interface.
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Zarlink Semiconductor Inc.
MT8981D
Data Sheet
Pin Description (continued)
Pin #
40
44
DIP PLCC
Name
Description
20
23
R/W
Read or Write (Input). This is the input for the read/write signal on the microprocessor interface high for read, low for write.
21
24
CS
Chip Select (Input). This is the input for the active low chip select on the microprocessor interface.
22-24 25-27 D7-D5 Data 7 to 5 (Three-state I/O Pins). These are the bidirectional data pins on the microprocessor
interface.
25-29 29-33 D4-D0 Data 4 to 0 (Three-state I/O Pins). These are the bidirectional data pins on the microprocessor
interface.
30
34
31-34 35-38
35
39
VSS
Power Input. Negative Supply (Ground).
IC
Internal Connections. Leave pins disconnected.
STo3 ST-BUS Output 3 (Three-state Outputs). These are the pins for the four 2048 kbit/s ST-BUS output
streams.
36-38 41-43 STo2- ST-BUS Output 2 to 0 (Three-state Outputs). These are the pins for the four 2048 kbit/s ST-BUS
STo0 output streams.
39
44
40
1
ODE Output Drive Enable (Input). If this input is held high, the STo0-STo3 output drivers function
normally. If this input is low, the STo0-STo3 output drivers go into their high impedance state. NB:
Even when ODE is high, channels on the STo0-STo3 outputs can go high impedance under software
control.
IC
Internal Connection. Leave pin disconnected.
Functional Description
In recent years, there has been a trend in telephony towards digital switching, particularly in association with
software control. Simultaneously, there has been a trend in system architectures towards distributed processing or
multi-processor systems.
In accordance with these trends, Zarlink has devised the ST-BUS (Serial Telecom Bus). This bus architecture can
be used both in software-controlled digital voice and data switching, and for interprocessor communications. The
uses in switching and in interprocessor communications are completely integrated to allow for a simple general
purpose architecture appropriate for the systems of the future.
The serial streams of the ST-BUS operate continuously at 2048 kbit/s and are arranged in 125 µs wide frames
which contain 32 8-bit channels. Zarlink manufactures a number of devices which interface to the ST-BUS; a key
device being the MT8981 chip.
The MT8981 can switch data from channels on ST-BUS inputs to channels on ST-BUS outputs, and simultaneously
allows its controlling microprocessor to read channels on ST-BUS inputs or write to channels on ST-BUS outputs
(Message Mode). To the microprocessor, the MT8981 looks like a memory peripheral. The microprocessor can
write to the MT8981 to establish switched connections between input ST-BUS channels and output ST-BUS
channels, or to transmit messages on output ST-BUS channels. By reading from the MT8981, the microprocessor
can receive messages from ST-BUS input channels or check which switched connections have already been
established.
By integrating both switching and interprocessor communications, the MT8981 allows systems to use distributed
processing and to switch voice or data in an ST-BUS architecture.
3
Zarlink Semiconductor Inc.
MT8981D
Data Sheet
Hardware Description
Serial data at 2048 kbit/s is received at the four ST-BUS inputs (STi0 to STi3), and serial data is transmitted at the
four ST-BUS outputs (STo0 to STo3). Each serial input accepts 32 channels of digital data, each channel containing
an 8-bit word which may represent a PCM-encoded analog/voice sample as provided by a codec (e.g., Zarlink’s
MT8964).
This serial input word is converted into parallel data and stored in the 128 X 8 Data Memory. Locations in the Data
Memory are associated with particular channels on particular ST-BUS input streams. These locations can be read
by the microprocessor which controls the chip.
Locations in the Connection Memory, which is split into high and low parts, are associated with particular ST-BUS
output streams. When a channel is due to be transmitted on an ST-BUS output, the data for the channel can either
be switched from an ST-BUS input or it can originate from the microprocessor. If the data is switched from an input,
then the contents of the Connection Memory Low location associated with the output channel is used to address
the Data Memory. This Data Memory address corresponds to the channel on the input ST-BUS stream on which the
data for switching arrived. If the data for the output channel originates from the microprocessor (Message Mode),
then the contents of the Connection Memory Low location associated with the output channel are output directly,
and this data is output repetitively on the channel once every frame until the microprocessor intervenes.
The Connection Memory data is received, via the Control Interface, at D7 to D0. The Control Interface also receives
address information at A5 to A0 and handles the microprocessor control signals CS, DTA, R/W and DS. There are
two parts to any address in the Data Memory or Connection Memory. The higher order bits come from the
Control Register, which may be written to or read from via the Control Interface. The lower order bits come from the
address lines directly.
The Control Register also allows the chip to broadcast messages on all ST-BUS outputs (i.e., to put every channel
into Message Mode), or to split the memory so that reads are from the Data Memory and writes are to the
Connection Memory Low. The Connection Memory High determines whether individual output channels are in
Message Mode, and allows individual output channels to go into a high-impedance state, which enables arrays of
MT8981s to be constructed. It also controls the CSTo pin.
All ST-BUS timing is derived from the two signals C4i and F0i.
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Zarlink Semiconductor Inc.
MT8981D
Data Sheet
A5
A4
A3
A2
A1
A0
HEX ADDRESS
LOCATION
0
1
1
•
•
•
1
X
0
0
•
•
•
1
X
0
0
•
•
•
1
X
0
0
•
•
•
1
X
0
0
•
•
•
1
X
0
1
•
•
•
1
00 - 1F
20
21
•
•
•
3F
Control Register *
Channel 0†
Channel 1†
•
•
•
Channel 31†
* Writing to the Control Register is the only fast transaction.
† Memory and stream are specified by the contents of the Control Register.
Figure 3 - Address Memory Map
Software Control
The address lines on the Control Interface give access to the Control Register directly or, depending on the
contents of the Control Register, to the High or Low sections of the Connection Memory or to the Data Memory.
If address line A5 is low, then the Control Register is addressed regardless of the other address lines (see Fig. 3). If
A5 is high, then the address lines A4-A0 select the memory location corresponding to channel 0-31 for the memory
and stream selected in the Control Register.
The data in the Control Register consists of mode control bits, memory select bits, and stream address bits (see
Fig. 4). The memory select bits allow the Connection Memory High or Low or the Data Memory to be chosen, and
the stream address bits define one of the ST-BUS input or output streams.
Bit 7 of the Control Register allows split memory operation - reads are from the Data Memory and writes are to the
Connection Memory Low.
The other mode control bit, bit 6, puts every output channel on every output stream into active Message Mode; i.e.,
the contents of the Connection Memory Low are output on the ST-BUS output streams once every frame unless the
ODE pin is low. In this mode the chip behaves as if bits 2 and 0 of every Connection Memory High location were 1,
regardless of the actual values.
5
Zarlink Semiconductor Inc.
MT8981D
Mode
Control
Bits
7
Bit
7
5
Memory
Select
Bits
4
3
Name
(unused)
2
Stream
Address
Bits
1
0
Description
Split Memory When 1, all subsequent reads are from the Data Memory and writes are to the Connection Memory
Low, except when the Control Register is accessed again. When 0, the Memory Select bits specify
the memory for subsequent operations. In either case, the Stream Address Bits select the subsection
of the memory which is made available.
6
Message
Mode
5
(unused)
4-3
Memory
Select Bits
2
(unused)
1-0
6
(unused)
Data Sheet
When 1, the contents of the Connection Memory Low are output on the Serial Output streams
except when the ODE pin is low. When 0, the Connection Memory bits for each channel determine
what is output.
0-0 - Not to be used
0-1 - Data Memory (read only from the microprocessor port)
1-0 - Connection Memory Low
1-1 - Connection Memory High
Must be a 0.
Stream
The number expressed in binary notation on these bits refers to the input or output ST-BUS stream
Address Bits which corresponds to the subsection of memory made accessible for subsequent operations.
Figure 4 - Control Register Bits
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Zarlink Semiconductor Inc.
MT8981D
Data Sheet
No Corresponding Memory
- These bits give 0s if read.
7
6
5
Per Channel
Control Bits
4
3
2
1
0
Bit
Name
Description
2
Message
Channel
When 1, the contents of the corresponding location in Connection Memory Low are output on the
location’s channel and stream. When 0, the contents of the corresponding location in Connection
Memory Low act as an address for the Data Memory and so determine the source of the
connection to the location’s channel and stream.
1
Unused
0
Output
Enable
If the ODE pin is high and bit 6 of the Control Register is 0, then this bit enables the output driver
for the location’s channel and stream. This allows individual channels on individual streams to be
made high-impedance, allowing switching matrices to be constructed. A 1 enables the driver and a
0 disables it.
Figure 5 - Connection Memory High Bits
(unused)
7
Stream
Address
Bits
6
Channel
Address
Bits
5
4
3
2
1
0
Bit
Name
Description
7
(Unused)
Must be a 0.
6-5*
Stream
Address
Bits*
The number expressed in binary notation on these 2 bits is the number of the ST-BUS stream for
the source of the connection. Bit 6 is the most significant bit. e.g., if bit 6 is 1, and bit 5 is 0, then
the source of the connection is a channel on STi2.
4-0*
Channel
Address
Bits*
The number expressed in binary notation on these 5 bits is the number of the channel which is the
source of the connection (The ST-BUS stream where the channel lies is defined by bits 6 and 5.).
Bit 4 is the most significant bit. e.g., if bit 4 is 1, bit 3 is 0, bit 2 is 0, bit 1 is 1 and bit 0 is 1, then
the source of the connection is channel 19.
*If bit 2 of the corresponding Connection High location is 1 or if bit 6 of the Control Register is 1, then these entire 8 bits are
output on the channel and stream associated with this location. Otherwise, the bits are used as indicated to define the source
of the connection which is output on the channel and stream associated with this location.
Figure 6 - Connection Memory Low Bits
7
Zarlink Semiconductor Inc.
MT8981D
Data Sheet
If bit 6 of the Control Register is 0, then bits 2 and 0 of each Connection Memory High location function normally
(see Fig. 5). If bit 2 is 1, the associated ST-BUS output channel is in Message Mode; i.e., the byte in the
corresponding Connection Memory Low location is transmitted on the stream at that channel. Otherwise, one of the
bytes received on the serial inputs is transmitted and the contents of the Connection Memory Low define the STBUS input stream and channel where the byte is to be found (see Fig. 6).
If the ODE pin is low, then all serial outputs are high-impedance. If it is high and bit 6 in the Control Register is 1,
then all outputs are active. If the ODE pin is high and bit 6 in the Control Register is 0, then the bit 0 in the
Connection Memory High location enables the output drivers for the corresponding individual ST-BUS output
stream and channel. Bit 0=1 enables the driver and bit 0=0 disables it (see Fig. 5).
Applications
Use in a Simple Digital Switching System
Fig. 7 and 8 show how MT8981s can be used with MT8964s to form a simple digital switching system. Fig. 7 shows
the interface between the MT8981s and the filter/codecs. Fig. 8 shows the position of these components in an
example architecture.
The MT8964 filter/codec in Fig. 7 receives and transmits digitized voice signals on the ST-BUS input DR, and STBUS output DX, respectively. These signals are routed to the ST-BUS inputs and outputs on the top MT8981, which
is used as a digital speech switch.
STo0
STi0
8981 used
as
speech
switch
MT8981
DX
DR
DC
Signalling
Logic
STo0
STi0
8981 used
in message
mode for
control and
signalling
MT8964
Filter/Codec
Line Driver
and
2- to 4Wire
Converter
Line Interface Circuit with 8964 Filter/Codec
MT8981
Figure 7 - Example of Typical Interface between 8981s and 8964s for Simple Digital Switching
System
The MT8964 is controlled by the ST-BUS input DC originating from the bottom MT8981, which generates the
appropriate signals from an output channel in Message Mode. This architecture optimizes the messaging capability
of the line circuit by building signalling logic, e.g., for on-off hook detection, which communicates on an ST-BUS
output. This signalling ST-BUS output is monitored by a microprocessor (not shown) through an ST-BUS input on
the bottom MT8981.
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Zarlink Semiconductor Inc.
MT8981D
Data Sheet
Fig. 8 shows how a simple digital switching system may be designed using the ST-BUS architecture. This is a
private telephone network with 128 extensions which uses a single MT8981 as a speech switch and a second
MT8981 for communication with the line interface circuits.
A larger digital switching system may be designed by cascading a number of MT8981s. Fig. 9 shows how four
MT8981s may be arranged in a non-blocking configuration which can switch any channel on any of the ST-BUS
inputs to any channel on the ST-BUS outputs.
Line Interface Circuit
with Codec (e.g. 8964)
Line 1
4
Speech
Switch
8981
STi0-3
4
STo0-3
•
•
•
Repeated for Lines
2 to 127
STo0-3
Controlling
MicroProcessor
4
STi0-3
•
•
•
Repeated for Lines
2 to 127
4
Control &
Signalling
8981
Line Interface Circuit
with Codec (e.g. 8964)
Line 128
Figure 8 - Example Architecture of a Simple Digital Switching System
8981
#1
IN 0/3
STi0/3 STo0/3
OUT 0/3
8981
#2
STi0/3 STo0/3
OUT 4/7
8981
#3
IN 4/7
STi0/3 STo0/3
8981
#4
STi0/3 STo0/3
Figure 9 - Four 8981s Arranged in a Non-Blocking 8 x 8 Configuration
9
Zarlink Semiconductor Inc.
MT8981D
Data Sheet
Application Circuit with 6802 Processor
Fig. 10 shows an example of a complete circuit which may be used to evaluate the chip.
For convenience, a 4 MHz crystal oscillator has been used rather than a 4.096 MHz clock, as both are within the
limits of the chip’s specifications. The RC delay used with the 393 counters ensures a sufficient hold time for the
FP signal, but the values used may have to be changed if faster 393 counters become available.
The chip is shown as memory mapped into the MEK6802D3 system. Chip addresses 00-3F correspond to
processor addresses 2000-203F. Delay through the address decoder requires the VMA signal to be used twice to
remove glitches. The MEK6802D3 board uses a 10 KΩ pullup on the MR pin, which would have to be incorporated
into the circuit if the board was replaced by a processor.
10
Zarlink Semiconductor Inc.
MT8981D
Data Sheet
A15
A14
A13
0V
0V
VMA
D7-D0
A15-A0
MEK6802D3
System
R/W
1
2
3
4
5
6
7
8
0V
MD
74
HCT
138
16
15
14
13
12
11
10
9
5V
16
15
14
13
12
11
10
9
5V
16
15
14
13
12
11
10
9
5V
16
15
14
13
12
11
10
9
5V
MR
VMA
1
2
3
4
5
6
7
8
A12
A11
A10
0V
0V
E
0V
909 Ω,
1/4W
5V
5V
DTA
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
VDD
F0i
C4i
A0
A1
A2
A3
A4
A5
DS
R/W
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MT
8980
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
CSTo
ODE
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
VSS
D0
D1
D2
D3
D4
D5
D6
D7
CS
5V
A9
A8
A7
0V
0V
0V
1
2
3
4
5
6
7
8
0V
A6
VMA
0V
0V
0V
1
2
3
4
5
6
7
8
0V
C4i
0V
0V
1
2
3
4
5
6
7
SN
74
HCT
393
14
13
12
11
10
9
8
5V
0V
DTA
CS
0V
C4i
0V
F0i
0V
510 Ω
0V
0V
0V
1
2
3
4
5
6
7
SN
74
HCT
393
14
13
12
11
10
9
8
5V
MD
74
HCT
138
1
2
MD
3
74
4 HCT
5 240
6
7
8
9
10
100pF
20
19
18
17
16
15
14
13
12
11
4 MHz
2MΩ
Figure 10 - Application Circuit with 6802
11
Zarlink Semiconductor Inc.
MD
74
HCT
138
MD
74
HCT
138
5V
0V
MR
5V
MT8981D
Data Sheet
Absolute Maximum Ratings*
Parameter
Symbol
Min.
Max.
Units
-0.3
7
V
1
VDD - VSS
2
Voltage on Digital Inputs
VI
VSS-0.3
VDD+0.3
V
3
Voltage on Digital Outputs
VO
VSS-0.3
VDD+0.3
V
4
Current at Digital Outputs
IO
40
mA
5
Storage Temperature
TS
+150
°C
6
Package Power Dissipation
PD
2
W
-65
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
1
Operating Temperature
TOP
-40
+85
°C
2
Positive Supply
VDD
4.75
5.25
V
3
Input Voltage
VI
0
VDD
V
Test Conditions
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
1
2
3
4
5
6
7
8
9
10
11
‡
I
N
P
U
T
S
O
U
T
P
U
T
S
Sym.
Min.
Typ.‡
Max.
Units
6
10
mA
Supply Current
IDD
Input High Voltage
VIH
Input Low Voltage
VIL
0.8
V
Input Leakage
IIL
5
µA
Input Pin Capacitance
CI
Output High Voltage
VOH
2.4
Output High Current
IOH
10
Output Low Voltage
VOL
Output Low Current
IOL
High Impedance Leakage
IOZ
2.0
Outputs unloaded
V
8
V
15
mA
10
5
V
Zarlink Semiconductor Inc.
IOH = 10 mA
Sourcing. VOH=2.4V
IOL = 5 mA
mA
Sinking. VOL = 0.4V
µA
VO between VSS and VDD
Output Pin Capacitance
CO
8
pF
Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
12
VI between VSS and VDD
pF
0.4
5
Test Conditions
MT8981D
Data Sheet
VDD
Test Point
S1 is open circuit except
when testing output levels
or high impedance states.
RL
Output
Pin
S1
S2 is switched to VDD or
V SS when testing output
levels or high impedance
states.
S2
CL
VSS
VSS
Figure 11 - Output Test Load
AC Electrical Characteristics† - Clock Timing (Figures 12 and 13)
Sym.
Min.
Typ.‡
Max.
Units
Clock Period*
tCLK
220
244
300
ns
Clock Width High
tCH
95
122
150
ns
Clock Width Low
tCL
110
122
150
ns
Clock Transition Time
tCTT
Frame Pulse Setup Time
tFPS
20
200
ns
Frame Pulse Hold Time
tFPH
0.020
50
µs
Frame Pulse Width
tFPW
Characteristics
1
2
I
N
P
U
T
S
3
4
5
6
7
20
ns
244
ns
† Timing is over recommended temperature & power supply voltages
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* Contents of Connection Memory are not lost if the clock stops, however, ST-BUS outputs go into the high impedance state.
NB: Frame Pulse is repeated every 512 cycles of C4i.
C4i
F0i
BIT
CELLS
Channel 31
Bit o
Channel 0
Bit 7
Figure 12 - Frame Alignment
13
Zarlink Semiconductor Inc.
Test Conditions
MT8981D
Data Sheet
tCLK
tCL
tCH
tCTT
2.0V
C4i
0.8V
tCHL
tFPH
F0i
tCTT
tFPS
tFPH
tFPS
2.0V
0.8V
tFPW
Figure 13 - Clock Timing
AC Electrical Characteristics† - Serial Streams (Figures 11, 14, 15 and 16)
Sym.
Min.
Typ.‡
Max.
Units
STo0/3 Delay - Active to High Z
tSAZ
20
50
80
ns
RL=1 KΩ*, CL=150 pF
STo0/3 Delay - High Z to Active
tSZA
25
60
125
ns
CL=150 pF
STo0/3 Delay - Active to Active
tSAA
30
65
125
ns
CL=150 pF
STo0/3 Hold Time
tSOH
25
45
ns
CL=150 pF
Output Driver Enable Delay
tOED
ns
RL=1 KΩ*, CL=150 pF
External Control Hold Time
tXCH
ns
CL=150 pF
External Control Delay
tXCD
75
110
ns
CL=150 pF
Serial Input Setup Time
tSIS
-40
-20
ns
Serial Input Hold Time
tSIH
Characteristics
1
2
3
4
5
6
O
U
T
P
U
T
S
7
8
9
I
N
45
0
125
50
90
Test Conditions
ns
† Timing is over recommended temperature & power supply voltages
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
14
Zarlink Semiconductor Inc.
MT8981D
Data Sheet
Bit Cell Boundary
2.0V
C4i
0.8V
tSOH
STo0 2.4V
to
STo3 0.4V
*
tSAZ
STo0 2.4V
to
STo3 0.4V
*
tSZA
tSOH
STo0 2.4V
to
STo3 0.4V
tSAA
Figure 14 - Serial Outputs and External Control
2.0V
ODE
0.8V
STo0 2.4V
to
STo3 0.4V
*
*
tOED
Figure 15 - Output Driver Enable
15
Zarlink Semiconductor Inc.
MT8981D
Data Sheet
Bit Cell Boundaries
2.0V
C4i
0.8V
tSIH
STi0 2.0V
to
STi3 0.8V
tSIS
Figure 16 - Serial Inputs
AC Electrical Characteristics† - Processor Bus (Figures 11 and 17)
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
1
Chip Select Setup Time
tCSS
20
0
ns
2
Read/Write Setup Time
tRWS
25
5
ns
3
Address Setup Time
tADS
25
5
ns
4
Acknowledgement Delay
Fast
tAKD
Slow
tAKD
2.7
20
5
Fast Write Data Setup Time
tFWS
6
Slow Write Data Delay
tSWD
7
Read Data Setup Time
tRDS
8
Data Hold Time
40
tDHT
20
Write
tDHT
20
100
ns
CL=150 pF
7.2
cycles
C4i cycles1
ns
2.0
Read
Test Conditions
1.7
cycles
C4i cycles1
0.5
cycles
C4i cycles1, CL= 150 pF
ns
RL=1 KΩ*, CL=150 pF
10
50
ns
90
ns
9
Read Data To High Impedance
tRDZ
10
Chip Select Hold Time
tCSH
0
ns
11
Read/Write Hold Time
tRWH
0
ns
12
Address Hold Time
tADH
0
ns
13
Acknowledgement Hold Time
tAKH
10
60
80
ns
RL=1 KΩ*, CL=150 pF
RL=1 KΩ*, CL=150 pF
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
Note 1: Processor accesses are dependent on the C4i clock, and so some timings are expressed as multiples of the C4i clock period.
16
Zarlink Semiconductor Inc.
MT8981D
Data Sheet
2.0V
DS
0.8V
2.0V
CS
0.8V
tCSS
tCSH
tRWS
tRWH
2.0V
R/W
A5
to
A0
0.8V
2.0V
0.8V
tADS
2.4V
DTA
0.4V
tADH
tAKD
tAKH
*
*
tRDS
D7
to
D0
2.4V (Read) 2.0V (Write)
0.8V (Read 0.8V (Write)
tDHT
*
*
tFWS
tSWD
Figure 17 - Processor Bus
17
Zarlink Semiconductor Inc.
tRDZ
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