ZARLINK MVTX2804

MVTX2804
8-Port 1000 Mbps Ethernet
Distributed Switch
Data Sheet
Features
•
October 2003
8 Gigabit Ports with GMII and PCS interface
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Ordering Information
Gigabit Port can also support 100/10 Mbps MII
interface
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Provide Hot plug support for GMII/PCS module
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2 Gigabit ports can be aggregated into 2Gbps
Stacking port working with VTX2600 in stacking
mode
MVTX2804AG
596 Pin HSBGA
-40°C to +85°C
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Support IP Multicast with IGMP snooping up to
64K groups.
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Traffic Classification
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Classify traffic into 8 transmission priorities per
port
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High Performance Layer 2 Packet Forwarding
(11.904M packets per second) and Filtering at
Full-Wire Speed
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Maximum throughput is 8 Gbps non-blocking
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Centralized shared-memory architecture
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Supports Delay Bounded, Strict Priority, and WFQ
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Consists of two Memory Domains at 133 MHz
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Provides 2 level dropping precedence with WRED
mechanism
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Frame Buffer Domain: Two banks of ZBT-SRAM
with 2M/4MB total
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Switch Database Domain with 256K/512K
SRAM
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Up to 64K MAC addresses to provide large node
aggregation in wiring closet switches
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Provides Port based and ID Tagged VLAN
(IEEE802.1Q) up to 4K VLAN
Frame Data Buffer A
ZBT-SRAM (1M/2MB)
VTX2804
-
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User controlled thresholds for WRED
Classification based on layer 2, 3 markings
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VLAN Priority field in VLAN tagged frame
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DS/TOS field in IP packet
The precedence of above two classifications can
be programmable
SRAM 256/512K
SW Database
MAC Table
Frame Data Buffer B
ZBT-SRAM (1M/2MB)
32bit
64bit
64bit
FDB Interface
SDB Interface
LED
Search
Engine
NM
Database
Frame
Engine
Scheduler
Management
Module
GMII
/PCS
Port 0
GMII
/PCS
Port 1
GMII
/PCS
Port 2
GMII
/PCS
Port 3
GMII
/PCS
Port 4
GMII
/PCS
Port 5
GMII
/PCS
Port 6
GMII
/PCS
Port 7
16/8bitBus/
Serial
Figure 1 - MVTX2804AG Functional Block Diagram
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Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.
CPU
MVTX2804
Data Sheet
QoS Support
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Supports IEEE 802.1p/Q Quality of Service with
8 Priority
Buffer Management: reserve buffers on per class
and per port basis
Port-based Priority: VLAN Priority with Tagged
frame can be overwritten by the priority of PVID
QoS features can be configured on a per port
basis
Packet Filtering and Port Security
Static addressing filtering for source and/or
destination MAC address
Static learned MAC addresses will not be aged
out
Secure mode per port: Prevent learning for port
in a secure mode
Support per MAC per Port filtering
Full Duplex Ethernet IEEE 802.3x Flow Control
Provides Ethernet Multicast and Broadcast
Control
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4 Port Trunking groups, 8 ports per group
(Trunking can be based on source MAC and/or
destination MAC and source port)
LED signals provided by a serial or parallel
interface
CPU interface supports 16/8-bit CPU bus in
managed mode and a synchronous Serial Interface
and I2C interface in unmanaged mode
SNMP/RMON support with CPU
Built-in MIB counter
Spanning tree with CPU
Multiple Spanning trees (Per Spanning Tree Per
VLAN)
Hardware auto-negotiation through serial
management interface (MDIO) for Gigabit Ethernet
ports, supports 10/100/1000 Mbps
BIST for internal and external SRAM-ZBT
I2C EEPROM or synchronous serial port for
configuration
Packaged in 596-pin BGA
Description
The MVTX2800AG family is a group of 8-port 1000 Mbps non-blocking Ethernet switch chips with on-chip address
memory. A single chip provides a maximum of eight 1000 Mbps ports and a dedicated CPU interface with a 16/8-bit
bus for managed and unmanaged switch applications. The VTX2800 family consists of the following four products:
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VTX2804 8 Gigabit ports Managed
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VTX2803 8 Gigabit ports Unmanaged
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VTX2802 4 Gigabit ports Managed
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VTX2801 4 Gigabit ports Unmanaged
The MVTX2804AG supports up to 64K MAC addresses to aggregate traffic from multiple wiring closet stacks. The
centralized shared-memory architecture allows a very high performance packet-forwarding rate of 11.904M packets
per second at full wire speed. The chip is optimized to provide a low-cost, high performance workgroup, and wiring
closet, layer 2 switching solution with 8 Gigabit Ethernet ports.
Two Frame Buffer Memory domains utilize cost effective, high-performance ZBT-SRAM with aggregated bandwidth
of 16Gbps to support full wire speed on all external ports simultaneously.
With Strict priority, Delay Bounded, and WRR transmission scheduling, plus WRED memory congestion scheme,
the chip provides powerful QoS functions for convergent network multimedia and mission-critical applications. The
chip provides 8 transmission priorities and 2 level drop precedence. Traffic is assigned its transmission priority and
dropping precedence based on the frame VLAN Tag priority or DS/TOS fields in IP packets.
IP multicast snooping provides up to 64k simultaneous IP Multicast groups. With 4K IEEE 802.1Q VLANs, the
MVTX2804AG provides the ability to logically group users to control multicast traffic.
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Zarlink Semiconductor Inc.
MVTX2804
Data Sheet
The MVTX2804AG supports port trunking/load sharing on the 1000 Mbps ports with fail-over capability. The port
trunking/load sharing can be used to group ports between interlinked switches to increase the effective network
bandwidth.
In full-duplex mode, IEEE 802.3x flow control is provided. The Physical Coding Sublayer (PCS) is integrated onchip to provide a direct 10-bit GMII interface, or the PCS can be bypassed to provide an interface to existing fiberbased Gigabit Ethernet transceivers.
Statistical information for Etherstat SNMP and Remote Monitoring Management Information Base (RMON MIB) are
collected independently for each of the eight ports. Access to these statistical counter/registers is provided via the
CPU interface. SNMP Management frames can be received and transmitted via the CPU interface, creating a
complete network management solution.
The MVTX2804AG is fabricated using 0.25mm technology. Inputs, however, are 3.3V tolerant and the outputs are
capable of directly interfacing to LVTTL levels. The MVTX2804AG is packaged in a 596-pin Ball Grid Array
package.
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Zarlink Semiconductor Inc.
MVTX2804
Data Sheet
Table of Contents
1.0 Block Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.1 Frame Data Buffer (FDB) Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.2 Switch Database (SDB) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.3 GMII/PCS MAC Module (GMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.4 CPU Interface Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.5 Management Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.6 Frame Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.7 Search Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.8 LED Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.9 Internal Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.0 System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1 Management and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2 Managed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3 Register Configuration, Frame Transmission, and Frame Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.1 Ethernet Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.2 Control Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4 Unmanaged Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.5 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.5.1 Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.5.2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.5.3 Data Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.5.4 Acknowledgment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.5.5 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.5.6 Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.6 Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.6.1 Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.6.2 Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.0 Data Forwarding Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1 Unicast Data Frame Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2 Multicast Data Frame Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3 Frame Forwarding To and From CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.0 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2 Detailed Memory Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.0 Search Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1 Search Engine Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2 Basic Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3 Search, Learning, and Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3.1 MAC Search. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3.2 Learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3.3 Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3.4 Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3.5 VLAN Port Association Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.0 Frame Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1 Data Forwarding Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.2 Frame Engine Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.2.1 FCB Manager. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.2.2 Rx Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.2.3 RxDMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.2.4 TxQ Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.3 Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.4 TxDMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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Zarlink Semiconductor Inc.
MVTX2804
Data Sheet
Table of Contents
7.0 Quality of Service and Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.1 Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.2 Four QoS Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.3 Delay Bound . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.4 Strict Priority and Best Effort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.5 Weighted Fair Queuing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.6 Shaper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.7 WRED Drop Threshold Management Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.8 Buffer Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.8.1 Dropping When Buffers Are Scarce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.9.1 Unicast Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.9.2 Multicast Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.10 Mapping to IETF Diffserv Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.0 Port Trunking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.1 Features and Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.2 Unicast Packet Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.3 Multicast Packet Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.4 Preventing Multicast Packets from Looping Back to the Source Trunk. . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.0 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.2 Serial Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.3 Parallel Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.4 LED Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10.0 Hardware Statistics Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
10.1 Hardware Statistics Counters List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
10.2 IEEE 802.3 HUB Management (RFC 1213) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
10.2.1 Event Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
10.2.1.1 READABLEOCTET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
10.2.1.2 READABLEFRAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
10.2.1.3 FCSERRORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
10.2.1.4 ALIGNMENTERRORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
10.2.1.5 FRAMETOOLONGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
10.2.1.6 SHORTEVENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10.2.1.7 RUNTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10.2.1.8 COLLISIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10.2.1.9 LATEEVENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10.2.1.10 VERYLONGEVENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10.2.1.11 DATARATEMISATCHES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10.2.1.12 AUTOPARTITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10.2.1.13 TOTALERRORS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.3 IEEE - 802.1 Bridge Management (RFC 1286) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.3.0.1 Event Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.3.0.3 OUTFRAMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.3.0.4 INDISCARDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.3.0.5 DELAYEXCEEDEDDISCARDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.3.0.6 MTUEXCEEDEDDISCARDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.4 RMON - Ethernet Statistic Group (RFC 1757) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.4.1 Event Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.4.1.1 DROP EVENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.4.1.2 OCTETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.4.1.3 BROADCASTPKTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.4.1.4 MULTICASTPKTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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10.4.1.5 CRCALIGNERRORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.4.1.6 UNDERSIZEPKTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.4.1.7 OVERSIZEPKTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.4.1.8 FRAGMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.4.1.9 JABBERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
10.4.1.10 COLLISIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
10.4.1.11 PACKET COUNT FOR DIFFERENT SIZE GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
11.0 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
11.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
11.2 Directly Accessed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11.2.1 INDEX_REG0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11.2.2 INDEX_REG1 (only needed for CPU 8-bit bus mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11.2.3 DATA_FRAME_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11.2.4 CONTROL_FRAME_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11.2.5 COMMAND & STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
11.2.6 Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
11.2.7 Control Frame Buffer1 Access Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.2.8 Control Frame Buffer2 Access Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.3 Group 0 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.3.1 MAC Ports Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.3.1.1 ECR1PN: PORT N CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.3.1.2 ECR2PN: PORT N CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.3.1.3 ECRMISC1 - CPU PORT CONTROL REGISTER MISC1 . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11.3.1.4 ECRMISC2 - CPU PORT CONTROL REGISTER MISC2 . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11.3.1.5 GGCONTROL 0- EXTRA GIGA PORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
11.3.1.6 GGCONTROL 1- EXTRA GIGA PORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
11.3.1.7 GGCONTROL 2- EXTRA GIGA PORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
11.3.1.8 GGCONTROL 3- EXTRA GIGA PORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
11.4 Group 1 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
11.4.1 VLAN Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
11.4.1.1 AVTCL - VLAN TYPE CODE REGISTER LOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
11.4.1.2 AVTCH - VLAN TYPE CODE REGISTER HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
11.4.1.3 PVMAP00_0 - PORT 00 CONFIGURATION REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . 58
11.4.1.4 PVMAP00_1 - PORT 00 CONFIGURATION REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . 58
11.4.1.5 PVMAP00_3 - PORT 00 CONFIGURATION REGISTER 3 . . . . . . . . . . . . . . . . . . . . . . . . . 59
11.5 Port VLAN Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
11.5.1 PVMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
11.6 Group 2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
11.6.1 Port Trunking Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
11.6.1.1 TRUNK0 - TRUNK GROUP 0 MEMBER (MANAGED MODE ONLY) . . . . . . . . . . . . . . . . . 61
11.6.1.2 TRUNK1 - TRUNK GROUP 1 MEMBER (MANAGED MODE ONLY) . . . . . . . . . . . . . . . . . 61
11.6.1.3 TRUNK2- TRUNK GROUP 2 MEMBER (MANAGED MODE ONLY) . . . . . . . . . . . . . . . . . 61
11.6.1.4 TRUNK3- TRUNK GROUP 3 MEMBER (MANAGED MODE ONLY) . . . . . . . . . . . . . . . . . 62
11.6.1.5 TRUNK_HASH_MODE - TRUNK HASH MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
11.6.1.6 TRUNK0_MODE - TRUNK GROUP 0 MODE (UNMANAGED MODE) . . . . . . . . . . . . . . . . 62
11.6.1.7 TRUNK0_HASH0 - TRUNK GROUP 0 HASH RESULT 0,1,2 DESTINATION PORT
NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
11.6.1.8 TRUNK0_HASH1 - TRUNK GROUP 0 HASH RESULT 2,3,4,5 DESTINATION PORT
NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
11.6.1.9 TRUNK0_HASH2 - TRUNK GROUP 0 HASH RESULT 5,6,7 DESTINATION PORT
NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
11.6.1.10 TRUNK0_HASH3 - TRUNK GROUP 0 HASH RESULT 8,9,10 DESTINATION PORT
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NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
11.6.1.11 TRUNK0_HASH4 - TRUNK GROUP 0 HASH RESULT 10,11,12,13 DESTINATION PORT
NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
11.6.1.12 TRUNK0_HASH5 - TRUNK GROUP 0 HASH RESULT 13,14,15 DESTINATION PORT
NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
11.6.1.13 TRUNK1_MODE - TRUNK GROUP 1 MODE (UNMANAGED MODE) . . . . . . . . . . . . . . . 64
11.6.1.14 TRUNK1_HASH0 - TRUNK GROUP 1 HASH RESULT 0, 1, 2 DESTINATION PORT
NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
11.6.1.15 TRUNK1_HASH1 - TRUNK GROUP 1 HASH RESULT 2, 3, 4, 5 DESTINATION PORT
NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
11.6.1.16 TRUNK1_HASH2 - TRUNK GROUP 1 HASH RESULT 5, 6, 7 DESTINATION PORT
NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
11.6.1.17 TRUNK1_HASH3 - TRUNK GROUP 1 HASH RESULT 8, 9, 10 DESTINATION PORT
NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
11.6.1.18 TRUNK1_HASH4- TRUNK GROUP 1 HASH RESULT 11, 12, 13 DESTINATION PORT
NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
11.6.1.19 TRUNK1_HASH5 - TRUNK GROUP 1 HASH RESULT 13, 14, 15 DESTINATION PORT
NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
11.6.1.20 TRUNK2_HASH0 - TRUNK GROUP 2 HASH RESULT 0, 1, 2 DESTINATION PORT
NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
11.6.1.21 TRUNK2_HASH1 - TRUNK GROUP 2 HASH RESULT 2, 3, 4, 5 DESTINATION PORT
NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
11.6.1.22 TRUNK2_HASH2 - TRUNK GROUP 2 HASH RESULT 5, 6, 7 DESTINATION PORT
NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
11.6.1.23 TRUNK2_HASH3 - TRUNK GROUP 2 HASH RESULT 8, 9, 10 DESTINATION PORT
NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
11.6.1.24 TRUNK0_HASH3 - TRUNK GROUP 0 HASH RESULT 8,9,10 DESTINATION PORT
NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
11.6.1.25 TRUNK0_HASH4 - TRUNK GROUP 0 HASH RESULT 10,11,12,13 DESTINATION PORT
NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
11.6.1.26 TRUNK0_HASH5 - TRUNK GROUP 0 HASH RESULT 13,14,15 DESTINATION PORT
NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
11.6.1.27 TRUNK1_MODE - TRUNK GROUP 1 MODE (UNMANAGED MODE) . . . . . . . . . . . . . . . 67
11.6.1.28 TRUNK1_HASH0 - TRUNK GROUP 1 HASH RESULT 0, 1, 2 DESTINATION PORT
NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
11.6.1.29 TRUNK1_HASH1 - TRUNK GROUP 1 HASH RESULT 2, 3, 4, 5 DESTINATION PORT
NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
11.6.1.30 TRUNK1_HASH2 - TRUNK GROUP 1 HASH RESULT 5, 6, 7 DESTINATION PORT
NUMBER68
11.6.1.31 TRUNK1_HASH3 - TRUNK GROUP 1 HASH RESULT 8, 9, 10 DESTINATION PORT
NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
11.6.1.32 TRUNK1_HASH4- TRUNK GROUP 1 HASH RESULT 11, 12, 13 DESTINATION PORT
NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
11.6.1.33 TRUNK1_HASH5 - TRUNK GROUP 1 HASH RESULT 13, 14, 15 DESTINATION PORT
NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
11.6.1.34 TRUNK2_HASH0 - TRUNK GROUP 2 HASH RESULT 0, 1, 2 DESTINATION PORT
NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
11.6.1.35 TRUNK2_HASH1 - TRUNK GROUP 2 HASH RESULT 2, 3, 4, 5 DESTINATION PORT
NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
11.6.1.36 TRUNK2_HASH2 - TRUNK GROUP 2 HASH RESULT 5, 6, 7 DESTINATION PORT
NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
11.6.1.37 TRUNK2_HASH3 - TRUNK GROUP 2 HASH RESULT 8, 9, 10 DESTINATION PORT
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NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
11.6.1.38 TRUNK2_HASH4 - TRUNK GROUP 2 HASH RESULT 10, 11, 12, 13 DESTINATION PORT
NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
11.6.1.39 TRUNK2_HASH5 - TRUNK GROUP 2 HASH RESULT 13, 14, 15 DESTINATION PORT
NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
11.6.1.40 TRUNK3_HASH0 - TRUNK GROUP 3 HASH RESULT 0, 1, 2 DESTINATION PORT
NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
11.6.1.41 TRUNK3_HASH1 - TRUNK GROUP 3 HASH RESULT 2, 3, 4, 5 DESTINATION PORT
NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
11.6.1.42 TRUNK3_HASH2 - TRUNK GROUP 3 HASH RESULT 5, 6, 7 DESTINATION PORT
NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
11.6.1.43 TRUNK3_HASH3 - TRUNK GROUP 3 HASH RESULT 8, 9, 10 DESTINATION PORT
NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
11.6.1.44 TRUNK3_HASH4 - TRUNK GROUP 3 HASH RESULT 10, 11, 12, 13 DESTINATION PORT
NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
11.6.1.45 TRUNK3_HASH5 - TRUNK GROUP 3 HASH RESULT 13, 14, 15 DESTINATION PORT
NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
11.6.2 Multicast Hash Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
11.6.2.1 MULTICAST_HASH00 - MULTICAST HASH RESULT0 MASK BYTE [7:0] . . . . . . . . . . . . 71
11.6.2.2 MULTICAST_HASH01 - MULTICAST HASH RESULT1 MASK BYTE [7:0] . . . . . . . . . . . . 71
11.6.2.3 MULTICAST_HASH02 - MULTICAST HASH RESULT2 MASK BYTE [7:0] . . . . . . . . . . . . 71
11.6.2.4 MULTICAST_HASH03 - MULTICAST HASH RESULT3 MASK BYTE [7:0] . . . . . . . . . . . . 72
11.6.2.5 MULTICAST_HASH04 - MULTICAST HASH RESULT4 MASK BYTE [7:0] . . . . . . . . . . . . 72
11.6.2.6 MULTICAST_HASH05 - MULTICAST HASH RESULT5 MASK BYTE [7:0] . . . . . . . . . . . . 72
11.6.2.7 MULTICAST_HASH06 - MULTICAST HASH RESULT6 MASK BYTE [7:0] . . . . . . . . . . . . 72
11.6.2.8 MULTICAST_HASH07 - MULTICAST HASH RESULT7 MASK BYTE [7:0] . . . . . . . . . . . . 72
11.6.2.9 MULTICAST_HASH08 - MULTICAST HASH RESULT8 MASK BYTE [7:0] . . . . . . . . . . . . 72
11.6.2.10 MULTICAST_HASH09 - MULTICAST HASH RESULT9 MASK BYTE [7:0] . . . . . . . . . . . 72
11.6.2.11 MULTICAST_HASH10 - MULTICAST HASH RESULT10 MASK BYTE [7:0] . . . . . . . . . . 72
11.6.2.12 MULTICAST_HASH11 - MULTICAST HASH RESULT11 MASK BYTE [7:0] . . . . . . . . . . 73
11.6.2.13 MULTICAST_HASH12 - MULTICAST HASH RESULT12 MASK BYTE [7:0] . . . . . . . . . . 73
11.6.2.14 MULTICAST_HASH13 - MULTICAST HASH RESULT13 MASK BYTE [7:0] . . . . . . . . . . 73
11.6.2.15 MULTICAST_HASH14 - MULTICAST HASH RESULT14 MASK BYTE [7:0] . . . . . . . . . . 73
11.6.2.16 MULTICAST_HASH15 - MULTICAST HASH RESULT15 MASK BYTE [7:0] . . . . . . . . . . 73
11.6.2.17 MULTICAST_HASHML - MULTICAST HASH BIT[8] FOR RESULT7-0 . . . . . . . . . . . . . . 73
11.6.2.18 MULTICAST_HASHML - MULTICAST HASH BIT[8] FOR RESULT 15-8 . . . . . . . . . . . . . 73
11.7 Group 3 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
11.7.1 CPU Port Configuration Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
11.7.1.1 MAC0 - CPU MAC ADDRESS BYTE 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
11.7.1.2 MAC1 - CPU MAC ADDRESS BYTE 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
11.7.1.3 MAC2 - CPU MAC ADDRESS BYTE 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
11.7.1.4 MAC3 - CPU MAC ADDRESS BYTE 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
11.7.1.5 MAC4 - CPU MAC ADDRESS BYTE 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
11.7.1.6 MAC5 - CPU MAC ADDRESS BYTE 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
11.7.1.7 INT_MASK0 - INTERRUPT MASK 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
11.7.1.8 INT_MASK1 - INTERRUPT MASK 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
11.7.1.9 INT_STATUS0 - MASKED INTERRUPT STATUS REGISTER0 . . . . . . . . . . . . . . . . . . . . . 75
11.7.1.10 INT_STATUS1 - MASKED INTERRUPT STATUS REGISTER1 . . . . . . . . . . . . . . . . . . . . 75
11.7.1.11 INTP_MASK0 - INTERRUPT MASK FOR MAC PORT 0,1 . . . . . . . . . . . . . . . . . . . . . . . . 76
11.7.1.12 INTP_MASK1 - INTERRUPT MASK FOR MAC PORT 2,3 . . . . . . . . . . . . . . . . . . . . . . . . 76
11.7.1.13 INTP_MASK4 - INTERRUPT MASK FOR MAC PORT 4,5 . . . . . . . . . . . . . . . . . . . . . . . . 76
11.7.1.14 INTP_MASK5 - INTERRUPT MASK FOR MAC PORT 6,7 . . . . . . . . . . . . . . . . . . . . . . . . 77
8
Zarlink Semiconductor Inc.
MVTX2804
Data Sheet
Table of Contents
11.7.2 RQS - Receive Queue Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
11.7.3 RQSS - Receive Queue Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
11.7.4 TX_AGE - Tx Queue Aging timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
11.8 Group 4 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
11.8.1 Search Engine Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
11.8.1.1 AGETIME_LOW - MAC ADDRESS AGING TIME LOW . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
11.8.1.2 AGETIME_HIGH -MAC ADDRESS AGING TIME HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
11.8.1.3 V_AGETIME - VLAN TO PORT AGING TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
11.8.1.4 SE_OPMODE - SEARCH ENGINE OPERATION MODE . . . . . . . . . . . . . . . . . . . . . . . . . . 79
11.8.1.5 SCAN - SCAN CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
11.9 Group 5 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
11.9.1 Buffer Control/QOS Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
11.9.1.1 FCBAT - FCB AGING TIMER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
11.9.1.2 QOSC - QOS CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
11.9.1.3 FCR - FLOODING CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
11.9.1.4 AVPML - VLAN PRIORITY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
11.9.1.5 AVPMM - VLAN PRIORITY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
11.9.1.6 AVPMH - VLAN PRIORITY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
11.9.1.7 TOSPML - TOS PRIORITY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
11.9.1.8 TOSPMM - TOS PRIORITY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
11.9.1.9 TOSPMH - TOS PRIORITY MAP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
11.9.1.10 AVDM - VLAN DISCARD MAP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
11.9.1.11 TOSDML - TOS DISCARD MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
11.9.2 BMRC - Broadcast/Multicast Rate Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
11.9.3 UCC - Unicast Congestion Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
11.9.4 MCC - Multicast Congestion Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
11.9.5 PRG - Port Reservation for Giga ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
11.9.6 FCB Reservation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
11.9.6.1 SFCB - SHARE FCB SIZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
11.9.6.2 C2RS - CLASS 2 RESERVED SIZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11.9.6.3 C3RS - CLASS 3 RESERVED SIZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11.9.6.4 C4RS - CLASS 4 RESERVED SIZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11.9.6.5 C5RS - CLASS 5 RESERVED SIZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11.9.6.6 C6RS - CLASS 6 RESERVED SIZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.9.6.7 C7RS - CLASS 7 RESERVED SIZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.9.7 Classes Byte Gigabit Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.9.7.1 QOSC00 - BYTE_C2_G0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.9.7.2 QOSC01 - BYTE_C3_G0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.9.7.3 QOSC02 - BYTE_C4_G0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.9.7.4 QOSC03 - BYTE_C5_G0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.9.7.5 QOSC04 - BYTE_C6_G0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.9.7.6 QOSC05 - BYTE_C7_G0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.9.8 Classes Byte Gigabit Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.9.8.1 QOSC06 - BYTE_C2_G1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.9.8.2 QOSC07 - BYTE_C3_G1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.9.8.3 QOSC08 - BYTE_C4_G1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.9.8.4 QOSC09 - BYTE_C5_G1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
11.9.8.5 QOSC0A - BYTE_C6_G1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
11.9.8.6 QOSC0B - BYTE_C7_G1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
11.9.9 Classes Byte Gigabit Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
11.9.9.1 QOSC0C - BYTE_C2_G2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
11.9.9.2 QOSC0D - BYTE_C3_G2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
9
Zarlink Semiconductor Inc.
MVTX2804
Data Sheet
Table of Contents
11.9.9.3 QOSC0E - BYTE_C4_G2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
11.9.9.4 QOSC0F - BYTE_C5_G2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
11.9.9.5 QOSC10 - BYTE_C6_G2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
11.9.9.6 QOSC11 - BYTE_C7_G2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
11.9.10 Classes Byte Gigabit Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
11.9.10.1 QOSC12 - BYTE_C2_G3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
11.9.10.2 QOSC13 - BYTE_C3_G3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
11.9.10.3 QOSC14 - BYTE_C4_G3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
11.9.10.4 QOSC15 - BYTE_C5_G3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
11.9.10.5 QOSC16 - BYTE_C6_G3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
11.9.10.6 QOSC17 - BYTE_C7_G3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
11.9.11 Classes Byte Gigabit Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
11.9.11.1 QOSC18 - BYTE_C2_G4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
11.9.11.2 QOSC019 - BYTE_C3_G4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
11.9.11.3 QOSC1A - BYTE_C4_G4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
11.9.11.4 QOSC1B - BYTE_C5_G4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
11.9.11.5 QOSC1C - BYTE_C6_G4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
11.9.11.6 QOSC1D- BYTE_C7_G4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
11.9.12 Classes Byte Gigabit Port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
11.9.12.1 QOSC1E- BYTE_C2_G5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
11.9.12.2 QOSC1F - BYTE_C3_G5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
11.9.12.3 QOSC20 - BYTE_C4_G5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
11.9.12.4 QOSC21 - BYTE_C5_G5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
11.9.12.5 QOSC22 - BYTE_C6_G5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
11.9.12.6 QOSC23 - BYTE_C7_G5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
11.9.13 Classes Byte Gigabit Port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
11.9.13.1 QOSC24 - BYTE_C2_G6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
11.9.13.2 QOSC25 - BYTE_C3_G6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
11.9.13.3 QOSC26 - BYTE_C4_G6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
11.9.13.4 QOSC27 - BYTE_C5_G6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.9.13.5 QOSC28 - BYTE_C6_G6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.9.13.6 QOSC29 - BYTE_C7_G6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.9.14 Classes Byte Gigabit Port 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.9.14.1 QOSC2A - BYTE_C2_G7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.9.14.2 QOSC2B - BYTE_C3_G7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.9.14.3 QOSC2C - BYTE_C4_G7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.9.14.4 1QOSC2D - BYTE_C5_G7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.9.14.5 QOSC2E - BYTE_C6_G7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.9.14.6 QOSC2F - BYTE_C7_G7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.9.15 Classes Byte Limit CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.9.15.1 QOSC30 - BYTE_C01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.9.15.2 QOSC31 - BYTE_C02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.9.15.3 QOSC32 - BYTE_C03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.9.16 Classes WFQ Credit Set 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
11.9.16.1 QOSC33 - CREDIT_C0_G0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
11.9.16.2 QOSC34 - CREDIT_C1_G0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
11.9.16.3 QOSC35 - CREDIT_C2_G0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
11.9.16.4 QOSC36 - CREDIT_C3_G0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
11.9.16.5 QOSC37 - CREDIT_C4_G0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
11.9.16.6 QOSC38 - CREDIT_C5_G0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
11.9.16.7 QOSC39- CREDIT_C6_G0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
11.9.16.8 QOSC3A- CREDIT_C7_G0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
10
Zarlink Semiconductor Inc.
MVTX2804
Data Sheet
Table of Contents
11.9.17 Classes WFQ Credit Port G1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
11.9.17.1 QOSC3B - CREDIT_C0_G1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
11.9.17.2 QOSC3C - CREDIT_C1_G1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
11.9.17.3 QOSC3D - CREDIT_C2_G1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
11.9.17.4 QOSC3E - CREDIT_C3_G1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
11.9.17.5 QOSC3F - CREDIT_C4_G1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
11.9.17.6 QOSC40 - CREDIT_C5_G1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
11.9.17.7 QOSC41- CREDIT_C6_G1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
11.9.17.8 QOSC42- CREDIT_C7_G1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
11.9.18 Classes WFQ Credit Port G2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
11.9.18.1 QOSC43 - CREDIT_C0_G2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
11.9.18.2 QOSC44 - CREDIT_C1_G2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
11.9.18.3 QOSC45 - CREDIT_C2_G2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
11.9.18.4 QOSC46 - CREDIT_C3_G2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
11.9.18.5 QOSC47 - CREDIT_C4_G2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
11.9.18.6 QOSC48 - CREDIT_C5_G2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
11.9.18.7 QOSC49- CREDIT_C6_G2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
11.9.18.8 QOSC4A- CREDIT_C7_G2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
11.9.19 Classes WFQ Credit Port G3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
11.9.19.1 QOSC4B - CREDIT_C0_G3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
11.9.19.2 QOSC4 - CREDIT_C1_G3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
11.9.19.3 QOSC4D - CREDIT_C2_G3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
11.9.19.4 QOSC4E - CREDIT_C3_G3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
11.9.19.5 QOSC4F - CREDIT_C4_G3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
11.9.19.6 QOSC50 - CREDIT_C5_G3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
11.9.19.7 QOSC51- CREDIT_C6_G3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
11.9.19.8 QOSC52- CREDIT_C7_G3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
11.9.20 Classes WFQ Credit Port G4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
11.9.20.1 QOSC53 - CREDIT_C0_G4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
11.9.20.2 QOSC54 - CREDIT_C1_G4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
11.9.20.3 QOSC55 - CREDIT_C2_G4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
11.9.20.4 QOSC56 - CREDIT_C3_G4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
11.9.20.5 QOSC57 - CREDIT_C4_G4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
11.9.20.6 QOSC58 - CREDIT_C5_G4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
11.9.20.7 QOSC59- CREDIT_C6_G4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
11.9.20.8 QOSC5A- CREDIT_C7_G4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
11.9.20.9 Classes WFQ Credit Port G5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
11.9.20.10 QOSC5B - CREDIT_C0_G5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
11.9.20.11 QOSC5C - CREDIT_C1_G5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
11.9.20.12 QOSC5D - CREDIT_C2_G5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
11.9.20.13 QOSC5E - CREDIT_C3_G5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
11.9.20.14 QOSC5F - CREDIT_C4_G5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
11.9.20.15 QOSC60 - CREDIT_C5_G5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
11.9.20.16 QOSC61- CREDIT_C6_G5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
11.9.20.17 QOSC62- CREDIT_C7_G5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
11.9.21 Classes WFQ Credit Port G6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
11.9.21.1 QOSC63 - CREDIT_C0_G6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
11.9.21.2 QOSC64 - CREDIT_C1_G6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
11.9.21.3 QOSC65 - CREDIT_C2_G6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
11.9.21.4 QOSC66 - CREDIT_C3_G6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
11.9.21.5 QOSC67 - CREDIT_C4_G6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
11.9.21.6 QOSC68 - CREDIT_C5_G6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
11
Zarlink Semiconductor Inc.
MVTX2804
Data Sheet
Table of Contents
11.9.21.7 QOSC69- CREDIT_C6_G6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
11.9.21.8 QOSC6A- CREDIT_C7_G6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
11.9.22 Classes WFQ Credit Port G7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
11.9.22.1 QOSC6B - CREDIT_C0_G7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
11.9.22.2 QOSC6C - CREDIT_C1_G7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
11.9.22.3 QOSC6D - CREDIT_C2_G7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
11.9.22.4 QOSC6E - CREDIT_C3_G7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
11.9.22.5 QOSC6F - CREDIT_C4_G7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
11.9.22.6 QOSC70 - CREDIT_C5_G7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
11.9.22.7 QOSC71- CREDIT_C6_G7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
11.9.22.8 QOSC72- CREDIT_C7_G7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
11.9.23 Class 6 Shaper Control Port G0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
11.9.23.1 QOSC73 - TOKEN_RATE_G0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
11.9.23.2 QOSC74 - TOKEN_LIMIT_G0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
11.9.23.3 Class 6 Shaper Control Port G1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
11.9.23.4 QOSC75 - TOKEN_RATE_G1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
11.9.23.5 QOSC76 - TOKEN_LIMIT_G1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
11.9.24 Class 6 Shaper Control Port G2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
11.9.24.1 QOSC77 - TOKEN_RATE_G2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
11.9.24.2 QOSC78 - TOKEN_LIMIT_G2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
11.9.25 Class 6 Shaper Control Port G3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
11.9.25.1 QOSC79 - TOKEN_RATE_G3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
11.9.25.2 QOSC7A - TOKEN_LIMIT_G3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
11.9.26 Class 6 Shaper Control Port G4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
11.9.26.1 QOSC7B - TOKEN_RATE_G4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
11.9.26.2 QOSC7C - TOKEN_LIMIT_G4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
11.9.27 Class 6 Shaper Control Port G5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
11.9.27.1 QOSC7D - TOKEN_RATE_G5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
11.9.27.2 QOSC7E - TOKEN_LIMIT_G5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
11.9.28 Class 6 Shaper Control Port G6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
11.9.28.1 Accessed by CPU only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
11.9.28.2 QOSC7F - TOKEN_RATE_G6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
11.9.28.3 QOSC80 - TOKEN_LIMIT_G6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
11.9.29 Class 6 Shaper Control Port G7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
11.9.29.1 QOSC81 - TOKEN_RATE_G7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
11.9.29.2 QOSC82 - TOKEN_LIMIT_G7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
11.9.30 RDRC0 - WRED Rate Control 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
11.9.31 RDRC1 - WRED Rate Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
11.10 Group 6 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
11.10.1 MISC Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
11.10.1.1 MII_OP0 - MII REGISTER OPTION 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
11.10.1.2 MII_OP1 - MII REGISTER OPTION 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
11.10.1.3 FEN - FEATURE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
11.10.1.4 MIIC0 - MII COMMAND REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
11.10.1.5 MIIC1 - MII COMMAND REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
11.10.1.6 MIIC2 - MII COMMAND REGISTER 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
11.10.1.7 MIIC3 - MII COMMAND REGISTER 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
11.10.1.8 MIID0 - MII DATA REGISTER 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
11.10.1.9 MIID1 - MII DATA REGISTER 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
11.10.1.10 LED MODE - LED CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
11.10.2 CHECKSUM - EEPROM Checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
11.10.3 LED User . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
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MVTX2804
Data Sheet
Table of Contents
11.10.3.1 LEDUSER0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
11.10.3.2 LEDUSER1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
11.10.3.3 LEDUSER2/LEDSIG2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
11.10.3.4 LEDUSER3/LEDSIG3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
11.10.3.5 LEDUSER4/LEDSIG4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
11.10.3.6 LEDUSER5/LEDSIG5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
11.10.3.7 LEDUSER6/LEDSIG6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
11.10.3.8 LEDUSER7/LEDSIG1_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
11.10.4 MIINP0 - MII Next Page Data Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
11.10.5 MIINP1 - MII Next Page Data Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
11.11 Group F Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
11.11.1 CPU Access Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
11.11.1.1 GCR-GLOBAL CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
11.11.1.2 DCR-DEVICE STATUS AND SIGNATURE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . 126
11.11.1.3 DCR01-GIGA PORT STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
11.11.1.4 DCR23-GIGA PORT STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
11.11.1.5 DCR45-GIGA PORT STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
11.11.1.6 DCR67-GIGA PORT STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
11.11.1.7 DPST - DEVICE PORT STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
11.11.1.8 DTST - Data Read Back Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
12.0 BGA and Ball Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
12.1 BGA Views (Top-View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
12.2 Ball-Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
12.2.1 Ball Signal Description in Managed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
12.2.2 Ball - Signal Description in Unmanaged Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
12.3 Ball Signal Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
12.4 Characteristics and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
12.4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
12.4.2 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
12.4.3 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
12.5 AC Characteristics and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
12.5.1 Typical Reset & Bootstrap Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
12.5.2 Typical CPU Timing Diagram for a CPU Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
12.5.3 Typical CPU Timing Diagram for a CPU Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
12.5.4 Local Frame Buffer ZBT SRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
12.5.4.1 Local ZBT SRAM Memory Interface A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
12.5.4.2 Local ZBT SRAM Memory Interface B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
12.5.5 Local Switch Database SBRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
12.5.5.1 Local SBRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
12.5.6 Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
12.5.7 Gigabit Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
12.5.8 PCS Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
12.5.9 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
12.5.10 MDIO Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
12.5.11 I2C Input Setup Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
12.5.12 Serial Interface Setup Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
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MVTX2804
Data Sheet
List of Figures
Figure 1 - MVTX2804AG Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - Overview of the MTVTX2804AG CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 3 - Data Transfer Format for I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 4 - MVTX2804 SRAM Interface Block Diagram (DMAs for Gigaport Ports) . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 5 - Buffer Partition Scheme Used in the MVTX2804. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 6 - MVTX2804 Features Enabling IETF Diffserv Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 7 - Timing diagram for serial mode in LED interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 8 - Typical Reset & Bootstrap Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 9 - Typical CPU Timing Diagram for a CPU Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 10 - Typical CPU Timing Diagram for a CPU Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 11 - Local Memory Interface – Input setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 12 - Local Memory Interface - Output valid delay timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 13 - Local Memory Interface – Input setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 14 - Local Memory Interface - Output valid delay timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 15 - Local Memory Interface – Input setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 16 - Local Memory Interface - Output valid delay timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 17 - AC Characteristics – Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 18 - AC Characteristics – Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 19 - AC Characteristics - GMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 20 - AC Characteristics – Gigabit Media Independent Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 21 - AC Characteristics – PCS Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 22 - AC Characteristics – PCS Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 23 - AC Characteristics – LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 24 - MDIO Input Setup and Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 25 - MDIO Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 26 - I2C Input Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 27 - I2C Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 28 - Serial Interface Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 29 - Serial Interface Output Delay Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
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Zarlink Semiconductor Inc.
MVTX2804
Data Sheet
List of Tables
Table 1 - Two-dimensional World Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 2 - Four QoS configurations per port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 3 - WRED Dropping Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 4 - Mapping between MVTX2804 and IETF Diffserv Classes for Gigabit Ports . . . . . . . . . . . . . . . . . . . . . . 34
Table 5 - Reset & Bootstrap Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 6 - CPU Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 7 - CPU Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 8 - AC Characteristics – Local frame buffer ZBT-SRAM Memory Interface A . . . . . . . . . . . . . . . . . . . . . . 163
Table 9 - AC Characteristics – Local frame buffer ZBT-SRAM Memory Interface B . . . . . . . . . . . . . . . . . . . . . . 164
Table 10 - AC Characteristics – Local Switch Database SBRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . 165
Table 11 - AC Characteristics – Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 12 - AC Characteristics – Gigabit Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 13 - AC Characteristics – PCS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 14 - AC Characteristics – LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 15 - MDIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 16 - I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 17 - Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
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MVTX2804
1.0
Block Functionality
1.1
Frame Data Buffer (FDB) Interfaces
Data Sheet
The FDB interface supports pipelined ZBT-SRAM memory at 133 MHz. To ensure a non-blocking switch, two
memory domains are required. Each domain has a 64-bit wide memory bus. At 133 MHz, the aggregate
memory bandwidth is 17 Gbps, which is enough to support 8 Gigabit ports at full wire speed switching. A patent
pending scheme is used to access the FDB memory. Each slot has one tick to read or write 8 bytes.
1.2
Switch Database (SDB) Interface
A pipelined synchronous burst SRAM (SBRAM) memory is used to store the switch database information
including MAC Table, VLAN Table and IP Multicast Table. Search Engine accesses the switch database via
SDB interface. The SDB memory has 32-bit wide bus at 133MHz.
1.3
GMII/PCS MAC Module (GMAC)
The GMII/PCS Media Access Control (MAC) module provides the necessary buffers and control interface
between the Frame Engine (FE) and the external physical device (PHY). The MVTX2804 has two interfaces,
GMII or PCS. The MAC of the MVTX2804 meets the IEEE 802.3z specification and supports the MII interface. It
is able to operate in 10M/100M/1G in Full Duplex mode with a flow control mechanism. It has the options to
insert Source Address/CRC/VLAN ID to each frame. The GMII/PCS Module also supports hot plug detection.
1.4
CPU Interface Module
One extra port is dedicated to the CPU via the CPU interface module. The CPU interface utilizes a 16/8-bit bus
in managed mode. It also supports a serial and an I2C interface, which provides an easy way to configure the
system if unmanaged.
1.5
Management Module
The CPU can send a control frame to access or configure the internal network management database. The
Management Module decodes the control frame and executes the functions requested by the CPU.
1.6
Frame Engine
The main function of the frame engine is to forward a frame to its proper destination port or ports. When a frame
arrives, the frame engine parses the frame header (64 bytes) and formulates a switching request, which is sent
to the search engine to resolve the destination port. The arriving frame is moved to the FDB. After receiving a
switch response from the search engine, the frame engine performs transmission scheduling based on the
frame's priority. The frame engine forwards the frame to the MAC module when the frame is ready to be sent.
1.7
Search Engine
The Search Engine resolves the frame's destination port or ports according to the destination MAC address (L2)
or IP multicast address (IP multicast packet) by searching the database. It also performs MAC learning, priority
assignment, and trunking functions.
1.8
LED Interface
The LED interface can be operated in a serial mode or a parallel mode. In the serial mode, the LED interface
uses 3 pins for carrying 8 port status signals. In the parallel mode, the interface can drive LEDs by 8 status pins.
The LED port is shared with bootstrap pins. In order to avoid mis-reading a buffer must be used to isolate the
LED circuitry from the bootstrap pins during bootstrap cycle (the bootstraps are sampled at the rising edge of
the #Reset).
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MVTX2804
1.9
Data Sheet
Internal Memory
Several internal tables are required and are described as follows:
•
Frame Control Block (FCB) - Each FCB entry contains the control information of the associated frame stored
in the FDB, e.g. frame size, read/write pointer, transmission priority, etc.
•
Network Management (NM) Database - The NM database contains the information in the statistics counters
and MIB.
•
MCT Link Table - The MCT Link Table stores the linked list of MCT entries that have collisions in the external
MAC Table.
•
VLAN Port Aging Table - This table provides the aging status of VLAN Port association status. Search
Engine maintains this table and informs the CPU when the entry is ready to age out.
2.0
System Configuration
2.1
Management and Configuration
Two modes are supported in the MVTX2804: managed and unmanaged. In managed mode, the MVTX2804
uses an 8- or 16-bit CPU interface very similar to the Industry Standard Architecture (ISA) specification. In
unmanaged mode, the MVTX2804 has no CPU but can be configured by EEPROM using an I2C interface at
bootup, or via a synchronous serial interface otherwise.
2.2
Managed Mode
In managed mode, the MVTX2804 uses an 8- or 16-bit CPU interface very similar to the ISA bus. The
MVTX2804 CPU interface provides for easy and effective management of the switching system. The figure
below provides an overview of the CPU interface.
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MVTX2804
Data Sheet
CPU Interface
8/16-bit Data Bus
3-bit Addr
Index Reg 1
(Addr = 001)
Index Reg 0
(Addr = 000)
Config
Data Reg
(Addr = 010)
CPU Frame
Data Reg
(Addr = 011)
8-bit Data Bus
8/16-bit
Data Bus
16-bit Address
Synchronous
Serial
Interface
I/O MUX
Internal
Registers
Command/
Status Reg
(Addr = 100)
Interrupt Reg
(Addr = 101)
Control Frame
Data Reg
(Addr = 110)
Response Reg
(RO)
(Addr = 111)
8/16-bit Data Bus
CPU Frame CPU Frame
Receiver
Transmit
FIFO
FIFO
Frame
Recent
FIFO
Frame
Transmit
FIFO1
Frame
Transmit
FIFO2
Interrupt
Process
Search
Engine
Q0
Q1
MUX
RD_CYC, WR_CYC
To Rate Control RAM
Statistic Counter RAM
FCB RAM
MCT RAM
External SRAM
VLAN Index
Figure 2 - Overview of the MTVTX2804AG CPU Interface
2.3
Register Configuration, Frame Transmission, and Frame Reception
The MVTX2804 has many programmable parameters, covering such functions as QoS weights, VLAN control.
In managed mode, the CPU interface provides an easy way of configuring these parameters. The parameters
are contained in 8-bit configuration registers. The MVTX2804 allows indirect access to these registers, as
follows:
•
ƒTwo “index” registers (addresses 000 and 001) need to be written, to indicate the desired 16-bit register
address.
•
ƒTo indirectly configure the register addressed by the two index registers, a “configure data” register
(address 010) must be written with the desired 8-bit data.
•
ƒSimilarly, to read the value in the register addressed by the two index registers, the “configure data” register
can now simply be read.
In summary, access to the many internal registers is carried out simply by directly accessing only three registers –
two registers to indicate the address of the desired parameter, and one register to read or write a value. Of course,
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MVTX2804
Data Sheet
because there is only one bus master, there can never be any conflict between reading and writing the
configuration registers.
2.3.1
Ethernet Frames
The CPU interface is also responsible for receiving and transmitting standard Ethernet frames to and from the
CPU. To transmit a frame from the CPU
The CPU writes a “data frame” register (address 011) with the data it wants to transmit. After writing all the data,
it then writes the frame size, destination port number, and frame status.
ƒ The MVTX2804 forwards the Ethernet frame to the desired destination port, no longer distinguishing the fact
that the frame originated from the CPU.
To receive a frame into the CPU
ƒ
The CPU receives an interrupt when an Ethernet frame is available to be received.
Frame information arrives first in the data frame register. This includes source port number, frame size, and
VLAN tag.
ƒ The actual data follows the frame information. The CPU uses the frame size information to read the frame out.
In summary, receiving and transmitting frames to and from the CPU is a simple process that uses one direct
access register only.
ƒ
ƒ
2.3.2
Control Frames
In addition to standard Ethernet frames described in the preceding section, the CPU is also called upon to
handle special “Control frames,” generated by the MVTX2804 and sent to the CPU. These proprietary frames
are related to such tasks as statistics collection, MAC address learning, aging, etc. All Control frames are 64
bytes long. Transmitting and receiving these frames is similar to transmitting and receiving Ethernet frames,
except that the register accessed is the “Control frame data” register (address 110).
Specifically, there are eight types of control frames generated by the CPU and sent to the MVTX2804:
• Memory read request
• Memory write request
• Learn MAC address
• Delete MAC address
• Search MAC address
• Learn IP Multicast address
• Delete IP Multicast address
• Search IP Multicast address
Note: Memory read and write requests by the CPU may include VLAN table, spanning tree, statistic counters,
and similar updates.
In addition, there are nine types of Control Frames generated by the MVTX2804 and sent to the CPU:
•
•
•
•
•
•
•
•
•
Interrupt CPU when statistics counter rolls over
Response to memory read request from CPU
Learn MAC address
Delete MAC address
Delete IP Multicast address
New VLAN port
Age out VLAN port
Response to search MAC address request from CPU
Response to search IP Multicast address request from CPU
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MVTX2804
Data Sheet
Note: Deleting IP Multicast address requests by the MVTX2804 occur when the CPU issues a Learn IP Multicast
address command but the search engine discovers no RAM space for storage.
The format of the Control Frame is described in the processor interface application note.
2.4
Unmanaged Mode
In unmanaged mode, the MVTX2804 can be configured by EEPROM (24C02 or compatible) via an I2C interface
at boot time, or via a synchronous serial interface during operation. When the bootstrap Td[8] is set to ‘0’
meaning EEPROM installed, the MVTX2804, acting as a master starts the data transfer from the memory to the
switch.
2.5
I2C Interface
The I2C interface uses two bus lines, a serial data line (SDA) and a serial clock line (SCL). The SCL line carries
the control signals that facilitate the transfer of information from EEPROM to the switch. Data transfer is 8-bit
serial and bi-directional, at 50 Kbps. Data transfer is performed between master and slave IC using a request /
acknowledgment style of protocol. The master IC generates the timing signals and terminates data transfer. The
figure below shows the data transfer format.
START
SLAVE
ADDRESS
R/W
ACK
DATA 1
(8 bits)
ACK
DATA 2
ACK
DATA M
ACK
STOP
Figure 3 - Data Transfer Format for I 2C Interface
2.5.1
Start Condition
Generated by the master, the MVTX2804. The bus is considered to be busy after the Start condition is
generated. The Start condition occurs if while the SCL line is High, there is a High-to-Low transition of the SDA
line.
Other than in the Start condition (and Stop condition), the data on the SDA line must be stable during the High
period of SCL. The High or Low state of SDA can only change when SCL is Low. In addition, when the I2C bus
is free, both lines are High.
2.5.2
Address
The first byte after the Start condition determines which slave the master will select. The slave in our case is the
EEPROM. The first seven bits of the first data byte make up the slave address.
2.5.3
Data Direction
The eighth bit in the first byte after the Start condition determines the direction (R/W) of the message. A master
transmitter sets this bit to W; a master receiver sets this bit to R.
2.5.4
Acknowledgment
Like all clock pulses, the master generates the acknowledgment-related clock pulse. However, the transmitter
releases the SDA line (High) during the acknowledgment clock pulse. Furthermore, the receiver must pull down
the SDA line during acknowledge pulse so that it remains stable Low during the High period of this clock pulse.
An acknowledgment pulse follows every byte transfer.
If a slave receiver does not acknowledge after any byte, then the master generates a Stop condition and aborts
the transfer.
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MVTX2804
Data Sheet
If a master receiver does not acknowledge after any byte, then the slave transmitter must release the SDA line
to let the master generate the Stop condition.
2.5.5
Data
After the first byte containing the address, all bytes that follow are data bytes. Each byte must be followed by an
acknowledge bit. Data is transferred MSB-first.
2.5.6
Stop Condition
Generated by the master. The bus is considered to be free after the Stop condition is generated. The Stop
condition occurs if while the SCL line is High, there is a Low-to-High transition of the SDA line.
The I2C interface serves the function of configuring the MVTX2804 at boot time. The master is the MVTX2804,
and the slave is the EEPROM memory.
2.6
Synchronous Serial Interface
The synchronous serial interface serves the function of configuring the MVTX2804 not at boot time but via a
PC. The PC serves as master and the MVTX2804 serves as slave. The protocol for the synchronous serial
interface is nearly identical to the I2C protocol. The main difference is that there is no acknowledgment bit after
each byte of data transferred.
The unmanaged MVTX2804 uses a synchronous serial interface to program the internal registers. To reduce
the number of signals required, the register address, command and data are shifted in serially through the
PS_DI pin. PS_STROBE pin is used as the shift clock. PS_DO pin is used as data return path.
Each command consists of four parts.
•
•
•
•
START pulse
Register Address
Read or Write command
Data to be written or read back
Any command can be aborted in the middle by sending an ABORT pulse to the MVTX2804.
A START command is detected when PS_DI is sampled high at PS_STROBE - leading edge, and PS_DI is
sampled low when PS_STROBE- falls.
An ABORT command is detected when PS_DI is sampled low at PS_STROBE - leading edge, and PS_DI is
sampled high when PS_STROBE - falls.
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MVTX2804
2.6.1
Data Sheet
Write Command
PS-STROBE2 Extra clocks after last
transfer
A0 A1 A2
PS_DI
START
2.6.2
...
A9
A11
A10
ADDRESS
W
D0 D1 D2 D3 D4 D5 D6 D7
COMMAND
DATA
Read Command
PS_STROBE-
PS_DI
A0 A1 A2
START
...
A9
ADDRESS
PS_DO
A10
A11
R
COMMAND
DATA
D0 D1 D2 D3 D4 D5 D6 D7
All registers in the MVTX2804 can be modified through this synchronous serial interface.
3.0
Data Forwarding Protocol
3.1
Unicast Data Frame Forwarding
When a frame arrives, it is assigned a handle in memory by the Frame Control Buffer Manager (FCB Manager).
An FCB handle will always be available, because of advance buffer reservations.
The memory (ZBT-SRAM) interface is two 64-bit buses, connected to two ZBT-SRAM domains, A and B. The
Receive DMA (RxDMA) is responsible for multiplexing the data and the address. On a port's “turn,” the RxDMA
will move 8 bytes (or up to the end-of-frame) from the port's associated RxFIFO into memory (Frame Data
Buffer, or FDB).
Once an entire frame has been moved to the FDB, and a good end-of-frame (EOF) has been received, the Rx
interface makes a switch request. The RxDMA arbitrates among multiple switch requests.
The switch request consists of the first 64 bytes of a frame, containing among other things, the source and
destination MAC addresses of the frame. The search engine places a switch response in the switch response
queue of the frame engine when done. Among other information, the search engine will have resolved the
destination port of the frame and will have determined that the frame is unicast.
After processing the switch response, the Transmission Queue Manager (TxQ manager) of the frame engine is
responsible for notifying the destination port that it has a frame to forward to it. But first, the TxQ manager has
to decide whether or not to drop the frame, based on global FDB reservations and usage, as well as TxQ
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MVTX2804
Data Sheet
occupancy at the destination. If the frame is not dropped, then the TxQ manager links the frame's FCB to the
correct per-port-per-class TxQ. Unicast TxQ's are linked lists of transmission jobs, represented by their
associated frames' FCBs. There is one linked list for each transmission class for each port. There are 8 classes
for each of the 8 Gigabit ports - a total of 32 unicast queues.
The TxQ manager is responsible for scheduling transmission among the queues representing different classes
for a port. When the port control module determines that there is room in the MAC Transmission FIFO (TxFIFO)
for another frame, it requests the handle of a new frame from the TxQ manager. The TxQ manager chooses
among the head-of-line (HOL) frames from the per-class queues for that port, using a Zarlink Semiconductor
scheduling algorithm.
As at the transmit end, each of the 8 ports has time slots devoted solely to reading data from memory at the
address calculated by port control. The Transmission DMA (TxDMA) is responsible for multiplexing the data and
the address. On a port's turn, the TxDMA will move 8 bytes (or up to the EOF) from memory into the port's
associated TxFIFO. After reading the EOF, the port control requests a FCB release for that frame. The TxDMA
arbitrates among multiple buffer release requests.
The frame is transmitted from the TxFIFO to the line.
3.2
Multicast Data Frame Forwarding
After receiving the switch response, the TxQ manager has to make the dropping decision. A global decision to
drop can be made, based on global FDB utilization and reservations. If so, then the FCB is released and the
frame is dropped. In addition, a selective decision to drop can be made, based on the TxQ occupancy at some
subset of the multicast packet's destinations. If so, then the frame is dropped at some destinations but not
others, and the FCB is not released.
If the frame is not dropped at a particular destination port, then the TxQ manager formats an entry in the
multicast queue for that port and class. Multicast queues are physical queues (unlike the linked lists for unicast
frames). There are 4 multicast queues for each of the 8 Gigabit ports. There is one multicast queue for every
two unicast classes.
During scheduling, the TxQ manager treats the unicast queue and the multicast queue of the same class as one
logical queue.
The port control requests a FCB release only after the EOF for the multicast frame has been read by all ports to
which the frame is destined.
3.3
Frame Forwarding To and From CPU
Frame forwarding from the CPU port to a regular transmission port is nearly the same as forwarding between
transmission ports. The only difference is that the physical destination port must be indicated in addition to the
destination MAC address. If an invalid port is indicated the frame is forwarded accordingly to the destination
MAC address.
Frame forwarding to the CPU port is nearly the same as forwarding to a regular transmission port. The only
difference is in frame scheduling. Instead of using the patent-pending scheduling algorithms, scheduling for
the CPU port is simply based on strict priority. That is, a frame in a high priority queue will always be transmitted
before a frame in a lower priority queue. There are four output queues to the CPU and one receive queue.
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Zarlink Semiconductor Inc.
MVTX2804
4.0
Memory Interface
4.1
Overview
Data Sheet
The figure below illustrates the first part of the ZBT-SRAM interface for the MVTX2804. As shown, two
ZBT-SRAM banks A and B are used, with a 64-bit bus connected to each. Each DMA can read and write from
both bank A and bank B. During each tick, two memory operations will take place in parallel - one for bank A,
and one for bank B. Because the clock frequency is 133 MHz, the total memory bandwidth is 128 bits
133 MHz = 17 Gbps, for frame data buffer (FDB) access.
In addition, the figure shows that the 8 Gigabit ports are actually grouped into sets of 4. If TxDMA 0 is using
bank B during a given memory slot, then TxDMA's 1-3 will never be using bank A during this same slot. As a
result, TxDMA's 0-3 can share the same bank selector.
Not shown in the figure are the CPU port RxDMA's and TxDMA's, each separately connected to its own bank
selector.
ZBT-SRAM Bank A
TxDMA
0-1
TxDMA
2-3
TxDMA
4-5
ZBT-SRAM Bank B
TxDMA
6-7
RxDMA
0-1
RxDMA
2-3
RxDMA
4-5
RxDMA
6-7
Figure 4 - MVTX2804 SRAM Interface Block Diagram (DMAs for Gigaport Ports)
4.2
Detailed Memory Information
Because the bus for each bank is 64 bits wide, frames are broken into 8-byte granules, written to and read from
memory. The first 8-byte granule gets written to Bank A, the second 8-byte granule gets written to Bank B, and
so on in alternating fashion. When reading frames from memory, the same procedure is followed, first from A,
then from B, and so on.
The reading and writing from alternating memory banks can be performed with minimal waste of memory
bandwidth. What's the worst case? For any speed port, in the worst case, a 1-byte-long EOF granule gets
written to Bank A. This means that a 7-byte segment of Bank A bandwidth is idle, and furthermore, the next
8-byte segment of Bank B bandwidth is idle, because the first 8 bytes of the next frame will be written to Bank A,
not B. This scenario results in a maximum 15 bytes of waste per frame, which is always acceptable because the
interframe gap is 20 bytes.
The CPU management port gets treated like any other port, reading and writing to alternating memory banks
starting with Bank A. Search engine data is written to both banks in parallel. In this way, a search engine read
operation could be performed by either bank at any time without a problem.
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Zarlink Semiconductor Inc.
MVTX2804
5.0
Search Engine
5.1
Search Engine Overview
Data Sheet
The MVTX2804 search engine is optimized for high throughput searching, with enhanced features to support:
•
•
•
•
•
•
•
•
•
Up to 64K MAC addresses
Up to 4K VLAN
Up to 64K IP Multicast groups
4 groups of port trunking
Traffic classification into 8 transmission priorities, and 2 drop precedence levels
Packet filtering
Security
IP Multicast
Per port, per VLAN Spanning Tree
5.2
Basic Flow
Shortly after a frame enters the MVTX2804 and is written to the Frame Data Buffer (FDB), the frame engine
generates a Switch Request, which is sent to the search engine. The switch request consists of the first 64
bytes of the frame, which contain all the necessary information for the search engine to perform its task. When
the search engine is done, it writes to the Switch Response Queue, and the frame engine uses the information
provided in that queue for scheduling and forwarding.
In performing its task, the search engine extracts and compresses the useful information from the 64-byte
switch request. Among the information extracted are the source and destination MAC addresses, the
transmission and discard priorities, whether the frame is unicast or multicast, and VLAN ID. Requests are sent
to the external SRAM Switch Database to locate the associated entries in the external MCT table.
When all the information has been collected from external SRAM, the search engine has to compare the MAC
address on the current entry with the MAC address for which it is searching. If it is not a match, the process is
repeated on the internal MCT Table. All MCT entries other than the first of each linked list are maintained
internal to the chip. If the desired MAC address is still not found, then the result is either learning (source MAC
address unknown) or flooding (destination MAC address unknown).
In addition, VLAN information is used to select the correct set of destination ports for the frame (for multicast),
or to verify that the frame's destination port is associated with the VLAN (for unicast).
If the destination MAC address belongs to a port trunk, then the trunk number is retrieved instead of the port
number. But on which port of the trunk will the frame be transmitted? This is easily computed using a hash of
the source and destination MAC addresses.
When all the information is compiled, the switch response is generated, as stated earlier. The search engine
also interacts with the CPU with regard to learning and aging.
5.3
5.3.1
Search, Learning, and Aging
MAC Search
The search block performs source MAC address and destination MAC address (or destination IP address for IP
multicast) searching. As we indicated earlier, if a match is not found, then the next entry in the linked list must
be examined, and so on until a match is found or the end of the list is reached.
In tag based VLAN mode, if the frame is unicast, and the destination port is not a member of the correct VLAN,
then the frame is dropped; otherwise, the frame is forwarded. If the frame is multicast, this same table is used to
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MVTX2804
Data Sheet
indicate all the ports to which the frame will be forwarded. Moreover, if port trunking is enabled, this block
selects the destination port (among those in the trunk group).
In port based VLAN mode, a bitmap is used to determine whether the frame should be forwarded to the
outgoing port. The main difference in this mode is that the bitmap is not dynamic. Ports cannot enter and exit
groups because of real-time learning made by a CPU.
The MAC search block is also responsible for updating the source MAC address timestamp and the VLAN port
association timestamp, used for aging.
5.3.2
Learning
The learning module learns new MAC addresses and performs port change operations on the MCT database.
The goal of learning is to update this database as the networking environment changes over time. When CPU
reporting is enabled, learning and port change will be performed when the CPU request queue has room, and a
memory slot is available, and a “Learn MAC Address” message is sent to the CPU. When CPU reporting is
disabled, learning and port change will be performed based on memory slot availability only.
In tag based VLAN mode, if the source port is not a member of a classified VLAN, a “New VLAN Port” message
is sent to the CPU. The CPU can decide whether or not the source port can be added to the VLAN.
5.3.3
Aging
Aging time is controlled by register 400h and 401h.
The aging module scans and ages MCT entries based on a programmable “age out” time interval. As we
indicated earlier, the search module updates the source MAC address and VLAN port association timestamps
for each frame it processes. When an entry is ready to be aged, the entry is removed from the table, and a
“Delete MAC Address” message is sent to inform the CPU.
Supported entry types are dynamic, static, source filter, destination filter, IP multicast, source and destination
filter, and secure MAC address. Only dynamic entries can be aged; whether an entry is static or dynamic is
maintained in the “status” field of the MCT data structure.
5.3.4
Data Structure
The MCT data structure is used for searching for MAC addresses. The structure is maintained by hardware in
the search engine. The CPU can make requests to add to, delete from, or search the MCT database. The
database is essentially a hash table, with collisions resolved by chaining. The database is partially external, and
partially internal, as described earlier: the first MCT entry of each linked list is always located in the external
SRAM, and the subsequent MCTs are located internally.
5.3.5
VLAN Port Association Table
31
30
Valid
Route
29
27
26
0
Reserved
Port 8 to 0 is VLAN status
Port 8
Port 7
Port 6
Port 5
Port 4
Port 3
Port 2
Port 1
Port 0
VLAN
status
VLAN
status
VLAN
status
VLAN
status
VLAN
status
VLAN
status
VLAN
status
VLAN
status
VLAN
status
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MVTX2804
Data Sheet
VLAN STATUS [2:0]
•
000:Not a valid entry
•
001:Blocking status, no RX and TX
•
010:Not a VLAN member, spanning tree learn status
•
011:VLAN member, spanning tree learn status
•
100:Not a VLAN member, spanning tree forward status
•
101:VLAN member and is subject to aging, spanning tree forward status (Don't use)
•
110:VLAN member and is subject to aging, spanning tree forward status
•
111:VLAN member and is not subject to aging, spanning tree forward status
CPU can create static VLAN port by writing the static status to the VLAN- PORT status entry.
Dynamic VLAN and Port association can be created by writing “110” to the VLAN STATUS. Hardware will age
and refresh the entry based on the VLAN - PORT activity. When the VLAN - PORT is ready to be aged out, a
message is sent to CPU and CPU can remove the VLAN - PORT association by writing “000” to the VLAN
STATUS. As a result, the VLAN and PORT are no long associated and the VLAN domain is shrunk.
6.0
Frame Engine
6.1
Data Forwarding Summary
•
Enters the device at the RxMAC, the RxDMA will move the data from the MAC RxFIFO to the FDB. Data is
moved in 8-byte granules in conjunction with the scheme for the SRAM interface.
•
A switch request is sent to the Search Engine. The Search Engine processes the switch request.
•
A switch response is sent back to the Frame Engine and indicates whether the frame is unicast or multicast,
and its destination port or ports. A VLAN table lookup is performed as well.
•
A Transmission Scheduling Request is sent in the form of a signal notifying the TxQ manager. Upon
receiving a Transmission Scheduling Request, the device will format an entry in the appropriate
Transmission Scheduling Queue (TxSch Q) or Queues. There is 8 transmission queues per Gigabit port,
one for each priority. Creation of a queue entry either involves linking a new job to the appropriate linked list
if unicast, or adding an entry to a physical queue if multicast.
•
When the port is ready to accept the next frame, the TxQ manager will get the head-of-line (HOL) entry of
one of the TxSch Qs, according to the transmission scheduling algorithm (so as to ensure per-class quality
of service). The unicast linked list and the multicast queue for the same port-class pair are treated as one
logical queue.
•
The TxDMA will pull frame data from the memory and forward it granule-by-granule to the MAC TxFIFO of
the destination port.
6.2
Frame Engine Details
This section briefly describes the functions of each of the modules of the MVTX2804 frame engine.
6.2.1
FCB Manager
The FCB manager allocates FCB handles to incoming frames, and releases FCB handles upon frame
departure. The FCB manager is also responsible for enforcing buffer reservations and limits. The default values
can be determined by referring to Chapter 8. In addition, the FCB manager is responsible for buffer aging, and
for linking unicast forwarding jobs to their correct TxSch Q. The buffer aging can be enabled or disabled by the
bootstrap pin and the aging time is defined in register FCBAT.
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6.2.2
Data Sheet
Rx Interface
The Rx interface is mainly responsible for communicating with the RxMAC. It keeps track of the start and end of
frame and frame status (good or bad). Upon receiving an end of frame that is good, the Rx interface makes a
switch request.
6.2.3
RxDMA
The RxDMA arbitrates among switch requests from each Rx interface. It also buffers the first 64 bytes of each
frame for use by the search engine when the switch request has been made.
6.2.4
TxQ Manager
First, the TxQ manager checks the per-class queue status and global Reserved resource situation, and using
this information, makes the frame dropping decision after receiving a switch response. If the decision is not to
drop, the TxQ manager requests that the FCB manager link the unicast frame's FCB to the correct
per-port-per-class TxQ. If multicast, the TxQ manager writes to the multicast queue for that port and class. The
TxQ manager can also trigger source port flow control for the incoming frame's source if that port is flow control
enabled. Second, the TxQ manager handles transmission scheduling; it schedules transmission among the
queues representing different classes for a port. Once a frame has been scheduled, the TxQ manager reads
the FCB information and writes to the correct port control module.
6.3
Port Control
The port control module calculates the SRAM read address for the frame currently being transmitted. It also
writes start of frame information and an end of frame flag to the MAC TxFIFO. When transmission is done, the
port control module requests that the buffer be released.
6.4
TxDMA
The TxDMA multiplexes data and address from port control, and arbitrates among buffer release requests from
the port control modules.
7.0
Quality of Service and Flow Control
7.1
Model
Quality of service (QoS) is an all-encompassing term for which different people have different interpretations. In
this chapter, by quality of service assurances, we mean the allocation of chip resources so as to meet the
latency and bandwidth requirements associated with each traffic class. We do not presuppose anything about
the offered traffic pattern. If the traffic load is light, then ensuring quality of service is straightforward. But if the
traffic load is heavy, the MVTX2804 must intelligently allocate resources so as to assure quality of service for
high priority data.
We assume that the network manager knows his applications, such as voice, file transfer, or web browsing, and
their relative importance. The manager can then subdivide the applications into classes and set up a service
contract with each. The contract may consist of bandwidth or latency assurances per class. Sometimes it may
even reflect an estimate of the traffic mix offered to the switch, though this is not required.
The table below shows examples of QoS applications with eight transmission priorities, including best effort
traffic for which we provide no bandwidth or latency assurances.
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Class
Example
Assured
Bandwidth
(user defined)
Low Drop Subclass
(If class is
oversubscribed, these
packets are the last to be
dropped.)
Highest transmission
priorities, P7
Latency < 200 µs
300 Mbps
Sample application:
control information
Highest transmission
priorities, P6
Latency < 200 µs
200 Mbps
Middle transmission
priorities, P5
Latency < 400 µs
Data Sheet
High Drop Subclass
(If class is oversubscribed,
these packets are the first
to be dropped.)
Sample applications:
phone calls; circuit
emulation
Sample application:
training video; other multimedia
125 Mbps
Sample application:
interactive activities
Sample application:
non-critical interactive activities
Middle transmission
priorities, P4
Latency < 800 µs
250 Mbps
Sample application:
web business
Sample application:
non-critical interactive activities
Low transmission
priorities, P3
Latency < 1600 µs
80 Mbps
Sample application:
file backups
Low transmission
priorities, P2
Latency < 3200 µs
45 Mbps
Sample application:
email
Best effort, P1-P0
-
TOTAL
1 Gbps
Sample application:
web research
Sample application: casual web browsing
Table 1 - Two-dimensional World Traffic
In our model, it is possible that a class of traffic may attempt to monopolize system resources by sending data
at a rate in excess of the contractually assured bandwidth for that class. A well-behaved class offers traffic at a
rate no greater than the agreed-upon rate. By contrast, a misbehaving class offers traffic that exceeds the
agreed-upon rate. A misbehaving class is formed from an aggregation of misbehaving microflows. To achieve
high link utilization, a misbehaving class is allowed to use any idle bandwidth. However, the quality of service
(QoS) received by well-behaved classes must never suffer.
As Table 1 illustrates, each traffic class may have its own distinct properties and applications. As shown,
classes may receive bandwidth assurances or latency bounds. In the example, P7, the highest transmission
class, requires that all frames be transmitted within 0.2 ms, and receives 30% of the 1 Gbps of bandwidth at that
port.
Best-effort (P1-P0) traffic forms a lower tier of service that only receives bandwidth when none of the other
classes have any traffic to offer.
In addition, each transmission class has two subclasses, high-drop and low-drop. Well-behaved users should
not lose packets. But poorly behaved users - users who send data at too high a rate - will encounter frame loss,
and the first to be discarded will be high-drop. Of course, if this is insufficient to resolve the congestion,
eventually some low-drop frames are dropped as well.
Table 1 shows that different types of applications may be placed in different boxes in the traffic table. For
example, web search may fit into the category of high-loss, high-latency-tolerant traffic, whereas VoIP fits into
the category of low-loss, low-latency traffic.
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7.2
Data Sheet
Four QoS Configurations
There are four basic pieces to QoS scheduling in the MVTX2804: strict priority (SP), delay bound, weighted fair
queuing (WFQ), and best effort (BE). Using these four pieces, there are four different modes of operation, as
shown in Table 2.
P7
P6
P5
P4
Op1 (default)
Delay Bound
Op2
SP
Delay Bound
Op3
SP
WFQ
Op4
WFQ
P3
P2
P1
P0
BE
BE
Table 2 - Four QoS configurations per port
The default configuration is six delay-bounded queues and two best-effort queues. The delay bounds per class are
0.16 ms for P7 and P6, 0.32 ms for P5, 0.64 ms for P4, 1.28 ms for P3, and 2.56 ms for P2. Best effort traffic is only
served when there is no delay-bounded traffic to be served. P1 has strict priority over P0.
We have a second configuration in which there are two strict priority queues, four delay bounded queues, and
two best effort queues. The delay bounds per class are 0.32 ms for P5, 0.64 ms for P4, 1.28 ms for P3, and
2.56 ms for P2. If the user is to choose this configuration, it is important that P7-P6 (SP) traffic be either
policed or implicitly bounded (e.g. if the incoming SP traffic is very light and predictably patterned). Strict priority
traffic, if not admission-controlled at a prior stage to the MVTX2804, can have an adverse effect on all other
classes' performance. P7 and P6 are both SP classes, and P7 has strict priority over P6.
The third configuration contains two strict priority queues and six queues receiving a bandwidth partition via
WFQ. As in the second configuration, strict priority traffic needs to be carefully controlled.
In the fourth configuration, all queues are served using a WFQ service discipline.
7.3
Delay Bound
In the absence of a sophisticated QoS server and signalling protocol, the MVTX2804 may not be assured of the
mix of incoming traffic ahead of time. To cope with this uncertainty, our delay assurance algorithm dynamically
adjusts its scheduling and dropping criteria, guided by the queue occupancies and the due dates of their
head-of-line (HOL) frames. As a result, we assure latency bounds for all admitted frames with high confidence,
even in the presence of system-wide congestion. Our algorithm identifies misbehaving classes and intelligently
discards frames at no detriment to well-behaved classes. Our algorithm also differentiates between high-drop
and low-drop traffic with a weighted random early drop (WRED) approach. Random early dropping prevents
congestion by randomly dropping a percentage of high-drop frames even before the chip's buffers are
completely full, while still largely sparing low-drop frames. This allows high-drop frames to be discarded early,
as a sacrifice for future low-drop frames. Finally, the delay bound algorithm also achieves bandwidth partitioning
among classes.
7.4
Strict Priority and Best Effort
When strict priority is part of the scheduling algorithm, if a queue has even one frame to transmit, it goes first.
Two of our four QoS configurations include strict priority queues. The goal is for strict priority classes to be used
for IETF expedited forwarding (EF), where performance guarantees are required. As we have indicated, it is
important that strict priority traffic be either policed or implicitly bounded, so as to keep from harming other
traffic classes.
When best effort is part of the scheduling algorithm, a queue only receives bandwidth when none of the other
classes have any traffic to offer. Two of our four QoS configurations include best effort queues. The goal is for
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MVTX2804
Data Sheet
best effort classes to be used for non-essential traffic, because we provide no assurances about best effort
performance. However, in a typical network setting, much best effort traffic will indeed be transmitted, and with
an adequate degree of expediency.
Because we do not provide any delay assurances for best effort traffic, we do not enforce latency by dropping
best effort traffic. Furthermore, because we assume that strict priority traffic is carefully controlled before
entering the MVTX2804, we do not enforce a fair bandwidth partition by dropping strict priority traffic. To
summarize, dropping to enforce quality of service (i.e. bandwidth or delay) does not apply to strict priority or
best effort queues. We only drop frames from best effort and strict priority queues when global buffer resources
become scarce.
7.5
Weighted Fair Queuing
In some environments - for example, in an environment in which delay assurances are not required, but precise
bandwidth partitioning on small time scales is essential - WFQ may be preferable to a delay-bounded
scheduling discipline. The MVTX2804 provides the user with a WFQ option with the understanding that delay
assurances cannot be provided if the incoming traffic pattern is uncontrolled. The user sets eight WFQ “weights”
such that all weights are whole numbers and sum to 64. This provides per-class bandwidth partitioning with
error within 2%.
In WFQ mode, though we do not assure frame latency, the MVTX2804 still retains a set of dropping rules that
helps to prevent congestion and trigger higher level protocol end-to-end flow control.
As before, when strict priority is combined with WFQ, we do not have special dropping rules for the strict priority
queues, because the input traffic pattern is assumed to be carefully controlled at a prior stage. However, we do
indeed drop frames from SP queues for global buffer management purposes. In addition, queues P1 and P0 are
treated as best effort from a dropping perspective, though they still are assured a percentage of bandwidth from
a WFQ scheduling perspective. What this means is that these particular queues are only affected by dropping
when the global buffer count becomes low.
7.6
Shaper
Although traffic shaping is not a primary function of the MVTX2804, the chip does implement a shaper for
expedited forwarding (EF). Our goal in shaping is to control the peak and average rate of traffic exiting the
MVTX2804. Shaping is limited to class P6 (the second highest priority). This means that class P6 will be the
class used for EF traffic. (By contrast, we assume class P7 will be used for control packets only.) If shaping is
enabled for P6, then P6 traffic must be scheduled using strict priority. With reference to Table 2, only the middle
two QoS configurations may be used.
Peak rate is set using a programmable whole number, no greater than 64 (register QOS-CREDIT_C6_Gn). For
example, if the setting is 32, then the peak rate for shaped traffic is 32/64 1000 Mbps = 500 Mbps. Average rate
is also a programmable whole number, no greater than 64, and no greater than the peak rate. For example, if
the setting is 16, then the average rate for shaped traffic is 16/64 1000 Mbps = 250 Mbps. As a consequence of
the above settings in our example, shaped traffic will exit the MVTX2804 at a rate always less than 500 Mbps,
and averaging no greater than 250 Mbps.
Also, when shaping is enabled, it is possible for a P6 queue to explode in length if fed by a greedy source. The
reason is that a shaper is by definition not work-conserving; that is, it may hold back from sending a packet
even if the line is idle. Though we do have global resource management, we do nothing to prevent this situation
locally. We assume SP traffic is policed at a prior stage to the MVTX2804.
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MVTX2804
7.7
Data Sheet
WRED Drop Threshold Management Support
To avoid congestion, the Weighted Random Early Detection (WRED) logic drops packets according to specified
parameters. The following table summarizes the behaviour of the WRED logic.
P7
Level 1
N ≥ 240
Level 2
N ≥ 280
P7 ≥A
KB
P6
P5
P6 ≥B
KB
P5 ≥C
KB
P4
P4 ≥D
KB
P3
P3 ≥E
KB
Level 3
N ≥ 320
P2
P2 ≥F
KB
High
Drop
Low
Drop
X%
0%
Y%
Z%
100%
100%
Table 3 - WRED Dropping Scheme
In the table, |Px| is the byte count in queue Px. The WRED logic has three drop levels, depending on the value
of N, which is based on the number of bytes in the priority queues. If delay bound scheduling is used, N equals
16|P7| + 16|P6| + 8|P5| + 4|P4| + 2|P3| + |P2|. If WFQ scheduling is used, N equals |P7| + |P6| + |P5| + |P4| +
|P3| + |P2|. Each drop level has defined high-drop and low-drop percentages, which indicate the percentage of
high-drop and low-drop packets that will be dropped at that level. The X, Y, and Z percent parameters can be
programmed using the registers RDRC0 and RDRC1. Parameters A-F are the byte count thresholds for each
priority queue, and are also programmable. When using delay bound scheduling, the values selected for A-F
also control the approximate bandwidth partition among the traffic classes; see application note.
7.8
Buffer Management
Because the number of frame data buffer (FDB) slots is a scarce resource, and because we want to ensure that
one misbehaving source port or class cannot harm the performance of a well-behaved source port or class, we
introduce the concept of buffer management into the MVTX2804. Our buffer management scheme is designed
to divide the total buffer space into numerous reserved regions and one shared pool, (see Figure 4).
As shown in the figure, the FDB pool is divided into several parts. A reserved region for temporary frames
stores frames prior to receiving a switch response. Such a temporary region is necessary, because when the
frame first enters the MVTX2804, its destination port and class are as yet unknown, and so the decision to drop
or not needs to be temporarily postponed. This ensures that every frame can be received first before subjecting
it to the frame drop discipline after classifying.
Six reserved sections, one for each of the highest six priority classes, ensure a programmable number of FDB
slots per class. The lowest two classes do not receive any buffer reservation.
Another segment of the FDB reserves space for each of the 8 Gigabit ports and CPU port. These source port
buffer reservations are programmable. These 9 reserved regions make sure that no well-behaved source port
can be blocked by another misbehaving source port.
In addition, there is a shared pool, which can store any type of frame. The registers related to the Buffer
Management logic are
•
PRG- Port Reservation for Gigabit Ports and CPU port
•
SFCB- Share FCB Size
•
C2RS- Class 2 Reserved Size
•
C3RS- Class 3 Reserved Size
•
C4RS- Class 4 Reserved Size
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MVTX2804
•
C5RS- Class 5 Reserved Size
•
C6RS- Class 6 Reserved Size
•
C7RS- Class 7 Reserved Size
Data Sheet
Temporary
Reservation RTMP
Shared Pool S
Per-Class
Reservations
RP7, RP6,...RP2
Per-Source Reservations 8-R1G
Figure 5 - Buffer Partition Scheme Used in the MVTX2804
7.8.1
Dropping When Buffers Are Scarce
The following is a summary of the two examples of local dropping discussed earlier in this chapter:
•
If a queue is a delay-bounded queue, we have a multi-level WRED drop scheme, designed to control delay
and partition bandwidth in case of congestion.
•
If a queue is a WFQ-scheduled queue, we have a multi-level WRED drop scheme, designed to prevent
congestion.
In addition to these reasons for dropping, the MVTX2804 also drops frames when global buffer space becomes
scarce. The function of buffer management is to ensure that such droppings cause as little blocking as possible.
7.9
Flow Control Basics
Because frame loss is unacceptable for some applications, the MVTX2804 provides a flow control option. When
flow control is enabled, scarcity of buffer space in the switch may trigger a flow control signal; this signal tells a
source port, sending a packet to this switch, to temporarily hold off.
While flow control offers the clear benefit of no packet loss, it also introduces a problem for quality of service.
When a source port receives an Ethernet flow control signal, all microflows originating at that port, well-behaved
or not, are halted. A single packet destined for a congested output can block other packets destined for
uncongested outputs. The resulting head-of-line blocking phenomenon means that quality of service cannot be
assured with high confidence when flow control is enabled.
In the MVTX2804, each source port can independently have flow control enabled or disabled. For flow control
enabled ports, by default all frames are treated as lowest priority during transmission scheduling. This is done
so that those frames are not exposed to the WRED Dropping scheme. Frames from flow control enabled ports
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MVTX2804
Data Sheet
feed to only one queue at the destination, the queue of lowest priority. What this means is that if flow control is
enabled for a given source port, then we can guarantee that no packets originating from that port will be lost, but
at the possible expense of minimum bandwidth or maximum delay assurances. In addition, these “downgraded”
frames may only use the shared pool or the per-source reserved pool in the FDB; frames from flow control
enabled sources may not use reserved FDB slots for the highest six classes (P2-P7).
The MVTX2804 does provide a system-wide option of permitting normal QoS scheduling (and buffer use) for
frames originating from flow control enabled ports. When this programmable option is active, it is possible that
some packets may be dropped, even though flow control is on. The reason is that intelligent packet dropping is
a major component of the MVTX2804's approach to ensuring bounded delay and minimum bandwidth for high
priority flows.
7.9.1
Unicast Flow Control
For unicast frames, flow control is triggered by source port resource availability. Recall that the MVTX2804's
buffer management scheme allocates a reserved number of FDB slots for each source port. If a programmed
number of a source port's reserved FDB slots have been used, then flow control Xoff is triggered. Xon is
triggered when a port is currently being flow controlled, and all of that port's reserved FDB slots have been
released.
Note that the MVTX2804's per-source-port FDB reservations assure that a source port that sends a single
frame to a congested destination will not be flow controlled.
7.9.2
Multicast Flow Control
In unmanaged mode, a global buffer counter triggers flow control for multicast frames. When the system
exceeds a programmable threshold of multicast packets, Xoff is triggered. Xon is triggered when the system
returns below this threshold. MCC register programs the threshold.
In managed mode, per-VLAN flow control is used for multicast frames. In this case, flow control is triggered by
congestion at the destination. The MVTX2804 checks each destination to which a multicast packet is headed.
For each destination port, the occupancy of the lowest-priority transmission queue (measured in number of
frames) is compared against a programmable congestion threshold. If congestion is detected at even one of the
packet's destinations, then Xoff is triggered.
In addition, each source port has an 8-bit port map recording which port or ports of the multicast frame's fanout
were congested at the time Xoff was triggered. All ports are continuously monitored for congestion, and a port is
identified as uncongested when its queue occupancy falls below a fixed threshold. When all those ports that
were originally marked as congested in the port map have become uncongested, then Xon is triggered, and the
8-bit vector is reset to zero.
The MVTX2804 also provides the option of disabling multicast flow control.
Note: If port flow control is on, QoS performance will be affected.
7.10
Mapping to IETF Diffserv Classes
The mapping between priority classes discussed in this chapter and elsewhere is shown below.
MVTX2804
IETF
P7
P6
P5
P4
P3
P2
P1
P0
NM
EF
AF0
AF1
AF2
AF3
BE0
BE1
Table 4 - Mapping between MVTX2804 and IETF Diffserv Classes for Gigabit Ports
As the table illustrates, P7 is used solely for network management (NM) frames. P6 is used for expedited
forwarding service (EF). Classes P2 through P5 correspond to an assured forwarding (AF) group of size 4.
Finally, P0 and P1 are two best effort (BE) classes.
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MVTX2804
Data Sheet
Features of the MVTX2804 that correspond to the requirements of their associated IETF classes are
summarized in the table below.
Network management (NM)
and Expedited forwarding (EF)
•
•
•
•
Global buffer reservation for NM and EF
Shaper for EF traffic
Option of strict priority scheduling
No dropping if admission controlled
Assured forwarding (AF)
•
•
•
Four AF classes
Programmable bandwidth partition, with option of WFQ service
Option of delay-bounded service keeps delay under fixed levels even if
not admission-controlled
Random early discard, with programmable levels
Global buffer reservation for each AF class
•
•
Best effort (BE)
•
•
•
•
Two BE classes
Service only when other queues are idle means that QoS not adversely
affected
Random early discard, with programmable levels
Traffic from flow control enabled ports automatically classified as BE
Figure 6 - MVTX2804 Features Enabling IETF Diffserv Standards
8.0
Port Trunking
8.1
Features and Restrictions
A port group (i.e. trunk) can include up to 8 physical ports, but all of the ports in a group must be in the same
MVTX2804.
In managed mode, there are four trunk groups total.
In unmanaged mode, the MVTX2804 provides several pre-assigned trunk group options, containing as many as
4 ports per group, or alternatively, as many as 4 total groups.
Load distribution among the ports in a trunk for unicast is performed using hashing based on source MAC
address and destination MAC address. The other options include source MAC address only, destination MAC
address only. Load distribution for multicast is performed similarly.
If a VLAN includes any of the ports in a trunk group, all the ports in that trunk group should be in the same VLAN
member map.
The MVTX2804 also provides a safe fail-over mode for port trunking automatically. If one of the ports in the
trunking group goes down, the MVTX2804 will automatically redistribute the traffic over to the remaining ports in
the trunk in unmanaged mode. In managed mode, the software can perform similar tasks.
8.2
Unicast Packet Forwarding
The search engine finds the destination MCT entry, and if the status field says that the destination address
found belongs to a trunk, then the group number is retrieved instead of the port number. In addition, if the
source address belongs to a trunk, then the source port's trunk membership register is checked to determine if
the address has moved.
A hash key is used to determine the appropriate forwarding port, based on some combination of the source and
destination MAC addresses for the current packet.
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MVTX2804
Data Sheet
The search engine retrieves the VLAN member ports from the VLAN index table, which consists of 4K entries.
The search engine retrieves the VLAN member ports from the ingress port's VLAN map. Based on the
destination MAC address, the search engine determines the egress port from the MCT database. If the egress
port is a member of a trunk group, the packet can be distributed to the other members of that trunk group. The
VLAN map is used to check whether the egress port is a member of the VLAN, based on the ingress port. If it is
a member, the packet is forwarded otherwise it is discarded.
8.3
Multicast Packet Forwarding
For multicast packet forwarding, the device must determine the proper set of ports from which to transmit the
packet based on the VLAN index and hash key.
Two functions are required in order to distribute multicast packets to the appropriate destination ports in a port
trunking environment.
•
•
Determining one forwarding port per group.
For multicast packets, all but one port per group, the forwarding port, must be excluded.
8.4
Preventing Multicast Packets from Looping Back to the Source Trunk
The search engine needs to prevent a multicast packet from sending to a port that is in the same trunk group
with the source port. This is because, when we select the primary forwarding port for each group, we do not
take the source port into account. To prevent this, we simply apply one additional filter, so as to block that
forwarding port for this multicast packet.
9.0
LED Interface
9.1
Introduction
The MVTX2804 LED block provides two interfaces: a serial output channel, and a parallel time-division
interface. The serial output channel provides port status information from the MVTX2804 chip in a continuous
serial stream. This means that a low cost external device must be used to decode the serial data and to drive an
LED array for display.
By contrast, the parallel time-division interface supports a glueless LED module. Indeed, the parallel interface
can directly drive low-current LEDs without any extra logic. The pin LED_PM is used to select serial or parallel
mode.
For some LED signals, the interface also provides a blinking option. Blinking may be enabled for LED signals
TxD, RxD, COL, and FC (to be described later). The pin LED_BLINK is used to enable blinking, and the blinking
frequency is around 160 ms.
9.2
Serial Mode
In serial mode, the following pins are utilized:
•
LED_SYNCO - a sync pulse that defines the boundary between status frames
•
LED_CLKO - the clock signal
•
LED_DO - a continuous serial stream of data for all status LEDs that repeats once every frame time
In each cycle (one frame of status information, or one sync pulse), 16x8 bits of data are transmitted on the
LED_DO signal. The sequence of transmission of data bits is as shown in the figure below:
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MVTX2804
Data Sheet
LE_SYNCO
LE_DO
P0
info
P1
info
P2
info
P3
info
P4
info
P5
info
P6
info
P7
info
U0
U1
U2
U3
0
1
2
3
4
5
6
7
FC
TxD
RxD
LNK
SP0
SP1
FDX
COL
U4
U5
U6
U7
LE_CLKO
Figure 7 - Timing diagram for serial mode in LED interface
The status bits shown in here are flow control (FC), transmitting data (TxD), receiving data (RxD), link up (LNK),
speed (SP0 and SP1), full duplex (FDX), and collision (COL). Note that SP[1:0] is defined as 10 for 1 Gbps, 01
for 100 Mbps, and 00 for 10 Mbps.
Also note that U0-U7 represent user-defined sub-frames in which additional status information may be
embedded. We will see later that the MVTX2804 provides registers that can be written by the CPU to indicate
this additional status information as it becomes available.
9.3
Parallel Mode
In parallel mode, the following pins are utilized:
•
LED_PORT_SEL[9:0] - indicates which of the 8 Gigabit port status bytes or 2 user-defined status bytes is
being read out
• LED_BYTEOUT_[7:0] - provides 8 bits for 8 different port status indicators. Note that these bits are active
low.
By default, the system is in parallel mode. In parallel mode, the 10 status bytes are scanned in a continuous
loop, with one byte read out per clock cycle, and the appropriate port select bit asserted.
9.4
LED Control Registers
An LED Control Register can be used for programming the LED clock rate, sample hold time, and pattern in
parallel mode.
In addition, the MVTX2804 provides 8 registers called LEDUSER[7:0] for user-defined status bytes. During
operation, the CPU can write values to these registers, which will be read out to the LED interface output (serial
or parallel). Only LEDUSER[1:0] are used in parallel mode. The content of the LEDUSER registers will be sent
out by the LED serial shift logic, or in parallel mode, a byte at a time.
Because in parallel mode there are only two user-defined registers, LEDUSER[7:2] is shared with LEDSIG[7:2].
For LEDSIG[j], where j = 2, 3, …, 6, the corresponding register is used for programming the LED pin
LED_BYTEOUT_[j]. The format is as follows:
7
COL
FDX
SP1
4
3
SP0
COL
Bits [3:0]Signal polarity:
0: do not invert polarity (high true)
1: invert polarity
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0
FDX
SP1
SP0
MVTX2804
Data Sheet
Bits [7:4]Signal select:
0: do not select
1: select the corresponding bit
For j = 2, 3, …, 5, the value of LED_BYTEOUT_[j] equals the logical AND of all selected bits. For j = 6, the
value is equal to the logical OR. Therefore, the programmable LEDSIG[5:2] registers allow any conjunctive
formula including any of the 4 status bits (COL, FDX, SP1, SP0) or their negations to be sent to the
LED_BYTEOUT_[5:2] pins. Similarly, the programmable LEDSIG[6] register allows any disjunctive formula
including any of the 4 status bits or their negations to be sent to pin LED_BYTEOUT_[6].
LEDSIG[7] is used for programming both LED_BYTEOUT_[1] and LED_BYTEOUT_[0]. As we will see, it has
other functions as well. The format is as follows:
7
GP
Bits [7]
•
RxD
TxD
4
3
FC
P6
0
RxD
TxD
FC
Global output polarity: this bit controls the output polarity of all LED_BYTEOUT_ and
LED_PORT_SEL pins. (Default 0)
- 0: do not invert polarity (LED_BYTEOUT_[7:0] are high activated; LED_PORT_SEL[9:0] are
low activated)
- 1: invert polarity (LED_BYTEOUT_[7:0] are low activated; LED_PORT_SEL[9:0] are high
activated)
Bits [6:4]
•
Signal select:
- 0: do not select
- 1: select the corresponding bit
Bit [3]
•
The value of LED_BYTEOUT_[1] equals the logical OR of all selected bits. (Default 110)
•
Polarity control of LED_BYTEOUT_[6] (Default 0)
- 0: do not invert
- 1: invert
Bits [2:0]
•
Signal select:
- 0: do not select
- 1: select the corresponding bit
•
The value of LED_BYTEOUT_[0] equals the logical OR of all selected bits. (Default 001)
10.0
Hardware Statistics Counter
10.1
Hardware Statistics Counters List
MVTX2804 hardware provides a full set of statistics counters for each Ethernet port. The CPU accesses these
counters through the CPU interface. All hardware counters are rollover counters. When a counter rolls over, the
CPU is interrupted, so that long-term statistics may be kept. The MAC detects all statistics, except for the delay
exceed discard counter (detected by buffer manager) and the filtering counter (detected by queue manager).
The following is the wrapped signal sent to the CPU through the command block.
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MVTX2804
31
30
26
25
0
Status Wrapped Signal
B[0]
0-d
B[1]
1-L
Unicast Frame Sent
B[2]
1-U
Frame Send Fail
Bytes Sent (D)
B[3]
2-I
Flow Control Frames Sent
B[4]
2-u
Non-Unicast Frames Sent
B[5]
3-d
Bytes Received (Good and Bad) (D)
B[6]
4-d
Frames Received (Good and Bad) (D)
B[7]
5-d
Total Bytes Received (D)
B[8]
6-L
Total Frames Received
B[9]
6-U
Flow Control Frames Received
B[10]
7-l
Multicast Frames Received
B[11]
7-u
Broadcast Frames Received
B[12]
8-L
Frames with Length of 64 Bytes
B[13]
8-U
Jabber Frames
B[14]
9-L
Frames with Length Between 65-127 Bytes
B[15]
9-U
Oversize Frames
B[16]
A-l
Frames with Length Between 128-255 Bytes
B[17]
A-u
Frames with Length Between 256-511 Bytes
B[18]
B-l
Frames with Length Between 512-1023 Bytes
B[19]
B-u
Frames with Length Between 1024-1528 Bytes
B[20]
C-l
Fragments
B[21]
C-U1
Alignment Error
B[22]
C-U
Undersize Frames
B[23]
D-l
CRC
B[24]
D-u
Short Event
B[25]
E-l
Collision
B[26]
E-u
Drop
B[27]
F-l
Filtering Counter
B[28]
F-U1
Delay Exceed Discard Counter
B[29]
F-U
Late Collision
B[30]
Link Status Change
B[31]
Current link status
Notation: X-Y
X:
Address in the contain memory
Y:
Size and bits for the counter
d:
L:
U:
U1:
l:
u:
Data Sheet
D Word counter
24 bits counter bit[23:0]
8 bits counter bit[31:24]
8 bits counter bit[23:16]
16 bits counter bit[15:0]
16 bits counter bit[31:16]
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10.2
IEEE 802.3 HUB Management (RFC 1213)
10.2.1
10.2.1.1
Event Counters
READABLEOCTET
Counts number of bytes (i.e. octets) contained in good valid frames received.
Frame size:≥ 64 bytes,< 1522 bytes if VLAN Tagged;
1518 bytes if not VLAN Tagged
No FCS (i.e. checksum) error
No collisions
10.2.1.2
READABLEFRAME
Counts number of good valid frames received.
Frame size:≥ 64 bytes,< 1522 bytes if VLAN Tagged;
1518 bytes if not VLAN Tagged
No FCS error
No collisions
10.2.1.3
FCSERRORS
Counts number of valid frames received with bad FCS.
Frame size:≥ 64 bytes,≤ 1522 bytes if VLAN Tagged;
1518 bytes if not VLAN Tagged
No framing error
No collisions
10.2.1.4
ALIGNMENTERRORS
Counts number of valid frames received with bad alignment (not byte-aligned).
Frame size:≥ 64 bytes,≤ 1522 bytes if VLAN Tagged;
1518 bytes if not VLAN Tagged
No framing error
No collisions
10.2.1.5
FRAMETOOLONGS
Counts number of frames received with size exceeding the maximum allowable frame size.
Frame size:≥ 64 bytes,≤ 1522 bytes if VLAN Tagged;
1518 bytes if not VLAN Tagged
FCS error:don't care
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Data Sheet
MVTX2804
Data Sheet
Framing error:don't care
No collisions
10.2.1.6
SHORTEVENTS
Counts number of frames received with size less than the length of a short event.
Frame size:≥ 64 bytes,≤ 10 bytes
FCS error:don't care
Framing error:don't care
No collisions
10.2.1.7
RUNTS
Counts number of frames received with size under 64 bytes, but greater than the length of a short event.
Frame size:≥ 10 bytes,≤ 64 bytes
FCS error:don't care
Framing error:don't care
No collisions
10.2.1.8
COLLISIONS
Counts number of collision events.
Frame size:any size
10.2.1.9
LATEEVENTS
Counts number of collision events that occurred late (after LateEventThreshold = 64 bytes).
Frame size:any size
Events are also counted by collision counter
10.2.1.10
VERYLONGEVENTS
Counts number of frames received with size larger than Jabber Lockup Protection Timer (TW3).
Frame size:> Jabber
10.2.1.11
DATARATEMISATCHES
For repeaters or HUB application only.
10.2.1.12
AUTOPARTITIONS
For repeaters or HUB application only.
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MVTX2804
10.2.1.13
Data Sheet
TOTALERRORS
Sum of the following errors:
FCS errors
Alignment errors
Frame too long
Short events
Late events
Very long events
10.3
IEEE - 802.1 Bridge Management (RFC 1286)
10.3.0.1
Event Counters
10.3.0.2
INFRAMES
Counts number of frames received by this port or segment.
Note: this counter only counts a frame received by this port if and only if it is for a protocol being processed by
the local bridge function.
10.3.0.3
OUTFRAMES
Counts number of frames transmitted by this port.
Note: this counter only counts a frame transmitted by this port if and only if it is for a protocol being processed
by the local bridge function.
10.3.0.4
INDISCARDS
Counts number of valid frames received which were discarded (i.e., filtered) by the forwarding process.
10.3.0.5
DELAYEXCEEDEDDISCARDS
Counts number of frames discarded due to excessive transmit delay through the bridge.
10.3.0.6
MTUEXCEEDEDDISCARDS
Counts number of frames discarded due to excessive size.
10.4
RMON - Ethernet Statistic Group (RFC 1757)
10.4.1
10.4.1.1
Event Counters
DROP EVENTS
Counts number of times a packet is dropped, because of lack of available resources. DOES NOT include all
packet dropping -- for example, random early drop for quality of service support.
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MVTX2804
10.4.1.2
OCTETS
Counts the total number of octets (i.e. bytes) in any frames received.
10.4.1.3
BROADCASTPKTS
Counts the number of good frames received and forwarded with broadcast address.
Does not include non-broadcast multicast frames.
10.4.1.4
MULTICASTPKTS
Counts the number of good frames received and forwarded with multicast address.
Does not include broadcast frames.
10.4.1.5
CRCALIGNERRORS
Frame size:≥ 64 bytes,< 1522 bytes if VLAN tag (1518 if no VLAN)
No collisions:
Counts number of frames received with FCS or alignment errors
10.4.1.6
UNDERSIZEPKTS
Counts number of frames received with size less than 64 bytes.
Frame size:< 64 bytes,
No FCS error
No framing error
No collisions
10.4.1.7
OVERSIZEPKTS
Counts number of frames received with size exceeding the maximum allowable frame size.
Frame size:>1522 bytes if VLAN tag (1518 bytes if no VLAN)
FCS errordon't care
Framing errordon't care
No collisions
10.4.1.8
FRAGMENTS
Counts number of frames received with size less than 64 bytes and with bad FCS.
Frame size:< 64 bytes
Framing error don't care
No collisions
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Zarlink Semiconductor Inc.
Data Sheet
MVTX2804
10.4.1.9
Data Sheet
JABBERS
Counts number of frames received with size exceeding maximum frame size and with bad FCS.
Frame size:> 1522 bytes if VLAN tag (1518 bytes if no VLAN)
Framing errordon't care
No collisions
10.4.1.10
COLLISIONS
Counts number of collision events detected.
Only a best estimate since collisions can only be detected while in transmit mode, but not while in receive
mode.
Frame size:any size
10.4.1.11
PACKET COUNT FOR DIFFERENT SIZE GROUPS
Six different size groups - one counter for each:
Pkts64Octetsfor any packet with size = 64 bytes
Pkts65to127Octetsfor any packet with size from 65 bytes to 127 bytes
Pkts128to255Octetsfor any packet with size from 128 bytes to 255 bytes
Pkts256to511Octetsfor any packet with size from 256 bytes to 511 bytes
Pkts512to1023Octetsfor any packet with size from 512 bytes to 1023 bytes
Pkts1024to1518Octetsfor any packet with size from 1024 bytes to 1518 bytes
counts both good and bad packets.
Miscellaneous Counters
In addition to the statistics groups defined in previous sections, the MVTX2804 has other statistics counters for
its own purposes. We have two counters for flow control - one counting the number of flow control frames
received, and another counting the number of flow control frames sent. We also have two counters, one for
unicast frames sent, and one for non-unicast frames sent. A broadcast or multicast frame qualifies as
non-unicast. Furthermore, we have a counter called “frame send fail.” This keeps track of FIFO under-runs, late
collisions, and collisions that have occurred 16 times.
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MVTX2804
11.0
Register Definition
11.1
Register Description
Data Sheet
Register Description Table
Register
CPU
Addr
(Hex)
Description
R/W
I2C
Addr
(Hex)
Default
Notes
0. ETHERNET Port Control Registers - Substitute [N] with Port number (0..7)
ECR1P"N"
Port Control Register 1 for Port N
(N=0-7)
000 + 2N
R/W 000+2N
c0
ECR2P"N"
Port Control Register 2 for Port N
(N=0-7)
001 + 2N
R/W 001+2N
00
ECRMISC1
Port Control Misc1
010
R/W 010
c0
ECRMISC2
Port Control Misc 2
011
R/W 011
00
GGCONTROL0
Extra Gigabit Port Control -port
0,1
012
R/W N/A
00
GGCONTROL1
Extra Gigabit Port Control -port
2,3
013
R/W N/A
00
GGCONTROL2
Extra Gigabit Port Control -port
4,5
014
R/W N/A
00
GGCONTROL3
Extra Gigabit Port Control -port
6,7
015
R/W N/A
00
ACTIVELINK
Active Link status port 7:0
016
R/W N/A
00
1. VLAN Control Registers - Substitute [N] with Port number (0..8)
AVTCL
VLAN Type Code Register Low
100
R/W 012
00
AVTCH
VLAN Type Code Register High
101
R/W 013
81
PVMAP"N"_0
Port "N" Configuration Register 0
(N=0-8)
102 + 4N
R/W 014+4N
ff
PVMAP"N"_1
Port "N" Configuration Register 1
(N=0-8)
103 + 4N
R/W 015+4N
ef
PVMAP"N"_3
Port "N" Configuration Register 3
(N=0-8)
105 + 4N
R/W 017+4N
00
PVMODE
VLAN Operating Mode
126
R/W 038
00
2. TRUNK Control Registers
TRUNK0
Trunk group 0 Member
200
R/W NA
00
TRUNK1
Trunk group 1 Member
201
R/W NA
00
TRUNK2
Trunk group 2 Member
202
R/W NA
00
TRUNK3
Trunk group 3 Member
203
R/W NA
00
SINGLE_RING
Single ring port map
204
R/W NA
Reserved
TRUNK_RING
Trunk ring port map
205
R/W NA
Reserved
TRUNK_HASH_MODE Trunk hash mode
206
R/W NA
00
TRUNK0_MODE
207
R/W 039
00
Trunk Group 0 Mode
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Zarlink Semiconductor Inc.
MVTX2804
Data Sheet
Register Description Table (continued)
Register
CPU
Addr
(Hex)
Description
R/W
I2C
Addr
(Hex)
Default
TRUNK0_HASH0
Trunk Group 0 Hash 0, 1, 2
Destination Port
208
R/W NA
08
TRUNK0_HASH1
Trunk Group 0 Hash 2, 3, 4, 5
Destination Port
209
R/W NA
82
TRUNK0_HASH2
Trunk Group 0 Hash 5, 6, 7
Destination Port
20A
R/W NA
20
TRUNK0_HASH3
Trunk Group 0 Hash 8, 9, 10
Destination Port
20B
R/W NA
08
TRUNK0_HASH4
Trunk Group 0 Hash 10, 11, 12,
13 Destination Port
20C
R/W NA
82
TRUNK0_HASH5
Trunk Group 0 Hash 13, 14, 15
Destination Port
20D
R/W NA
20
TRUNK1_MODE
Trunk Group 1 Mode
20E
R/W 03A
00
TRUNK1_HASH0
Trunk Group 1 Hash 0, 1, 2
Destination Port
20F
R/W NA
08
TRUNK1_HASH1
Trunk Group 1 Hash 2, 3, 4, 5
Destination Port
210
R/W NA
82
TRUNK1_HASH2
Trunk Group 1 Hash 5, 6, 7
Destination Port
211
R/W NA
20
TRUNK1_HASH3
Trunk Group 1 Hash 8, 9, 10
Destination Port
212
R/W NA
08
TRUNK1_HASH4
Trunk Group 1 Hash 10, 11, 12,
13 Destination
213
R/W NA
82
TRUNK1_HASH5
Trunk Group 1 Hash 13, 14, 15
Destination
214
R/W NA
20
TRUNK2_HASH0
Trunk Group 2 Hash 0, 1, 2
Destination Port
215
R/W NA
2c
TRUNK2_HASH1
Trunk Group 2 Hash 2, 3, 4, 5
Destination Port
216
R/W NA
cb
TRUNK2_HASH2
Trunk Group 2 Hash 5, 6, 7
Destination Port
217
R/W NA
b2
TRUNK2_HASH3
Trunk Group 2 Hash 8, 9, 10
Destination Port
218
R/W NA
2c
TRUNK2_HASH4
Trunk Group 2 Hash 10, 11, 12,
13 Destination Port
219
R/W NA
cb
TRUNK2_HASH5
Trunk Group 2 Hash 13, 14, 15
Destination Port
21A
R/W NA
b2
TRUNK3_HASH0
Trunk Group 3 Hash 0, 1, 2
Destination Port
21B
R/W NA
2c
TRUNK3_HASH1
Trunk Group 3 Hash 2, 3, 4, 5
Destination Port
21C
R/W NA
cb
TRUNK3_HASH2
Trunk Group 3 Hash 5, 6, 7
Destination Port
21D
R/W NA
b2
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Zarlink Semiconductor Inc.
Notes
MVTX2804
Data Sheet
Register Description Table (continued)
Register
CPU
Addr
(Hex)
Description
R/W
I2C
Addr
(Hex)
Default
TRUNK3_HASH3
Trunk Group 3 Hash 8, 9, 10
Destination Port
21E
R/W NA
2c
TRUNK3_HASH4
Trunk Group 3 Hash 10, 11, 12,
13 Destination Port
21F
R/W NA
Bc
TRUNK3_HASH5
Trunk Group 3 Hash 13, 14, 15
Destination Port
220
R/W NA
b2
Multicast_HASH00
Multicast hash result 0 mask
bit[7:0]
221
R/W NA
ff
Multicast_HASH01
Multicast hash result 1 mask
bit[7:0]
222
R/W NA
ff
Multicast_HASH02
Multicast hash result 2 mask
bit[7:0]
223
R/W NA
ff
Multicast_HASH03
Multicast hash result 3 mask
bit[7:0]
224
R/W NA
ff
Multicast_HASH04
Multicast hash result 4 mask
bit[7:0]
225
R/W NA
ff
Multicast_HASH05
Multicast hash result 5 mask
bit[7:0]
226
R/W NA
ff
Multicast_HASH06
Multicast hash result 6 mask
bit[7:0]
227
R/W NA
ff
Multicast_HASH07
Multicast hash result 7 mask
bit[7:0]
228
R/W NA
ff
Multicast_HASH08
Multicast hash result 8 mask
bit[7:0]
229
R/W NA
ff
Multicast_HASH09
Multicast hash result 9 mask
bit[7:0]
22A
R/W NA
fff
Multicast_HASH10
Multicast hash result 10 mask
bit[7:0]
22B
R/W NA
ff
Multicast_HASH11
Multicast hash result 11 mask
bit[7:0]
22C
R/W NA
ff
Multicast_HASH12
Multicast hash result 12 mask
bit[7:0]
22D
R/W NA
ff
Multicast_HASH13
Multicast hash result 13 mask
bit[7:0]
22E
R/W NA
ff
Multicast_HASH14
Multicast hash result 14 mask
bit[7:0]
22F
R/W NA
ff
Multicast_HASH15
Multicast hash result 15 mask
bit[7:0]
230
R/W NA
ff
Multicast_HASHML
Multicast hash bit[8] for result 7-0 231
R/W NA
ff
Multicast_HASHMH
Multicast hash bit[8] for result
15-8
R/W NA
ff
232
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Zarlink Semiconductor Inc.
Notes
MVTX2804
Data Sheet
Register Description Table (continued)
Register
CPU
Addr
(Hex)
Description
R/W
I2C
Addr
(Hex)
Default
Notes
00
3. CPU Port Configuration
MAC0
CPU MAC Address byte 0
300
R/W
NA
MAC1
CPU MAC Address byte 1
301
R/W NA
00
MAC2
CPU MAC Address byte 2
302
R/W NA
00
MAC3
CPU MAC Address byte 3
303
R/W NA
00
MAC4
CPU MAC Address byte 4
304
R/W NA
00
MAC5
CPU MAC Address byte 5
305
R/W NA
00
INT_MASK0
Interrupt Mask 0
306
R/W NA
ff
INT_MASK1
Interrupt Mask 1
307
R/W NA
ff
INT_MASK2
Interrupt Mask 2
308
R/W NA
ff
INT_MASK3
Interrupt Mask 3
309
R/W NA
ff
INT_STATUS0
Status of Masked Interrupt
Register0
30A
RO
NA
INT_STATUS1
Status of Masked Interrupt
Register1
30B
RO
NA
INTP_MASK"N"
Interrupt Mask for MAC Port 2n,
2n+1 ( n=0-3)
30C-30F
R/W NA
ff
RQS
Receive Queue Select
310
R/W NA
00
RQSS
Receive Queue Status
311
RO
TX_AGE
Transmission Queue Aging Time
312
R/W 03B
08
NA
4. Search Engine Configurations
AGETIME_LOW
MAC Address Aging Time Low
400
R/W 03C
2c
AGETIME_HIGH
MAC Address Aging Time High
401
R/W 03D
00
V_AGETIME
VLAN to Port Aging Time
402
R/W NA
ff
SE_OPMODE
Search Engine operation mode
403
R/W NA
00
SCAN
Scan Control Register
404
R/W NA
00
5. Buffer Control and QOS Control
FCBAT
FCB Aging Timer
500
R/W 03E
ff
QOSC
QOS Control
501
R/W 03F
00
FCR
Flooding Control Register
502
R/W 040
08
AVPML
VLAN Priority Map Low
503
R/W 041
88
AVPMM
VLAN Priority Map Middle
504
R/W 042
c6
AVPMH
VLAN Priority Map High
505
R/W 043
fa
TOSPML
TOS Priority Map Low
506
R/W 044
88
TOSPMM
TOS Priority Map Middle
507
R/W 045
c6
TOSPMH
TOS Priority Map High
508
R/W 046
fa
AVDM
VLAN Discard Map
509
R/W 047
00
TOSDML
TOS Discard Map
50A
R/W 048
00
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MVTX2804
Data Sheet
Register Description Table (continued)
Register
CPU
Addr
(Hex)
Description
R/W
I2C
Addr
(Hex)
Default
BMRC
Broadcast/Multicast Rate Control 50B
R/W 049
00
UCC
Unicast Congestion Control
50C
R/W 04A
07
MCC
Multicast Congestion Control
50D
R/W 04B
48
PR100
Port Reservation for 10/100
Ports
50E
R/W 04C
00
PRG
Port Reservation for Giga Ports
50F
R/W 04D
26
SFCB
Share FCB Size
510
R/W 04E
37
C2RS
Class 2 Reserved Size
511
R/W 04F
00
C3RS
Class 3 Reserved Size
512
R/W 050
00
C4RS
Class 4 Reserved Size
513
R/W 051
00
C5RS
Class 5 Reserved Size
514
R/W 052
00
C6RS
Class 6 Reserved Size
515
R/W 053
00
C7RS
Class 7 Reserved Size
516
R/W 054
00
QOSC"N"
QOS Control (N=0 - 2F)
517-546
R/W 055-084
QOSC"N"
QOS Control (N=30 - 82)
547-599
R/W NA
RDRC0
WRED Rate Control 0
59A
R/W 085
8e
RDRC1
WRED Rate Control 1
59B
R/W 086
68
6. MISC Configuration Registers
MII_OP0
MII Register Option 0
600
R/W 0B1
00
MII_OP1
MII Register Option 1
601
R/W 0B2
00
FEN
Feature Registers
602
R/W 0B3
10
MIIC0
MII Command Register 0
603
R/W N/A
00
MIIC1
MII Command Register 1
604
R/W N/A
00
MIIC2
MII Command Register 2
605
R/W N/A
00
MIIC3
MII Command Register 3
606
R/W N/A
00
MIID0
MII Data Register 0
607
RO
N/A
00
MIID1
MII Data Register 1
608
RO
N/A
00
LED
LED Control Register
609
R/W 0B4
38
CHECKSUM
EEPROM Checksum Register
60B
R/W 0C5
00
LEDUSER0
LED User Define Register 0
60C
R/W 0BB
00
LEDUSER1
LED User Define Register 1
60D
R/W 0BC
00
LEDUSER2
LED User Define Reg.
2/LED_byte pin 2
60E
R/W 0BD
80
LEDUSER3
LED User Define Reg.
3/LED_byte pin 3
60F
R/W 0BE
33
LEDUSER4
LED User Define Reg.
4/LED_byte pin 4
610
R/W 0BF
32
LEDUSER5
LED User Define Reg.
5/LED_byte pin 5
611
R/W 0C0
20
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Notes
MVTX2804
Data Sheet
Register Description Table (continued)
Register
CPU
Addr
(Hex)
Description
R/W
I2C
Addr
(Hex)
Default
LEDUSER6
LED User Define Reg.
6/LED_byte pin 6
612
R/W 0C1
40
LEDUSER7
LED User Define Reg.
7/LED_byte pin 1 & 0
613
R/W 0C2
61
MIINP0
MII NEXT PAGE DATA
REGISTER0
614
R/W 0C3
00
MIINP1
MII NEXT PAGE DATA
REGISTER1
615
R/W 0C4
00
DTSRL
Test Register Low
E00
R/W N/A
00
DTSRM
Test Register Medium
E01
R/W N/A
01
DTSRH
Test Register High
E02
R/W N/A
00
TDRB0
TEST MUX read back register
[7:0]
E03
RO
N/A
TDRB1
TEST MUX read back register
[15:8]
E04
RO
N/A
DTCR
Test Counter Register
E05
R/W N/A
00
MASK0
MASK Timeout 0
E06
R/W 0B6
00
MASK1
MASK Timeout 1
E07
R/W 0B7
00
MASK2
MASK Timeout 2
E08
R/W 0B8
00
MASK3
MASK Timeout 3
E09
R/W 0B9
00
MASK4
MASK Timeout 4
E0A
R/W 0BA
00
00
Notes
E. Test Group Control
F. Device Configuration Register
GCR
Global Control Register
F00
R/W N/A
DCR
Device Status and Signature
Register
F01
RO
N/A
DCR01
Gigabit Port0 Port1 Status
Register
F02
RO
NA
DCR23
Gigabit Port2 Port3 Status
Register
F03
RO
NA
DCR45
Gigabit Port4 Port5 Status
Register
F04
RO
NA
DCR67
Gigabit Port6 Port7 Status
Register
F05
RO
NA
DPST
Device Port Status Register
F06
R/W N/A
DTST
Data read back register
F07
RO
PLLCR
PLL Control Register
F08
R/W N/A
Reserved
LCLKCR
LCLK Control Register
F09
R/W N/A
Reserved
BCLKCR
BCLK Control Register
F0A
R/W N/A
Reserved
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00
N/A
MVTX2804
Data Sheet
Register Description Table (continued)
Register
Default
Notes
F0B
RO
N/A
Reserved
BSTRRB1
BOOT STRAP read back register
1
F0C
RO
N/A
Reserved
BSTRRB2
BOOT STRAP read back register
2
F0D
RO
N/A
Reserved
BSTRRB3
BOOT STRAP read back register
3
F0E
RO
N/A
Reserved
BSTRRB4
BOOT STRAP read back register
4
F0F
RO
N/A
Reserved
BSTRRB5
BOOT STRAP read back register
5
F10
RO
N/A
Reserved
DA
DA Register
FFF
RO
N/A
1:
2:
3:
4:
5:
11.2.1
se = Search Engine
fe = Frame Engine
pgs = Port Group01, 23, 45, and 67
mc = MAC Control
tm = timer
Directly Accessed Registers
INDEX_REG0
Address bits [7:0] for indirectly accessed register addresses
Address = 0 (write only)
11.2.2
INDEX_REG1 (only needed for CPU 8-bit bus mode)
Address bits [15:8] for indirectly accessed register addresses
Address = 1 (write only)
11.2.3
•
•
I2C
Addr
(Hex)
BOOT STRAP read back register
0
11.2
•
•
R/W
BSTRRB0
Note
Note
Note
Note
Note
•
•
CPU
Addr
(Hex)
Description
DATA_FRAME_REG
Data of indirectly accessed registers. (8 bits)
Address = 2 (read/write)
11.2.4
CONTROL_FRAME_REG
• CPU transmit/receive switch frames. (8/16 bits)
• Address = 3 (read/write)
• Format: (see processor interface application note for more information)
- Send frame from CPU: (In sequence)
Frame Data (size should be in multiple of 8-byte)
8-byte of Frame status (Frame size, Destination port #, Frame O.K. status)
- CPU Received frame: (In sequence)
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DA
MVTX2804
Data Sheet
8-byte of Frame status (Frame size, Source port #, VLAN tag)
Frame Data
11.2.5
COMMAND & STATUS
•
CPU interface commands (write) and status
•
Address = 4 (read/write)
•
When the CPU reads this register:
•
-
Bit [0]: Transmit Control Command 1 Ready; Must read true before CPU writes new Control Command 1.
-
Bit [1]: Receive Control Command 1 Ready; Must read true before CPU reads a new Control Command 1.
-
Bit [2]: Receive Control Command 2 Ready; Must read true before CPU reads a new Control Command 2.
-
Bit [3]: Receive CPU Frame Ready; Must read true before receiving a CPU frame and at every 8-byte
boundary within a CPU frame.
-
Bit [4]: Transmit CPU Frame Ready; Must read true before transmitting a CPU frame and at every 16-byte
boundary within a CPU frame.
-
Bit [5]: End of Receive CPU Frame to indicate that the last 8 bytes need to be read.
-
Bit [15:6]: Reserved.
When the CPU writes to this register:
- Bit [0]: End of Transmit Control Command indicator; Set after CPU writes a Control Command Frame into Rx
buffer.
-
Bit [1]: End of Receive Control Command 1 indicator; Set after CPU reads out a Control Command 1 Frame
from Tx buffer 1.
-
Bit [2]: End of Receive Control Command 2 indicator; Set after CPU reads out a Control Command 2 Frame
from Tx buffer 2.
-
Bit [3]: End of Receive CPU Frame indicator. Set after CPU reads out a CPU frame or to flush out the rest of
CPU frame.
-
Bit [4]: End of Transmit CPU Frame indicator. Set before writing the last byte of CPU frame.
-
Bit [7:5]: Reserved and always write 0's.
-
Bit [15:8]: Reserved and write 0's in 16-bit mode.
11.2.6
Interrupt Register
•
Interrupt sources (8 bits)
•
Address = 5 (read only)
•
When CPU reads this register
Bit [0]: ·CPU frame interrupt
Bit [1]:·Control Frame 1 interrupt. Control Frame receive buffer1 has data for CPU to read
Bit [2]:·Control Frame 2 interrupt. Control Frame receive buffer2 has data for CPU to read
Bit [3]··From any of the gigabit port interrupt
Bit [7:4]:·Reserve
Note: This register is not self-cleared. After reading CPU has to clear the bit writing 0 to it
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11.2.7
Data Sheet
Control Frame Buffer1 Access Register
•
Address = 6 (read/write)
•
When CPU writes to this register, data is written to the Control Command Frame Receive Buffer
•
When CPU reads this register, data is read from the Control Command Frame Transmit Buffer1
11.2.8
•
•
Control Frame Buffer2 Access Register
Address = 7 (read only)
When CPU reads this register, data is read from the Control Command Frame transmit Buffer 2
Indirectly Accessed Registers
11.3
Group 0 Address
11.3.1
11.3.1.1
•
•
MAC Ports Group
ECR1PN: PORT N CONTROL REGISTER
I2C Address h00+2n; CPU Address:h000+2n (n=0 to 7)
Accessed by CPU, serial interface and I2C (R/W)
7
6
5
Sp State
Bit [4:0]
•
4
3
2
A-FC
1
0
Port Mode
Port Mode (Default 2'b00)
Bit [4:3]
• 00 - Automatic Enable Auto-Negotiation - This enables hardware state machine for auto-negotiation.
• 01 - Limited Disable auto-Negotiation - This disables hardware auto-negotiation. Hardware only Polls
MII for link status. Use bit [2:0] for config.
• 10 - Link Down - Force link down (disable the port). Does not talk to PHY.
• 11 - Link Up - Does not talk to PHY. User ERC1 [2:0] for config.
Bit [2]
• 1 - 10Mbps (Default 1'b0)
• 0 - 100Mbps
Bit 2 is used only when the port is in MII mode.
Bit [1]
• 1 - Half Duplex (Do not use) (Default 1'b0)
• 0 - Full Duplex
Bit [0]
• 1 - Flow Control Off (Default 1'b0)
• 0 - Flow Control On
• When flow control is on:
• In full duplex mode, the MAC transmitter sends Flow Control Frames when necessary. The MAC
receiver interprets and processes incoming flow control frames. The Flow Control Frame Received
counter is incremented whenever a flow control frame is received.
• When flow control is off:
• In full duplex mode, the MAC transmitter does not send flow control frames. The MAC receiver does not
interpret or process the flow control frames. The Flow Control Frame Receiver counter is not
incremented.
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Bit [5]
•
Data Sheet
Asymmetric Flow Control Enable.
• 0 - Disable asymmetric flow control
• 1 - Enable asymmetric flow control
Bit [7:6]
•
When this bit is set, and flow control is on (bit[0] = 0), don't send out a flow control frame. But
MAC receiver interprets and process flow control frames. (Default is 0)
•
SS - Spanning tree state (802.1D spanning tree protocol). (Default 2'b11)
•
•
•
•
11.3.1.2
•
•
00 - Blocking: Frame is dropped
01 - Listening:
Frame is dropped
10 - Learning:
Frame is dropped. Source MAC address is learned.
11 - Forwarding: Frame is forwarded. Source MAC address is learned.
ECR2PN: PORT N CONTROL REGISTER
I2C Address: 01+2n; CPU Address:h001+2n (n=0to7)
Accessed by CPU and serial interface (R/W):
7
6
5
3
Security EN
Bit[0]
•
2
1
0
DisL
Ftf
Futf
Filter untagged frame (Default 0)
• 0: Disable
• 1: Enable - All untagged frames from this port are discarded or follow security option when security is
enable
Bit[1]
•
Filter Tag frame (Default 0)
• 0: Disable
• 1: Enable - All tagged frames from this port are discarded or follow security option when security is
enable
Bit[2]
•
Learning Disable (Default 0)
• 0: Learning is enabled on this port
• 1: Learning is disabled on this port
Bit [5:3:]
•
Bit[7:6]
•
Reserved
Security Enable (Default 00). The MVTX2804 checks the incoming data for one of the following
conditions:
1. If the source MAC address of the incoming packet is in the MAC table and is defined as secure
address but the ingress port is not the same as the port associated with the MAC address in
the MAC table.
A MAC address is defined as secure when its entry at MAC table has static status and bit 0 is set
to 1. MAC address bit 0 (the first bit transmitted) indicates whether the address is unicast or
multicast. As source addresses are always unicast bit 0 is not used (always 0). MVTX2804
uses this bit to define secure MAC addresses.
2. If the port is set as learning disable and the source MAC address of the incoming packet is not
defined in the MAC address table.
3. If the port is configured to filter untagged frames and an untagged frame arrives or if the port is
configured to filter tagged frames and a tagged frame arrives.
If one of these three conditions occurs, the packet will be handled according to one of the following
specified options:
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MVTX2804
•
CPU installed
•
•
•
•
•
•
•
00 - Disable port security
01 - Discard violating packets
10 - Send packet to CPU and destination port
11 - Send packet to CPU only
CPU not installed
•
•
•
•
11.3.1.3
00 - Disable port security
01 - Enable port security. Port will be disabled when security violation is detected
10 - N/A
11 - N/A
ECRMISC1 - CPU PORT CONTROL REGISTER MISC1
I2C Address h10, CPU Address:h010
Access by CPU, serial interface and I2C (R/W)
7
6
5
0
SS state
Reserved
Bit [5:0]
•
Reserved
Bit [7:6]
•
SS - Spanning tree state (802.1D spanning tree protocol). (Default 2'b11)
•
•
•
•
11.3.1.4
•
•
Data Sheet
00 - Blocking: Frame is dropped
01 - Listening:
Frame is dropped
10 - Learning:
Frame is dropped. Source MAC address is learned.
11 - Forwarding: Frame is forwarded. Source MAC address is learned.
ECRMISC2 - CPU PORT CONTROL REGISTER MISC2
(I2C Address h11, CPU Address:h011)
Access by CPU, serial interface and I2C (R/W)
7
6
5
3
Security EN
Bit [0]
•
2
1
DisL
Ftf
0
Futf
Filter untagged frame (Default 0)
• 0: Disable
• 1: Enable - All untagged frames from the CPU are discarded or follow security option when security is
enable Security does not make much sense for CPU!
Bit[1]
•
Filter Tagged frame (Default 0)
• 0: Disable
• 1: Enable - All tagged frames from the CPU are discarded or follow security option when security is
enable Security does not make much sense for CPU!
Bit[2]
•
Learning Disable (Default 0)
• 1 - Learning is disabled on this port
• 0 - Learning is enabled on this port
Bit [5:3]
•
Reserved (Default 0)
Bit[7:6]
•
Security Enable (Default 2'b00)
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•
CPU installed
•
•
•
•
11.3.1.5
•
•
Data Sheet
00 - Disable port security
01 - Discard violation packet
10 - Send packet to CPU and port
11 - Send packet to CPU only
GGCONTROL 0- EXTRA GIGA PORT CONTROL
CPU Address:h012
Accessed by CPU and serial interface (R/W)
7
Bit[0]:
•
6
5
4
MII1
Rst1
3
2
1
MII0
0
Rst0
Reset GIGA port 0 Default is 0
• 0: Normal operation
• 1: Reset Gigabit port 0. Example: used when a new Why is connected (Hot swap)
Bit[1]:
•
GIGA port 0 use MII interface (10/100M) Default is 0
• 0: Gigabit port operation at 1000M mode
• 1: Gigabit port operation at 10/100M mode (MII)
Bit[3:2]:
•
Reserved - Must be '0'
Bit[4]:
•
Reset GIGA port 1 Default is 0
• 0: Normal operation
• 1: Reset Gigabit port 1. Example: used when a new Phy is connected (Hot swap)
Bit[5]:
•
GIGA port 1 use MII interface (10/100M) Default is 0
• 0: Gigabit port operation at 1000M mode
• 1: Gigabit port operation at 10/100M mode (MII)
Bit[7:6]:
11.3.1.6
•
•
•
Reserved - Must be '0'
GGCONTROL 1- EXTRA GIGA PORT CONTROL
CPU Address:h013
Accessed by CPU and serial interface (R/W)
7
Bit[0]:
•
6
5
4
MII3
Rst3
3
2
1
MII2
0
Rst2
Reset GIGA port 2 Default is 0
• 0: Normal operation
• 1: Reset Gigabit port 2. Example: used when a new Phy is connected (Hot swap)
Bit[1]:
•
GIGA port 2 use MII interface (10/100M) Default is 0
• 0: Gigabit port operation at 1000M mode
• 1: Gigabit port operation at 10/100M mode (MII)
Bit[3:2]:
•
Reserved - must be '0'
Bit[4]:
•
Reset GIGA port 3 Default is 0
• 0: Normal operation
• 1: Reset Gigabit port 3. Example: used when a new Phy is connected (Hot swap)
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Bit[5]:
•
Data Sheet
GIGA port 3 use MII interface (10/100M) Default is 0
• 0: Gigabit port operation at 1000M mode
• 1: Gigabit port operation at 10/100M mode (MII)
Bit[7:6]:
11.3.1.7
•
•
•
Reserved - Must be '0'
GGCONTROL 2- EXTRA GIGA PORT CONTROL
CPU Address:h014
Accessed by CPU and serial interface (R/W)
7
Bit[0]:
•
6
5
4
MII5
Rst5
3
2
1
MII4
0
Rst4
Reset GIGA port 4 Default is 0
• 0: Normal operation
• 1: Reset Gigabit port 4. Example: used when a new Phy is connected (Hot swap)
Bit[1]:
•
GIGA port 4 use MII interface (10/100M) Default is 0
• 0: Gigabit port operation at 1000M mode
• 1: Gigabit port operation at 10/100M mode (MII)
Bit[3:2]:
•
Reserved - Must be '0
Bit[4]:
•
Reset GIGA port 5 Default is 0
• 0: Normal operation
• 1: Reset Gigabit port 5. Example: used when a new Phy is connected (Hot swap)
Bit[5]
•
GIGA port 5 use MII interface (10/100M) Default is 0
• 0: Gigabit port operation at 1000M mode
• 1: Gigabit port operation at 10/100M mode (MII)
Bit[7:6]:
11.3.1.8
•
•
•
Reserved - Must be '0'
GGCONTROL 3- EXTRA GIGA PORT CONTROL
CPU Address:h015
Accessed by CPU and serial interface (R/W)
7
Bit[0]:
•
6
5
4
MII7
Rst7
3
2
1
MII6
0
Rst6
Reset GIGA port 6 Default is 0
• 0: Normal operation
• 1: Reset Gigabit port 6. Example: used when a new Phy is connected (Hot swap)
Bit[1]:
•
GIGA port 6 use MII interface (10/100M) Default is 0
• 0: Gigabit port operation at 1000M mode
• 1: Gigabit port operation at 10/100M mode (MII)
Bit[3:2]:
•
Reserved - Must be '0
Bit[4]:
•
Reset GIGA port 7 Default is 0
• 0: Normal operation
• 1: Reset Gigabit port 7. Example: used when a new Phy is connected (Hot swap)
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Bit[5]
•
Data Sheet
GIGA port 7 use MII interface (10/100M) Default is 0
• 0: Gigabit port operation at 1000M mode
• 1: Gigabit port operation at 10/100M mode (MII)
Bit[7:6]:
11.4
•
Reserved - Must be '0'
Group 1 Address
11.4.1
11.4.1.1
VLAN Group
AVTCL - VLAN TYPE CODE REGISTER LOW
• I2C Address h12; CPU Address:h100
• Accessed by CPU, serial interface and I 2C (R/W)
Bit[7:0]:VLANType_LOW: Lower 8 bits of the VLAN type code (Default 00)
11.4.1.2
•
•
Bit
I2C Address h13; CPU Address:h101
Accessed by CPU, serial interface and I 2C (R/W)
[7:0] VLANType_HIGH: Upper 8 bits of the VLAN type code (Default is 81)
11.4.1.3
•
•
AVTCH - VLAN TYPE CODE REGISTER HIGH
PVMAP00_0 - PORT 00 CONFIGURATION REGISTER 0
I2C Address h14, CPU Address:h102)
Accessed by CPU, serial interface and I 2C (R/W)
In Port Based VLAN Mode
This register indicates the legal egress ports. Example: A “1” on bit 7 means that packets arriving on port 0 can
be sent to port 7. A “0” on bit 7 means that any packet destined to port 7 will be discarded.
Bit[7:0]:
VLAN Mask for ports 7 to 0 (Default FF)
0 - Disable
1 - Enable
In Tag Based VLAN Mode
This is the default VLAN tag. It works with configuration register PVMAP00_1 [7:5] [3:0] to form the default
VLAN tag. If the received packed is untagged, it receives the default VLAN tag. If the packet has a VLAN ID of
0, then PVID is used to replace the packet's VLAN.
Bit[7:0]:
11.4.1.4
•
•
PVID [7:0] (Default is FF)
PVMAP00_1 - PORT 00 CONFIGURATION REGISTER 1
I2C Address h15, CPU Address:h103
Accessed by CPU, serial interface and I 2C (R/W)
In Port Based VLAN Mode
Bit[7:0]:
VLAN Mask for port 8 - CPU port (Default is FF)
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Data Sheet
In Tag Based VLAN Mode
7
5
Unitag Port Priority
4
3
0
Ultrust
PVID
Bit[3:0]:
•
PVID [11:8] (Default is F)
Bit [4]:
• Untrusted Port. (Default is 0)
This register is used to change the VLAN priority field of a packet to a predetermined priority.
• 1: VLAN priority field is changed to Bit[7:5] at ingress port
• 0: Keep VLAN priority field
Bit [7:5]:
11.4.1.5
•
Untag Port Priority (Default 7)
PVMAP00_3 - PORT 00 CONFIGURATION REGISTER 3
• I2C Address h17, CPU Address:h105
• Accessed by CPU, serial interface and I 2C (R/W)
In Port Based Mode
7
6
FP en
5
Drop
3
Default TX priority
Bit [1:0]:
Reserved (Default 0)
Bit [2]:
Force untagged out (Default 0)
2
1
FNT
IF
0
Reserved
• 0 Disable
• 1 Force untag output
All packets transmitted from this port are untagged. This register is used when this port is
connected to legacy equipment that does not support VLAN tagging.
Bit [5:3]:
Fixed Transmit priority. Used when bit[7] = 1 (Default 0)
•
•
•
•
•
•
•
•
Bit [6]:
000
001
010
011
100
101
110
111
Transmit Priority Level 0 (Lowest)
Transmit Priority Level 1
Transmit Priority Level 2
Transmit Priority Level 3
Transmit Priority Level 4
Transmit Priority Level 5
Transmit Priority Level 6
Transmit Priority Level 7 (Highest)
Fixed Discard priority (Default 0)
• 0 - Discard Priority Level 0 (Lowest)
• 1 - Discard Priority Level 7(Highest)
Bit [7]:
Enable Fix Priority (Default 0)
• 0 Disable fix priority. All frames are analyzed. Transmit Priority and Drop Priority are based on VLAN
Tag or TOS.
• 1 Transmit Priority and Discard Priority are based on values programmed in bit [6:3]
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Data Sheet
In Tag based VLAN Mode
Bit [1]:
Ingress filter enable (Default 1)
• 0 Disable - Ingress filter. Packets with VLAN not belonging to source port are forwarded if destination
port belongs to the VLAN. Symmetric VLAN.
• Enable - Packets are discarded when source port is not a VLAN member. Asymmetric VLAN.
Bit [2]:
Force untagged out (Default 1).
• 0 Disable
• 1 Force untagged output.
All packets transmitted from this port are untagged. This register is used when this port is
connected to legacy equipment that does not support VLAN tagging.
Bit [5:3]:
Fixed Transmit priority (Default 0) Used When Bit [7] = 1
•
•
•
•
•
•
•
•
Bit [6]:
000
001
010
011
100
101
110
111
Transmit Priority Level 0 (Lowest)
Transmit Priority Level 1
Transmit Priority Level 2
Transmit Priority Level 3
Transmit Priority Level 4
Transmit Priority Level 5
Transmit Priority Level 6
Transmit Priority Level 7 (Highest)
Fixed Discard priority (Default 0) Used When Bit [7] = 1
• 0 - Discard Priority Level 0 (Lowest)
• 1 Discard Priority Level 1 (Highest)
Bit [7]:
Enable Fix Priority (Default 0)
• 0 Disable fix priority. All frames are analyzed. Transmit Priority and Drop Priority are based on VLAN
Tag or TOS.
• 1 Transmit Priority and Discard Priority are based on values programmed in bit [6:3]
11.5
Port VLAN Map
PVMAP00_0,1,3 I2C Address h14,15,17; CPU Address:h102,103,105)
PVMAP01_0,1,3 I2C Address h18,19,1B; CPU Address:h106,107,109)
PVMAP02_0,1,3 I2C Address h1C,1D,1F; CPU Address:h10A, 10B,10D)
PVMAP03_0,1,3 I2C Address h20,21,23; CPU Address:h10E, 10F,111)
PVMAP04_0,1,3 I2C Address h24,25,27; CPU Address:h112, 113,115)
PVMAP05_0,1,3 I2C Address h28,29,2B; CPU Address:h116, 117,119)
PVMAP06_0,1,3 I2C Address h2C,2D,2F; CPU Address:h11A, 11B,11D)
PVMAP07_0,1,3 I2C Address h30,31,33; CPU Address:h11E, 11F,121)
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11.5.1
•
•
Data Sheet
PVMODE
I2C Address: h038, CPU Address:h126
Accessed by CPU, serial interface (R/W)
7
RO
Bit [0]:
•
6
5
4
MP
BPDU
3
DM
1
Reserved
0
Vmod
VLAN Mode (vlan_enable) (Default = 0)
• 1: Tag Based VLAN Mode
• 0: Port Based VLAN Mode
Bit [4]:
•
Disable MAC address 0
• 0: MAC address 0 is not leaned.
• 1: MAC address 0 is leaned.
Bit [5]:
•
Force BPDU as multicast frame (Default 0)
• 1: Enable.
• 0: Disable. BPDU packet is forwarded to CPU.
Bit [6]:
•
MAC/PORT
• 0: Single MAC address per system
• 1: Single MAC address per port
Bit [7]:
•
Routing option (force frame as switched frame)
• 1: Routing Frame to CPU is independent of ingress port spanning tree state
• 0: Routing Frame to CPU is dependent of ingress port spanning tree state
11.6
Group 2 Address
11.6.1
11.6.1.1
•
•
•
•
TRUNK1 - TRUNK GROUP 1 MEMBER (MANAGED MODE ONLY)
CPU Address:h201
Accessed by CPU, serial interface (R/W)
Bit [7:0] Port7-0 bit map of trunk 1. (Default 00)
11.6.1.3
•
•
•
TRUNK0 - TRUNK GROUP 0 MEMBER (MANAGED MODE ONLY)
CPU Address:h200
Accessed by CPU, serial interface (R/W)
Bit [7:0] Port7-0 bit map of trunk 0. (Default 00)
TRUNK0 provides a bitmap for trunk0 membership. Example: To trunk ports 0 and 2 in trunk group 0, bits 0
and 2 of TRUNK0 must be set to 1. All others must be cleared to “0” to indicate that they are not members of
the trunk 0.
11.6.1.2
•
•
•
Port Trunking Group
TRUNK2- TRUNK GROUP 2 MEMBER (MANAGED MODE ONLY)
CPU Address:h202
Accessed by CPU, serial interface (R/W)
Bit [7:0] Port7-0 bit map of trunk 2. (Default 00)
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11.6.1.4
•
•
•
Data Sheet
TRUNK3- TRUNK GROUP 3 MEMBER (MANAGED MODE ONLY)
CPU Address:h203
Accessed by CPU, serial interface (R/W)
Bit [7:0] Port7-0 bit map of trunk 3. (Default 00)
11.6.1.5
TRUNK_HASH_MODE - TRUNK HASH MODE
• CPU Address:h206
• Accessed by CPU, serial interface (R/W)
Hash Select. The hash selected is valid for Trunk 0, 1, 2 and 3.
7
2
1
0
Hash sel
Bit [1:0]
•
(Default 2'b00)
•
•
•
•
11.6.1.6
00 - Use Source and Destination Mac address for hashing.
01 - Use Source Mac Address for hashing.
10 - Use Destination Mac Address for hashing.
11 - Not Used.
TRUNK0_MODE - TRUNK GROUP 0 MODE (UNMANAGED MODE)
• I2C Address: h039, CPU Address:h207
• Accessed by serial interface and I2C (R/W)
Port Selection in unmanaged mode. Trunk group 0 and trunk group 1 are enable accordingly to bits [1:0] when
input pin P_D[9] = 0 (external pull down).
7
2
1
0
Port sel
Bit [1:0]
•
Port member selection for Trunk 0 and 1 in unmanaged mode (Default 2'b00)
•
•
•
•
00 - Only trunk group 0 is enable. Port 0 and 1 are used for trunk group0
01 - Only trunk group 0 is enable. Port 0,1 and 2 are used for trunk group0
10 - Only trunk group 0 is enable. Port 0,1,2 and 3 are used for trunk group0
11 - Trunk group 0 and 1 are enable. Port 0, 1 are used for trunk group0, and port 2 and 3 are used for
trunk group1
TRUNK HASH
•
•
•
•
Trunk
Trunk
Trunk
Trunk
group
group
group
group
0
1
2
3
achieve
achieve
achieve
achieve
load
load
load
load
balance
balance
balance
balance
by
by
by
by
TRUNK0_HASH0
TRUNK1_HASH0
TRUNK2_HASH0
TRUNK3_HASH0
to
to
to
to
5.
5.
5.
5.
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Zarlink Semiconductor Inc.
(only
(only
(only
(only
in
in
in
in
managed
managed
managed
managed
mode)
mode)
mode)
mode)
MVTX2804
11.6.1.7
•
•
Bit [2:0]:
•
Hash result 0 destination port number[2:0] (Default 000)
Bit [5:3]
•
Hash result 1 destination port number[2:0] (Default 001)
Bit [7:6]
•
Hash result 2 destination port number[1:0] (Default 00)
Bit [0]:
•
Hash result 2 destination port number[2] (Default 0)
Bit [3:1]:
•
Hash result 3 destination port number[2:0] (Default 001)
Bit [6:4]:
•
Hash result 4 destination port number[2:0] (Default 000)
Bit [7]:
•
Hash result 5 destination port number[0] (Default 1)
Bit [1:0]:
•
Hash result 5 destination port number[2:1] (Default 00)
Bit [4:2]
•
Hash result 6 destination port number[2:0] (Default 000)
Bit [7:5]
•
Hash result 7 destination port number[2:0] (Default 001)
TRUNK0_HASH3 - TRUNK GROUP 0 HASH RESULT 8,9,10 DESTINATION PORT
NUMBER
CPU Address:h20B
Accessed by CPU, serial interface (R/W)
Bit [2:0]:
•
Hash result 8 destination port number[2:0] (Default 000)
Bit [5:3]
•
Hash result 9 destination port number[2:0] (Default 001)
Bit [7:6]
•
Hash result 10 destination port number[1:0] (Default 00)
11.6.1.11
•
•
TRUNK0_HASH2 - TRUNK GROUP 0 HASH RESULT 5,6,7 DESTINATION PORT
NUMBER
CPU Address:h20A
Accessed by CPU, serial interface (R/W)
11.6.1.10
•
•
TRUNK0_HASH1 - TRUNK GROUP 0 HASH RESULT 2,3,4,5 DESTINATION PORT
NUMBER
CPU Address:h209
Accessed by CPU, serial interface (R/W)
11.6.1.9
•
•
TRUNK0_HASH0 - TRUNK GROUP 0 HASH RESULT 0,1,2 DESTINATION PORT
NUMBER
CPU Address:h208
Accessed by CPU, serial interface (R/W)
11.6.1.8
•
•
Data Sheet
TRUNK0_HASH4 - TRUNK GROUP 0 HASH RESULT 10,11,12,13 DESTINATION PORT
NUMBER
CPU Address:h20C
Accessed by CPU, serial interface (R/W)
Bit [0]:
•
Hash result 10 destination port number[2] (Default 0)
Bit [3:1]
•
Hash result 11 destination port number[2:0] (Default 001)
Bit[6:4]
•
Hash result 12 destination port number[2:0] (Default (000)
Bit [7]
•
Hash result 13 destination port number[2:0] (Default (1)
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11.6.1.12
•
•
TRUNK0_HASH5 - TRUNK GROUP 0 HASH RESULT 13,14,15 DESTINATION PORT
NUMBER
CPU Address:h20D
Accessed by CPU, serial interface (R/W)
Bit [1:0]:
Hash result 13 destination port number[2:1] (Default 00)
Bit [4:2]
Hash result 14 destination port number[2:0] (Default 000)
Bit [7:5]
Hash result 15 destination port number[2:0] (Default 001)
11.6.1.13
•
•
•
Data Sheet
TRUNK1_MODE - TRUNK GROUP 1 MODE (UNMANAGED MODE)
I2C Address h03A; CPU Address:20E
Accessed by CPU, serial interface and I 2C (R/W)
Port Selection in unmanaged mode. Trunk group 2 and trunk group 3 are enable accordingly to bits [1:0]
when input pin P_D[10] = 0.
7
2
1
0
Port Select
Bit [1:0]:
•
Port member selection for Trunk 2 and 3 in unmanaged mode
•
•
•
•
11.6.1.14
•
•
TRUNK1_HASH0 - TRUNK GROUP 1 HASH RESULT 0, 1, 2 DESTINATION PORT
NUMBER
CPU Address:h20F
Accessed by CPU, serial interface (R/W)
Bit [2:0]:
•
Hash result 0 destination port number[2:0] (Default 000)
Bit [7:6]
•
Hash result 2 destination port number[1:0] (Default 00)
Bit [5:3]
•
Hash result 1 destination port number[2:0] (Default 001)
11.6.1.15
•
•
00 - Only trunk group 2 is enable. Port 4 and 5 are used for trunk group 2
01 - Only trunk group 2 is enable. Port 4, 5 and 6 are used for trunk group 2
10 - Only trunk group 2 is enable. Port 4, 5, 6 and 7 are used for trunk group 2
11 - Trunk group 2 and trunk group 3 are enable. Port 4 and 5 are used for trunk group 2, and port 6
and 7 are used for trunk group 3
TRUNK1_HASH1 - TRUNK GROUP 1 HASH RESULT 2, 3, 4, 5 DESTINATION PORT
NUMBER
CPU Address:h210
Accessed by CPU, serial interface (R/W)
Bit [0]:
•
Hash result 2 destination port number[2] (Default 0)
Bit [3:1
•
Hash result 3 destination port number[2:0] (Default 001)
Bit [6:4]
•
Hash result 4 destination port number[2:0] (Default 000)
Bit [7]
•
Hash result 5 destination port number[0] (Default 1)
64
Zarlink Semiconductor Inc.
MVTX2804
11.6.1.16
•
•
Bit [1:0]:
•
Hash result 5 destination port number[2:1] (Default 00)
Bit [4:2]
•
Hash result 6 destination port number[2:0] (Default 000)
Bit [7:5]
•
Hash result 7 destination port number[2:0] (Default 001)
Bit [2:0]
•
Hash result 8 destination port number[2:0] (Default 000)
Bit [5:3]
•
Hash result 9 destination port number[2:0] (Default 001)
Bit [7:6]
•
Hash result 10 destination port number[1:0] (Default 00)
Bit [0]:
•
Hash result 10 destination port number[2] (Default 0)
Bit [3:1]
•
Hash result 11 destination port number[2:0] (Default 001)
Bit [6:4]
•
Hash result 12 destination port number[2:0] (Default (000)
Bit [7]
•
Hash result 13 destination port number[0] (Default (1)
TRUNK1_HASH5 - TRUNK GROUP 1 HASH RESULT 13, 14, 15 DESTINATION PORT
NUMBER
CPU Address:h214
Accessed by CPU, serial interface (R/W)
Bit [1:0]:
•
Hash result 13 destination port number[2:1] (Default 00)
Bit [4:2]
•
Hash result 14 destination port number[2:0] (Default 000)
Bit [7:5]
•
Hash result 15 destination port number[2:0] (Default 001)
11.6.1.20
•
•
TRUNK1_HASH4- TRUNK GROUP 1 HASH RESULT 11, 12, 13 DESTINATION PORT
NUMBER
CPU Address:h213
Accessed by CPU, serial interface (R/W)
11.6.1.19
•
•
TRUNK1_HASH3 - TRUNK GROUP 1 HASH RESULT 8, 9, 10 DESTINATION PORT
NUMBER
CPU Address:h212
Accessed by CPU, serial interface (R/W)
11.6.1.18
•
•
TRUNK1_HASH2 - TRUNK GROUP 1 HASH RESULT 5, 6, 7 DESTINATION PORT
NUMBER
CPU Address:h211
Accessed by CPU, serial interface (R/W)
11.6.1.17
•
•
Data Sheet
TRUNK2_HASH0 - TRUNK GROUP 2 HASH RESULT 0, 1, 2 DESTINATION PORT
NUMBER
CPU Address:h215
Accessed by CPU, serial interface (R/W)
Bit [2:0]:
•
Hash result 0 destination port number[2:0] (Default 100)
Bit [5:3]
•
Hash result 1 destination port number[2:0] (Default 101)
Bit [7:6]
•
Hash result 2 destination port number[1:0] (Default 00)
65
Zarlink Semiconductor Inc.
MVTX2804
11.6.1.21
•
•
Bit [0]:
•
Hash result 2 destination port number[2] (Default 1)
Bit [3:1]
•
Hash result 3 destination port number[2:0] (Default 101)
Bit [6:4]
•
Hash result 4 destination port number[2:0] (Default 100)
Bit [7]
•
Hash result 5 destination port number[0] (Default 1)
Bit [1:0]:
•
Hash result 5 destination port number[2:1] (Default 10)
Bit [4:2]
•
Hash result 6 destination port number[2:0] (Default 100)
Bit [7:5]
•
Hash result 7 destination port number[2:0] (Default 101)
Bit [2:0]:
•
Hash result 8 destination port number[2:0] (Default 000)
Bit [5:3]
•
Hash result 9 destination port number[2:0] (Default 001)
Bit [7:6]
•
Hash result 10 destination port number[1:0] (Default 00)
TRUNK0_HASH3 - TRUNK GROUP 0 HASH RESULT 8,9,10 DESTINATION PORT
NUMBER
CPU Address:h20B
Accessed by CPU, serial interface (R/W)
Bit [2:0]:
•
Hash result 8 destination port number[2:0] (Default 000)
Bit [5:3]
•
Hash result 9 destination port number[2:0] (Default 001)
Bit [7:6]
•
Hash result 10 destination port number[1:0] (Default 00)
11.6.1.25
•
•
TRUNK2_HASH3 - TRUNK GROUP 2 HASH RESULT 8, 9, 10 DESTINATION PORT
NUMBER
CPU Address:h218
Accessed by CPU, serial interface (R/W)
11.6.1.24
•
•
TRUNK2_HASH2 - TRUNK GROUP 2 HASH RESULT 5, 6, 7 DESTINATION PORT
NUMBER
CPU Address:h217
Accessed by CPU, serial interface (R/W)
11.6.1.23
•
•
TRUNK2_HASH1 - TRUNK GROUP 2 HASH RESULT 2, 3, 4, 5 DESTINATION PORT
NUMBER
CPU Address:h216
Accessed by CPU, serial interface (R/W)
11.6.1.22
•
•
Data Sheet
TRUNK0_HASH4 - TRUNK GROUP 0 HASH RESULT 10,11,12,13 DESTINATION
PORT NUMBER
CPU Address:h20C
Accessed by CPU, serial interface (R/W)
Bit [0]:
•
Hash result 10 destination port number[2] (Default 0)
Bit [3:1]
•
Hash result 11 destination port number[2:0] (Default 001)
Bit[6:4]
•
Hash result 12 destination port number[2:0] (Default (000)
Bit [7]
•
Hash result 13 destination port number[2:0] (Default (1)
66
Zarlink Semiconductor Inc.
MVTX2804
11.6.1.26
•
•
TRUNK0_HASH5 - TRUNK GROUP 0 HASH RESULT 13,14,15 DESTINATION PORT
NUMBER
CPU Address:h20D
Accessed by CPU, serial interface (R/W)
Bit [1:0]:
Hash result 13 destination port number[2:1] (Default 00)
Bit [4:2]
Hash result 14 destination port number[2:0] (Default 000)
Bit [7:5]
Hash result 15 destination port number[2:0] (Default 001)
11.6.1.27
•
•
•
Data Sheet
TRUNK1_MODE - TRUNK GROUP 1 MODE (UNMANAGED MODE)
I2C Address h03A; CPU Address:20E
Accessed by CPU, serial interface and I 2C (R/W)
Port Selection in unmanaged mode. Trunk group 2 and trunk group 3 are enable accordingly to bits [1:0]
when input pin P_D[10] = 0.
7
2
1
0
Port Select
Bit [1:0]:
•
Port member selection for Trunk 2 and 3 in unmanaged mode
•
•
•
•
11.6.1.28
•
•
TRUNK1_HASH0 - TRUNK GROUP 1 HASH RESULT 0, 1, 2 DESTINATION PORT
NUMBER
CPU Address:h20F
Accessed by CPU, serial interface (R/W)
Bit [2:0]:
•
Hash result 0 destination port number[2:0] (Default 000)
Bit [7:6]
•
Hash result 2 destination port number[1:0] (Default 00)
Bit [5:3]
•
Hash result 1 destination port number[2:0] (Default 001)
11.6.1.29
•
•
00 - Only trunk group 2 is enable. Port 4 and 5 are used for trunk group 2
01 - Only trunk group 2 is enable. Port 4, 5 and 6 are used for trunk group 2
10 - Only trunk group 2 is enable. Port 4, 5, 6 and 7 are used for trunk group 2
11 - Trunk group 2 and trunk group 3 are enable. Port 4 and 5 are used for trunk group 2, and port 6
and 7 are used for trunk group 3
TRUNK1_HASH1 - TRUNK GROUP 1 HASH RESULT 2, 3, 4, 5 DESTINATION PORT
NUMBER
CPU Address:h210
Accessed by CPU, serial interface (R/W)
Bit [0]:
•
Hash result 2 destination port number[2] (Default 0)
Bit [3:1
•
Hash result 3 destination port number[2:0] (Default 001)
Bit [6:4]
•
Hash result 4 destination port number[2:0] (Default 000)
Bit [7]
•
Hash result 5 destination port number[0] (Default 1)
67
Zarlink Semiconductor Inc.
MVTX2804
11.6.1.30
•
•
Bit [1:0]:
•
Hash result 5 destination port number[2:1] (Default 00)
Bit [4:2]
•
Hash result 6 destination port number[2:0] (Default 000)
Bit [7:5]
•
Hash result 7 destination port number[2:0] (Default 001)
Bit [2:0]
•
Hash result 8 destination port number[2:0] (Default 000)
Bit [5:3]
•
Hash result 9 destination port number[2:0] (Default 001)
Bit [7:6]
•
Hash result 10 destination port number[1:0] (Default 00)
Bit [0]:
•
Hash result 10 destination port number[2] (Default 0)
Bit [3:1]
•
Hash result 11 destination port number[2:0] (Default 001)
Bit [6:4]
•
Hash result 12 destination port number[2:0] (Default (000)
Bit [7]
•
Hash result 13 destination port number[0] (Default (1)
TRUNK1_HASH5 - TRUNK GROUP 1 HASH RESULT 13, 14, 15 DESTINATION PORT
NUMBER
CPU Address:h214
Accessed by CPU, serial interface (R/W)
Bit [1:0]:
•
Hash result 13 destination port number[2:1] (Default 00)
Bit [4:2]
•
Hash result 14 destination port number[2:0] (Default 000)
Bit [7:5]
•
Hash result 15 destination port number[2:0] (Default 001)
11.6.1.34
•
•
TRUNK1_HASH4- TRUNK GROUP 1 HASH RESULT 11, 12, 13 DESTINATION PORT
NUMBER
CPU Address:h213
Accessed by CPU, serial interface (R/W)
11.6.1.33
•
•
TRUNK1_HASH3 - TRUNK GROUP 1 HASH RESULT 8, 9, 10 DESTINATION PORT
NUMBER
CPU Address:h212
Accessed by CPU, serial interface (R/W)
11.6.1.32
•
•
TRUNK1_HASH2 - TRUNK GROUP 1 HASH RESULT 5, 6, 7 DESTINATION PORT
NUMBER
CPU Address:h211
Accessed by CPU, serial interface (R/W)
11.6.1.31
•
•
Data Sheet
TRUNK2_HASH0 - TRUNK GROUP 2 HASH RESULT 0, 1, 2 DESTINATION PORT
NUMBER
CPU Address:h215
Accessed by CPU, serial interface (R/W)
Bit [2:0]:
•
Hash result 0 destination port number[2:0] (Default 100)
Bit [5:3]
•
Hash result 1 destination port number[2:0] (Default 101)
Bit [7:6]
•
Hash result 2 destination port number[1:0] (Default 00)
68
Zarlink Semiconductor Inc.
MVTX2804
11.6.1.35
•
•
Bit [0]:
•
Hash result 2 destination port number[2] (Default 1)
Bit [3:1]
•
Hash result 3 destination port number[2:0] (Default 101)
Bit [6:4]
•
Hash result 4 destination port number[2:0] (Default 100)
Bit [7]
•
Hash result 5 destination port number[0] (Default 1)
Bit [1:0]:
•
Hash result 5 destination port number[2:1] (Default 10)
Bit [4:2]
•
Hash result 6 destination port number[2:0] (Default 100)
Bit [7:5]
•
Hash result 7 destination port number[2:0] (Default 101)
Bit [2:0]:
•
Hash result 8 destination port number[2:0] (Default 000)
Bit [5:3]
•
Hash result 9 destination port number[2:0] (Default 001)
Bit [7:6]
•
Hash result 10 destination port number[1:0] (Default 00)
TRUNK2_HASH4 - TRUNK GROUP 2 HASH RESULT 10, 11, 12, 13 DESTINATION
PORT NUMBER
CPU Address:h219
Accessed by CPU, serial interface (R/W)
Bit [0]:
•
Hash result 10 destination port number[2] (Default 1)
Bit [3:1]
•
Hash result 11 destination port number[2:0] (Default 101)
Bit [6:4]
•
Hash result 12 destination port number[2:0] (Default 1000)
Bit [7]
•
Hash result 13 destination port number[2:0] (Default (1)
11.6.1.39
•
•
TRUNK2_HASH3 - TRUNK GROUP 2 HASH RESULT 8, 9, 10 DESTINATION PORT
NUMBER
CPU Address:h218
Accessed by CPU, serial interface (R/W)
11.6.1.38
•
•
TRUNK2_HASH2 - TRUNK GROUP 2 HASH RESULT 5, 6, 7 DESTINATION PORT
NUMBER
CPU Address:h217
Accessed by CPU, serial interface (R/W)
11.6.1.37
•
•
TRUNK2_HASH1 - TRUNK GROUP 2 HASH RESULT 2, 3, 4, 5 DESTINATION PORT
NUMBER
CPU Address:h216
Accessed by CPU, serial interface (R/W)
11.6.1.36
•
•
Data Sheet
TRUNK2_HASH5 - TRUNK GROUP 2 HASH RESULT 13, 14, 15 DESTINATION PORT
NUMBER
CPU Address:h21A
Accessed by CPU, serial interface (R/W)
Bit [1:0]:
•
Hash result 13 destination port number[2:1] (Default 10)
Bit [4:2]
•
Hash result 14 destination port number[2:0] (Default 100)
Bit [7:5]
•
Hash result 15 destination port number[2:0] (Default 101)
69
Zarlink Semiconductor Inc.
MVTX2804
11.6.1.40
•
•
Bit [2:0]:
•
Hash result 0 destination port number[2:0] (Default 100)
Bit [5:3]
•
Hash result 1 destination port number[2:0] (Default 101)
Bit [7:6]
•
Hash result 2 destination port number[1:0] (Default 00)
Bit [0]:
•
Hash result 2 destination port number[2] (Default 1)
Bit [3:1]
•
Hash result 3 destination port number[2:0] (Default 101)
Bit [6:4]
•
Hash result 4 destination port number[2:0] (Default 100)
Bit [7]
•
Hash result 5 destination port number[0] (Default 1)
Bit [1:0]:
•
Hash result 5 destination port number[2:1] (Default 10)
Bit [4:2]
•
Hash result 6 destination port number[2:0] (Default 100)
Bit [7:5]
•
Hash result 7 destination port number[2:0] (Default 101)
TRUNK3_HASH3 - TRUNK GROUP 3 HASH RESULT 8, 9, 10 DESTINATION PORT
NUMBER
CPU Address:h21E
Accessed by CPU, serial interface (R/W)
Bit [2:0]:
•
Hash result 8 destination port number[2:0] (Default 100)
Bit [5:3]
•
Hash result 9 destination port number[2:0] (Default 101)
Bit [7:6]
•
Hash result 10 destination port number[1:0] (Default 00)
11.6.1.44
•
•
TRUNK3_HASH2 - TRUNK GROUP 3 HASH RESULT 5, 6, 7 DESTINATION PORT
NUMBER
CPU Address:h21D
Accessed by CPU, serial interface (R/W)
11.6.1.43
•
•
TRUNK3_HASH1 - TRUNK GROUP 3 HASH RESULT 2, 3, 4, 5 DESTINATION PORT
NUMBER
CPU Address:h21C
Accessed by CPU, serial interface (R/W)
11.6.1.42
•
•
TRUNK3_HASH0 - TRUNK GROUP 3 HASH RESULT 0, 1, 2 DESTINATION PORT
NUMBER
CPU Address:h21B
Accessed by CPU, serial interface (R/W)
11.6.1.41
•
•
Data Sheet
TRUNK3_HASH4 - TRUNK GROUP 3 HASH RESULT 10, 11, 12, 13 DESTINATION
PORT NUMBER
CPU Address:h21F
Accessed by CPU, serial interface (R/W)
Bit [0]:
•
Hash result 10 destination port number[2] (Default 1)
Bit [3:1]
•
Hash result 11 destination port number[2:0] (Default 101)
Bit [6:4]
•
Hash result 12 destination port number[2:0] (Default (100)
Bit [7]
•
Hash result 13 destination port number[2:0] (Default (1)
70
Zarlink Semiconductor Inc.
MVTX2804
11.6.1.45
•
•
Data Sheet
TRUNK3_HASH5 - TRUNK GROUP 3 HASH RESULT 13, 14, 15 DESTINATION PORT
NUMBER
CPU Address:h220
Accessed by CPU, serial interface (R/W)
Bit [1:0]:
•
Hash result 13 destination port number[2:1] (Default 10)
Bit [4:2]
•
Hash result 14 destination port number[2:0] (Default 100)
Bit [7:5]
•
Hash result 15 destination port number[2:0] (Default 101)
11.6.2
Multicast Hash Registers
Multicast Hash registers are used to distribute multicast traffic. 16 + 2 registers are used to form a 16-entry
array; each entry has 9 bits, with each bit representing one port. Any port not belonging to a trunk group should
be programmed with 1. Ports belonging to the same trunk group should only have a single port set to “1” per
entry. The port set to “1” is picked to transmit the multicast frame when the hash value is met.
5
4
3
2
1
0
Port 4
Port 3
Port 2
Port 1
Port 0
6
Port 5
7
Port 6
8
Port 7
Bit
Hash Result = 0
Hash Result = 1
Hash Result = 2
...
Hash Result = 13
Hash Result = 14
Hash Result = 15
CPU Port
11.6.2.1
•
•
•
CPU Address:h221
Accessed by CPU, serial interface (R/W)
Bit [7:0]
(Default FF)
11.6.2.2
•
•
•
MULTICAST_HASH01 - MULTICAST HASH RESULT1 MASK BYTE [7:0]
CPU Address:h222
Accessed by CPU, serial interface (R/W)
Bit [7:0]
(Default FF)
11.6.2.3
•
•
•
MULTICAST_HASH00 - MULTICAST HASH RESULT0 MASK BYTE [7:0]
MULTICAST_HASH02 - MULTICAST HASH RESULT2 MASK BYTE [7:0]
CPU Address:h223
Accessed by CPU, serial interface (R/W)
Bit [7:0]
(Default FF)
71
Zarlink Semiconductor Inc.
MVTX2804
11.6.2.4
•
•
•
CPU Address:h224
Accessed by CPU, serial interface (R/W)
Bit [7:0]
(Default FF)
11.6.2.5
•
•
•
MULTICAST_HASH09 - MULTICAST HASH RESULT9 MASK BYTE [7:0]
CPU Address:h22A
Accessed by CPU, serial interface (R/W)
Bit [7:0]
(Default FF)
11.6.2.11
•
•
•
MULTICAST_HASH08 - MULTICAST HASH RESULT8 MASK BYTE [7:0]
CPU Address:h229
Accessed by CPU, serial interface (R/W)
Bit [7:0]
(Default FF)
11.6.2.10
•
•
•
MULTICAST_HASH07 - MULTICAST HASH RESULT7 MASK BYTE [7:0]
CPU Address:h228
Accessed by CPU, serial interface (R/W)
Bit [7:0]
(Default FF)
11.6.2.9
•
•
•
MULTICAST_HASH06 - MULTICAST HASH RESULT6 MASK BYTE [7:0]
CPU Address:h227
Accessed by CPU, serial interface (R/W)
Bit [7:0]
(Default FF)
11.6.2.8
•
•
•
MULTICAST_HASH05 - MULTICAST HASH RESULT5 MASK BYTE [7:0]
CPU Address:h226
Accessed by CPU, serial interface (R/W)
Bit [7:0]
(Default FF)
11.6.2.7
•
•
•
MULTICAST_HASH04 - MULTICAST HASH RESULT4 MASK BYTE [7:0]
CPU Address:h225
Accessed by CPU, serial interface (R/W)
Bit [7:0]
(Default FF)
11.6.2.6
•
•
•
MULTICAST_HASH03 - MULTICAST HASH RESULT3 MASK BYTE [7:0]
MULTICAST_HASH10 - MULTICAST HASH RESULT10 MASK BYTE [7:0]
CPU Address:h22B
Accessed by CPU, serial interface (R/W)
Bit [7:0]
(Default FF)
72
Zarlink Semiconductor Inc.
Data Sheet
MVTX2804
11.6.2.12
•
•
•
MULTICAST_HASHML - MULTICAST HASH BIT[8] FOR RESULT7-0
CPU Address:h231
Accessed by CPU, serial interface (R/W)
Bit [7:0]
(Default FF)
11.6.2.18
•
•
•
MULTICAST_HASH15 - MULTICAST HASH RESULT15 MASK BYTE [7:0]
CPU Address:h230
Accessed by CPU, serial interface (R/W)
Bit [7:0]
(Default FF)
11.6.2.17
•
•
•
MULTICAST_HASH14 - MULTICAST HASH RESULT14 MASK BYTE [7:0]
CPU Address:h22F
Accessed by CPU, serial interface (R/W)
Bit [7:0]
(Default FF)
11.6.2.16
•
•
•
MULTICAST_HASH13 - MULTICAST HASH RESULT13 MASK BYTE [7:0]
CPU Address:h22E
Accessed by CPU, serial interface (R/W)
Bit [7:0]
(Default FF)
11.6.2.15
•
•
•
MULTICAST_HASH12 - MULTICAST HASH RESULT12 MASK BYTE [7:0]
CPU Address:h22D
Accessed by CPU, serial interface (R/W)
Bit [7:0]
(Default FF)
11.6.2.14
•
•
•
MULTICAST_HASH11 - MULTICAST HASH RESULT11 MASK BYTE [7:0]
CPU Address:h22C
Accessed by CPU, serial interface (R/W)
Bit [7:0]
(Default FF)
11.6.2.13
•
•
•
Data Sheet
MULTICAST_HASHML - MULTICAST HASH BIT[8] FOR RESULT 15-8
CPU Address:h232
Accessed by CPU, serial interface (R/W)
Bit [7:0]
(Default FF)
11.7
11.7.1
Group 3 Address
CPU Port Configuration Group
MAC5 to MAC0 registers form the CPU address. When a packet with destination address equal to MAC5[5:0]
arrives, it is forwarded to the CPU.
(MC bit)
MAC5
MAC4
MAC3
MAC2
73
Zarlink Semiconductor Inc.
MAC1
MAC0
MVTX2804
11.7.1.1
•
•
•
MAC4 - CPU MAC ADDRESS BYTE 4
CPU Address:h304
Accessed by CPU
Bit [7:0] Byte 4 of the CPU MAC address. (Default 8'00)
11.7.1.6
•
•
•
MAC3 - CPU MAC ADDRESS BYTE 3
CPU Address:h303
Accessed by CPU
Bit [7:0] Byte 3 of the CPU MAC address. (Default 8'00)
11.7.1.5
•
•
•
MAC2 - CPU MAC ADDRESS BYTE 2
CPU Address:h302
Accessed by CPU
Bit [7:0] Byte 2 of the CPU MAC address. (Default 8'00)
11.7.1.4
•
•
•
MAC1 - CPU MAC ADDRESS BYTE 1
CPU Address:h301
Accessed by CPU
Bit [7:0] Byte 1 of the CPU MAC address. (Default 8'00)
11.7.1.3
•
•
•
MAC0 - CPU MAC ADDRESS BYTE 0
CPU Address:h300
Accessed by CPU
Bit [7:0] Byte 0 of the CPU MAC address. (Default 8'00)
11.7.1.2
•
•
•
Data Sheet
MAC5 - CPU MAC ADDRESS BYTE 5
CPU Address:h305
Accessed by CPU
Bit [7:0] Byte 5 of the CPU MAC address. (Default 8'00). These registers form the CPU MAC address
11.7.1.7
INT_MASK0 - INTERRUPT MASK 0
• CPU Address:h306
• Accessed by CPU, serial interface (R/W)
• Mask off the interrupt source
The CPU can dynamically mask the interruption when it is busy and doesn't want to be interrupted
Bit [0]:
•
CPU frame interrupt. CPU frame buffer has data for CPU to read (Default 1'b1)
Bit [1]:
•
Control Command Frame 1 interrupt. Control Command Frame buffer1 has data for
CPU to read (Default 1'b1)
Bit [2]:
•
Control Command Frame 2 interrupt. Control Command Frame buffer2 has data for
CPU to read (Default 1'b1)
Bit [7:3]:
•
Reserved
•
•
1 - Mask the interrupt
0 - Unmask the interrupt (Enable interrupt)
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11.7.1.8
•
•
•
INT_MASK1 - INTERRUPT MASK 1
CPU Address:h307
Accessed by CPU, serial interface (R/W)
Mark off the interrupt source
Bit [0]:
•
From Gigabit port 0 interrupt (Default 1'b1)
Bit [1]:
•
From Gigabit port 1 interrupt (Default 1'b1)
Bit [2]:
•
From Gigabit port 2 interrupt (Default 1'b1)
Bit [3]:
•
From Gigabit port 3 interrupt (Default 1'b1)
Bit [4]:
•
From Gigabit port 4 interrupt (Default 1'b1)
Bit [5]:
•
From Gigabit port 5 interrupt (Default 1'b1)
Bit [6]:
•
From Gigabit port 6 interrupt (Default 1'b1)
Bit [7]:
•
From Gigabit port 7 interrupt (Default 1'b1)
• 1 - Mask the interrupt
• 0 - Unmask the interrupt (Enable interrupt)
11.7.1.9
•
•
•
CPU Address:h30A
Access by CPU, serial interface (RO)
Indicate the source of the masked interrupt.
Bit [0]:
•
CPU frame interrupt.
Bit [1]:
•
Control Command Frame 1 interrupt.
Bit [2]:
•
Control Command Frame 2 interrupt.
Bit [3]:
•
From any of the Gigabit port interrupt.
Bit [7:4]:
•
Reserved.
11.7.1.10
•
•
•
INT_STATUS0 - MASKED INTERRUPT STATUS REGISTER0
INT_STATUS1 - MASKED INTERRUPT STATUS REGISTER1
(CPU Address:h30B)
Access by CPU, serial interface (RO)
Indicate the source of the masked interrupt.
Bit [0]:
•
From Gigabit port 0 interrupt
Bit [1]:
•
From Gigabit port 1 interrupt
Bit [2]:
•
From Gigabit port 2 interrupt
Bit [3]:
•
From Gigabit port 3 interrupt
Bit [4]:
•
From Gigabit port 4 interrupt
Bit [5]:
•
From Gigabit port 5 interrupt
Bit [6]:
•
From Gigabit port 6 interrupt
Bit [7]:
•
From Gigabit port 7 interrupt
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Data Sheet
MVTX2804
11.7.1.11
•
•
Data Sheet
INTP_MASK0 - INTERRUPT MASK FOR MAC PORT 0,1
CPU Address:h30C
Accessed by CPU, serial interface (R/W)
The CPU can dynamically mask the interruption when it is busy and doesn't want to be interrupted
7
6
5
4
3
2
1
0
P1
P0
1 - Mask the Interrupt
0 - Unmask the Interrupt (Enable interrupt)
Bit[0]: Port 0 statistic counter Wrap around interrupt mask. An interrupt is generated when a statistic counter
gets to its maximum value and wraps around. Refer to hardware statistic counter for interrupt sources. (Default
1'b1)
Bit [1]: Port 0 Link change mask. (Default 1'b1)
Bit [4]: Port 1 statistic counter Wrap around interrupt mask. (Default 1'b1)
Bit [5]: Port 1 Link change mask. (Default 1'b1)
11.7.1.12
•
•
INTP_MASK1 - INTERRUPT MASK FOR MAC PORT 2,3
CPU Address:h30D
Accessed by CPU, serial interface (R/W)
7
6
5
4
3
2
1
P3
•
•
P2
Bit [0]:
•
Port 2 WAS mask (Default 1'b1)
Bit [1]:
•
Port 2 link change mask (Default 1'b1)
Bit [4]:
•
Port 3 WAS mask (Default 1'b1)
Bit [5]:
•
Port 3 link change mask (Default 1'b1)
11.7.1.13
0
INTP_MASK4 - INTERRUPT MASK FOR MAC PORT 4,5
CPU Address:h30E
Accessed by CPU, serial interface (R/W)
7
6
5
4
3
P4
2
1
0
P5
Bit [0]:
•
Port 4 WAS mask (Default 1'b1)
Bit [1]:
•
Port 4 link change mask (Default 1'b1)
Bit [4]:
•
Port 5 WAS mask (Default 1'b1)
Bit [5]:
•
Port 5 link change mask (Default 1'b1)
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11.7.1.14
•
•
Data Sheet
INTP_MASK5 - INTERRUPT MASK FOR MAC PORT 6,7
CPU Address:h30F
Accessed by CPU, serial interface (R/W)
7
6
5
4
3
2
1
0
P6
Bit [0]:
•
Port 6 WAS mask (Default 1'b1)
Bit [1]·
•
Port 6 link change mask (Default 1'b1)
Bit [4]·
•
Port 7 WAS mask (Default 1'b1)
Bit [5]:
•
Port 7 link change mask (Default 1'b1)
11.7.2
•
•
•
P7
RQS - Receive Queue Select
CPU Address:h310
Accessed by CPU, serial interface (RW)
This register selects which receive queue is enable to send data to the CPU.
7
6
5
4
3
2
1
0
FQ3
FQ2
FQ1
FQ0
SQ3
SQ2
SQ1
SQ0
Bit[0]:
•
Select Queue 0. If set to one, this queue may be scheduled to CPU port. If set to zero, this
queue will be blocked. If multiple queues are selected, a strict priority will be applied. Q3> Q2>
Q1> Q0. Same applies to bits [3:1]. See QoS application note for more information.
Bit[1]:
•
Select Queue 1
Bit[2]:
•
Select Queue 2
Bit[3]:
•
Select Queue 3
Note: Strip priority applies between different selected queues (Q3>Q2>Q1>Q0)
Bit[4]:
•
Enable flush Queue 0
Bit[5]:
•
Enable flush Queue 1
Bit[6]:
•
Enable flush Queue 2
Bit[7]:
•
Enable flush Queue 3
When flush (drop frames) is enable, it starts when queue is too long or entry is too old. A queue is too long
when it reaches WRED thresholds. Queue 0 is not subject to early drop. Packets in queue 0 are dropped only
when the queue is too old. An entry is too old when it is older than the time programmed in the register TX_AGE
[5:0]. CPU can dynamically program this register reading register RQSS [7:4].
11.7.3
•
•
RQSS - Receive Queue Status
CPU Address:h311
Accessed by CPU, serial interface (RO)
7
6
5
4
3
2
1
0
LQ3
LQ2
LQ1
LQ0
NeQ3
NeQ2
NeQ1
NeQ0
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Data Sheet
CPU queue status:
Bit[3:0]:
•
Queue 3 to 0 not empty
Bit[4]:
•
Head of line entry for Queue 3 to 0 is valid for too long. CPU queue 0 has no
WRED threshold
Bit[7:5]:
•
Head of line entry for Queue 3 to 0 is valid for too long or Queue length is
longer than WRED threshold
11.7.4
•
•
TX_AGE - Tx Queue Aging timer
I2C Address: h03B;CPU Address:h312
Accessed by CPU, serial interface (RO)
7
6
5
4
0
Tx Queue Agent
Bit[4:0]:
•
Unit of 100ms (Default 8)Disable transmission queue aging if value is zero.
Bit[5]
•
Must be set to '0'
Bit[7:6]:
•
Reserved
11.8
Group 4 Address
11.8.1
11.8.1.1
•
•
•
•
Search Engine Group
AGETIME_LOW - MAC ADDRESS AGING TIME LOW
I2C Address h03C; CPU Address:h400
Accessed by CPU, serial interface and I 2C (R/W)
Bit [7:0] Low byte of the MAC address aging timer. (Default 2c)
The 2800 removes the MAC address from the data base and sends a Delete MAC Address Control
Command to the CPU. Mac address aging is enable/disable by boot strap T_D[9].
11.8.1.2
AGETIME_HIGH -MAC ADDRESS AGING TIME HIGH
• I2C Address h03D; CPU Address:h401
• Accessed by CPU, serial interface and I 2C (R/W)
• Bit [7:0]: High byte of the MAC address aging timer. (Default 00)
• Aging time is based on the following equation:
{AGETIME_HIGH,AGETIME_LOW} X (# of MAC entries X100µsec)
Note: the number of entries= 66K when T_D[5] is pull down (SRAM memory size = 512K) and 34K when T_D[5]
is pull up (SRAM memory size = 256K).
11.8.1.3
•
•
•
V_AGETIME - VLAN TO PORT AGING TIME
CPU Address:h402
Accessed by CPU (R/W)
Bit [7:0] - 2msec/unit. (Default FF)
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11.8.1.4
•
•
Data Sheet
SE_OPMODE - SEARCH ENGINE OPERATION MODE
CPU Address:h403
Accessed by CPU (R/W)
Bit [0]:
•
•
7
6
5
4
3
2
1
0
SL
DMS
ARP
DRA
DA
DRD
DRN
FL
1 - Enable fast learning mode. In this mode, the hardware learns all the new MAC addresses at
highest rate, and reports to the CPU while the hardware scans the MAC database. When the
CPU report queue is full, the MAC address is learned and marked as “Not reported”. When the
hardware scans the database and finds a MAC address marked as “Not Reported” it tries to
report it to the CPU. The scan rate must be set. SCAN Control register sets the scan rate.
(Default 0)
0 - Search Engine learns a new MAC address and sends a message to the CPU report queue. If
queue is full, the learning is temporarily halted.
Bit [1]:
•
•
Bit [2]:
Report control
•
•
Bit [3]:
1 - Disable report new VLAN port association (Default 0)
0 - Report new VLAN port association
1 - Disable report MAC address deletion (Default 0)
0 - Report MAC address deletion (MAC address is deleted from MCT after aging time)
Delete Control
• 1 - Disable aging logic from removing MAC during aging (Default 0)
• 0 - MAC address entry is removed when it is old enough to be aged.
However, a report is still sent to the CPU in both cases, when bit[2] = 0
Bit [4]:
•
•
1 - Disable report aging VLAN port association (Default 0)
0 - Enable Report aging VLAN. VLAN is not removed by hardware. The CPU needs to remove
the VLAN -port association.
Bit [5]:
•
1 - Report ARP packet to CPU (Default 0)
Bit [6]:
•
Disable MCT speedup aging (Default 0)
• 1 - Disable speedup aging when MCT resource is low.
• 0 - Enable speedup aging when MCT resource is low.
Bit [7]:
•
Slow Learning (Default 0)
• 1- Enable slow learning. Learning is temporary disabled when search demand is high
• 0 - Learning is performed independent of search demand
11.8.1.5
•
•
SCAN - SCAN CONTROL REGISTER
CPU Address:h404
Accessed by CPU (R/W)
7
6
0
R
Ratio
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Data Sheet
SCAN is used when fast learning is enabled (SE_OP MODE bit 0). It is used for setting up the report rate for newly
learned MAC addresses to the CPU.
Bit [6:0]:
•
Ratio between database scanning and aging round (Default 00)
Bit [7]:
•
Reverse the ratio between scanning round and aging round (Default 0)
Examples:
R= 0, Ratio = 0:
All aging rounds are used for aging
R= 0, Ratio = 1:
Aging and scanning in every other aging round
R= 1, Ratio = 7:
In eight rounds, one is used for scanning and seven is used for aging
R= 0, Ratio = 7:
In eight rounds, one is used for aging and seven is used for scanning
11.9
Group 5 Address
11.9.1
11.9.1.1
•
Buffer Control/QOS Group
FCBAT - FCB AGING TIMER
I2C Address h03E; CPU Address:h500
7
0
FCBAT
Bit [7:0]:
11.9.1.2
•
•
•
•
FCB Aging time. Unit of 1ms. (Default FF)
FCBAT define the aging time out interval of FCB handle
QOSC - QOS CONTROL
I2C Address h03F; CPU Address:h501
Accessed by CPU, serial interface and I 2C (R/W)
7
6
5
4
Tos-d
Tos-p
CPUQ
VF1c
3
1
0
Bit [0]:
•
QoS frame lost is OK. Priority will be available for flow control enabled source only when this bit
is set (Default 0)
Bit [4]:
•
Per VLAN Multicast Flow Control (Default 0)
• 0 - Disable
• 1 - Enable
Bit [5]:
•
CPU multicast queues size
• 0 = 16 entries
• 1 = 160 entries
Bit [6]:
•
Select TOS bits for Priority (Default 0)
• 0 - Use TOS [4:2] bits to map the transmit priority
• 1 - Use TOS [5:3] bits to map the transmit priority
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Bit [7]:
•
Data Sheet
select TOS bits for Drop (Default 0)
• 0 - Use TOS [4:2] bits to map the drop priority
• 1 - Use TOS [5:3] bits to map the drop priority
11.9.1.3
•
•
FCR - FLOODING CONTROL REGISTER
I2C Address h040; CPU Address:h502
Accessed by CPU, serial interface and I 2C (R/W)
7
6
Tos
5
4
TimeBase
3
0
U2MR
Bit [3:0]:
•
U2MR: Unicast to Multicast Rate. Units in terms of time base defined in bits [6:4]. This is used
to limit the amount of flooding traffic. The value in U2MR specifies how many packets are
allowed to flood within the time specified by bit [6:4]. To disable this function, program U2MR
to 0. (Default = 4'h8)
Bit [6:4]:
•
TimeBase: (Default = 000)
•
•
•
•
•
•
•
•
Bit [7]:
•
000 = 10us
001 = 20us
010 = 40us
011 = 80us
100 = 160us
01 = 320us
110 = 640us
111 = 10us, same as 000.
Select VLAN tag or TOS field (IP packets) to be preferentially picked to map transmit priority
and drop priority (Default = 0).
• 0 - Select VLAN tag priority field over TOS field
• 1 - Select TOS field over VLAN tag priority field
11.9.1.4
•
•
AVPML - VLAN PRIORITY MAP
I2C Address h041; CPU Address:h503
Accessed by CPU, serial interface and I 2C (R/W)
7
6
5
VP2
3
2
VP1
0
VP0
Registers AVPML, AVPMM, and AVPMH allow the eight VLAN priorities to map into eight internal level transmit
priorities. Under the internal transmit priority, “seven” is the highest priority where as “zero” is the lowest. This
feature allows the user the flexibility of redefining the VLAN priority field. For example, programming a value of
7 into bit 2:0 of the AVPML register would map packet VLAN priority) into internal transmit priority 7. The new
priority is used only inside the 2804. When the packet goes out it carries the original priority.
Bit [2:0]:
•
Mapped priority of 0 (Default 000)
Bit [5:3]:
•
Mapped priority of 1 (Default 001)
Bit [7:6]:
•
Mapped priority of 2 (Default 10)
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11.9.1.5
•
•
Data Sheet
AVPMM - VLAN PRIORITY MAP
I2C Address h042, CPU Address:h504
Accessed by CPU, serial interface and I 2C (R/W)
7
6
4
VP5
3
1
VP4
0
VP3
VP2
Map VLAN priority into eight level transmit priorities:
Bit [0]:
•
Mapped priority of 2 (Default 0)
Bit [3:1]:
•
Mapped priority of 3 (Default 011)
Bit [6:4]:
•
Mapped priority of 4 (Default 100)
Bit [7]:
•
Mapped priority of 5 (Default 1)
11.9.1.6
•
•
AVPMH - VLAN PRIORITY MAP
I2C Address h043, CPU Address:h505
Accessed by CPU, serial interface and I 2C (R/W)
7
5
4
VP2
2
1
VP6
0
VP5
Map VLAN priority into eight level transmit priorities:
Bit [1:0]:
•
Mapped priority of 5 (Default 10)
Bit [4:2]:
•
Mapped priority of 6 (Default 110)
Bit [7:5]:
•
Mapped priority of 7 (Default 111)
11.9.1.7
•
•
TOSPML - TOS PRIORITY MAP
I2C Address h044, CPU Address:h506
Accessed by CPU, serial interface and I 2C (R/W)
7
6
5
TP2
3
2
TP1
0
TP0
Map TOS field in IP packet into four level transmit priorities
Bit [2:0]:
•
Mapped priority when TOS is 0 (Default 000)
Bit [5:3]:
•
Mapped priority when TOS is 1 (Default 001)
Bit [7:6]
•
Mapped priority when TOS is 2 (Default 10)
11.9.1.8
•
•
TOSPMM - TOS PRIORITY MAP
I2C Address h045, CPU Address:h507
Accessed by CPU, serial interface and I 2C (R/W)
7
6
TP5
5
4
3
TP4
1
TP3
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0
TP2
MVTX2804
Data Sheet
Map TOS field in IP packet into four level transmit priorities
Bit [0]:
•
Mapped priority when TOS is 2 (Default 0)
Bit [3:1]:
•
Mapped priority when TOS is 3 (Default 011)
Bit [6:4]:
•
Mapped priority when TOS is 4 (Default 100)
Bit [7]:
•
Mapped priority when TOS is 5 (Default 1)
11.9.1.9
•
•
TOSPMH - TOS PRIORITY MAP
I2C Address h046, CPU Address:h508
Accessed by CPU, serial interface and I 2C (R/W)
7
5
4
2
TP7
1
TP6
0
TP5
Map TOS field in IP packet into four level transmit priorities:
Bit [1:0]:
•
Mapped priority when TOS is 5 (Default 01)
Bit [4:2]:
•
Mapped priority when TOS is 6 (Default 110)
Bit [7:5]:
•
Mapped priority when TOS is 7 (Default 111)
11.9.1.10
•
•
AVDM - VLAN DISCARD MAP
I2C Address h047, CPU Address:h509
Accessed by CPU, serial interface and I2C (R/W)
7
6
5
4
3
2
1
0
FDV7
FDV6
FDV5
FDV4
FDV3
FDV2
FDV1
FDV0
Map VLAN priority into frame discard when low priority buffer usage is above threshold. Frames with high
discard (drop) priority will be discarded (dropped) before frames with low drop priority.
•
•
0 - Low discard priority
1 - High discard priority
Bit [0]:
•
Frame discard priority for frames with VLAN transmit priority 0 (Default 0)
Bit [1]:
•
Frame discard priority for frames with VLAN transmit priority 1 (Default 0)
Bit [2]:
•
Frame discard priority for frames with VLAN transmit priority 2 (Default 0)
Bit [3]:
•
Frame discard priority for frames with VLAN transmit priority 3 (Default 0)
Bit [4]:
•
Frame discard priority for frames with VLAN transmit priority 4 (Default 0)
Bit [5]:
•
Frame discard priority for frames with VLAN transmit priority 5 (Default 0)
Bit [6]:
•
Frame discard priority for frames with VLAN transmit priority 6 (Default 0)
Bit [7]:
•
Frame discard priority for frames with VLAN transmit priority 7 (Default 0)
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11.9.1.11
•
•
Data Sheet
TOSDML - TOS DISCARD MAP
I2C Address h048, CPU Address:h50A
Accessed by CPU, serial interface and I 2C (R/W)
7
6
5
4
3
2
1
0
FDT7
FDT6
FDT5
FDT4
FDT3
FDT2
FDT1
FDT0
Map TOS into frame discard when low priority buffer usage is above threshold
Bit [0]:
Frame discard priority for frames with TOS transmit priority 0 (Default 0)
Bit [1]:
Frame discard priority for frames with TOS transmit priority 1 (Default 0)
Bit [2]:
Frame discard priority for frames with TOS transmit priority 2 (Default 0)
Bit [3]:
Frame discard priority for frames with TOS transmit priority 3 (Default 0)
Bit [4]:
Frame discard priority for frames with TOS transmit priority 4 (Default 0)
Bit [5]:
Frame discard priority for frames with TOS transmit priority 5 (Default 0)
Bit [6]:
Frame discard priority for frames with TOS transmit priority 6 (Default 0)
Bit [7]:
Frame discard priority for frames with TOS transmit priority 7 (Default 0)
11.9.2
•
•
BMRC - Broadcast/Multicast Rate Control
I2C Address h049, CPU Address:h50B)
Accessed by CPU, serial interface and I 2C (R/W)
7
4
Broadcast Rate
3
0
Multicast Rate
This broadcast and multicast rate defines for each port the number of incoming packet allowed to be forwarded
within a specified time. Once the packet rate is reached, packets will be dropped. To turn off the rate limit,
program the field to 0.
Bit [3:0]:
Multicast Rate Control Number of multicast packets allowed within the time
defined in bits 6 to 4 of the Flooding Control Register (FCR). (Default 0).
Bit [7:4]:
Broadcast Rate Control Number of broadcast packets allowed within the time
defined in bits 6 to 4 of the Flooding Control Register (FCR). (Default 0)
11.9.3
•
•
UCC - Unicast Congestion Control
I2C Address h04A, CPU Address:h50C
Accessed by CPU, serial interface and I 2C (R/W)
7
0
Unicast congest threshold
Bit [7:0]:
Number of frame count. Used for best effort dropping at B% when destination port's best effort
queue reaches UCC threshold and shared pool is all in use. Granularity 16 frame. (Default: h07)
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11.9.4
•
•
MCC - Multicast Congestion Control
I2C Address h0B7, CPU Address:h50D
Accessed by CPU, serial interface and I 2C (R/W)
7
0
FC reaction prd
Multicast congest threshold
Bit [3:0]:
In multiples of two. Used for triggering MC flow control when destination port's multicast best
effort queue reaches MCC threshold. (Default 5'h08)
Bit [4]:
Must be 0
Bit [7:5]:
Flow control reaction period. ([7:5] *4 uSec)+3 uSec (Default 3'h2).
11.9.5
•
•
Data Sheet
PRG - Port Reservation for Giga ports
I2C Address h0B9, CPU Address:h50F
Accessed by CPU, serial interface and I 2C (R/W)
7
7
7
Buffer low thd
Bit [3:0]:
0
Per source buffer Reservation
Per source buffer reservation. Define the space in the FDB reserved for each port. Expressed in
multiples of 16 packets. For each packet 1536 bytes are reserved in the memory.
Default: 4'hA for 4MB memory
4'h6 for 2MB memory
4'h3 for 1MB memory
Bits [7:4]:
Expressed in multiples of 16 packets. Threshold for dropping all best effort frames when
destination port best effort queues reach UCC threshold and shared pool is all used and source
port reservation is at or below the PRG[7:4] level. Also the threshold for initiating UC flow
control.
Default: 4'h6 for 4MB memory
4'h2 for 2MB memory
4'h1 for 1MB memory
11.9.6
11.9.6.1
•
•
FCB Reservation
SFCB - SHARE FCB SIZE
I2C Address h04E), CPU Address:h510
Accessed by CPU, serial interface and I 2C (R/W)
7
0
Shared buffer size
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Bits [7:0]:
Data Sheet
• Expressed in multiples of 8. Buffer reservation for shared pool.
(Default 4G & 4M = 8'd62)
(Default 4G & 2M = 8'd20)
(Default 4G & 1M = 8'd08
(Default 8G & 4M = 8'd150)
(Default 8G & 2M = 8'd55)
(Default 8G & 1M = 8'd25
11.9.6.2
•
•
C2RS - CLASS 2 RESERVED SIZE
I2C Address h04F, CPU Address:h511
Accessed by CPU, serial interface and I 2C (R/W)
7
0
Class 2 FCB Reservation
Bits [7:0]:
11.9.6.3
•
•
•
Buffer reservation for class 2 (third lowest priority). Granularity 2. (Default
8'h00)
C3RS - CLASS 3 RESERVED SIZE
I2C Address h050, CPU Address:h512
Accessed by CPU, serial interface and I 2C (R/W)
7
0
Class 3 FCB Reservation
Bits [7:0]:
11.9.6.4
•
•
•
Buffer reservation for class 3. Granularity 2.
(Default 8'h00)
C4RS - CLASS 4 RESERVED SIZE
I2C Address h051, CPU Address:h513
Accessed by CPU, serial interface and I 2C (R/W)
7
0
Class 4 FCB Reservation
Bits [7:0]:
11.9.6.5
•
•
•
Buffer reservation for class 4. Granularity 2.
(Default 8'h00)
C5RS - CLASS 5 RESERVED SIZE
I2C Address h052; CPU Address:h514
Accessed by CPU, serial interface and I 2C (R/W)
7
0
Class 5 FCB Reservation
Bits [7:0]:
•
Buffer reservation for class 5. Granularity 2.
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(Default 8'h00)
MVTX2804
11.9.6.6
•
•
Data Sheet
C6RS - CLASS 6 RESERVED SIZE
I2C Address h053; CPU Address:h515
Accessed by CPU, serial interface and I 2C (R/W)
7
0
Class 6 FCB Reservation
Bits [7:0]:
11.9.6.7
•
•
•
Buffer reservation for class 6 (second highest priority). Granularity 2.
(Default 8'h00)
C7RS - CLASS 7 RESERVED SIZE
I2C Address h054; CPU Address:h516
Accessed by CPU, serial interface and I 2C (R/W)
7
0
Class 7 FCB Reservation
Bits [7:0]:
11.9.7
•
Accessed by CPU; serial interface and I 2C (R/W):
QOSC00 - BYTE_C2_G0
I2C Address h055, CPU Address:h517
Bits [7:0]:
11.9.7.2
•
•
•
•
Byte count threshold for C2 queue WRED (Default 8'h28)
(1024byte/unit when Delay Bound is used)
(1024byte/unit when WFQ is used)
QOSC01 - BYTE_C3_G0
I2C Address h056, CPU Address:h518
Bits [7:0]:
11.9.7.3
•
Buffer reservation for class 7 (highest priority). Granularity 2.
Classes Byte Gigabit Port 0
11.9.7.1
•
•
•
•
•
Byte count threshold for C3 queue WRED (Default 8'h28)
(512byte/unit when Delay Bound is used)
(1024byte/unit when WFQ is used)
QOSC02 - BYTE_C4_G0
I2C Address h057, CPU Address:h519
Bits [7:0]:
•
•
•
Byte count threshold for C4 queue WRED (Default 8'h28)
(256byte/unit when Delay Bound is used)
(1024byte/unit when WFQ is used)
87
Zarlink Semiconductor Inc.
(Default 8'h00)
MVTX2804
11.9.7.4
•
QOSC03 - BYTE_C5_G0
I2C Address h058, CPU Address:h51A
Bits [7:0]:
11.9.7.5
•
•
•
•
Byte count threshold for C5 queue WRED (Default 8'h28)
(128byte/unit when Delay Bound is used)
(1024byte/unit when WFQ is used)
QOSC04 - BYTE_C6_G0
I2C Address h059, CPU Address:h51B
Bits [7:0]:
11.9.7.6
•
Data Sheet
•
•
•
Byte count threshold for C6 queue WRED (Default 8'h50)
(64byte/unit when Delay Bound is used)
(1024byte/unit when WFQ is used)
QOSC05 - BYTE_C7_G0
I2C Address h05A, CPU Address:h51C
Bits [7:0]:
•
•
•
Byte count threshold for C6 queue WRED (Default 8'h50)
(64byte/unit when Delay Bound is used)
(1024byte/unit when WFQ is used)
QOSC00 through QOSC05 represent the values F-A in Table 3 for Gigabit port 0. They are per-queue byte
thresholds for weighted random early drop (WRED). QOSC05 represents A, and QOSC00 represents F. See
QoS application note for more information.
11.9.8
•
Classes Byte Gigabit Port 1
Accessed by CPU; serial interface and I 2C (R/W):
11.9.8.1
•
QOSC06 - BYTE_C2_G1
I2C Address h05B, CPU Address:h51D
Bits [7:0]:
11.9.8.2
•
Byte count threshold for C2 queue WRED (Default 8'h28)
(1024byte/unit when Delay Bound is used)
(1024byte/unit when WFQ is used)
QOSC07 - BYTE_C3_G1
I2C Address h05C, CPU Address:h51E
Bits [7:0]:
11.9.8.3
•
•
•
•
•
•
•
Byte count threshold for C3 queue WRED (Default 8'h28)
(512 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC08 - BYTE_C4_G1
I2C Address h05D, CPU Address:h51F
Bits [7:0]:
•
•
•
Byte count threshold for C4 queue WRED (Default 8'h28)
(256 byte/unit when Delay Bound is used)
(1024byte/unit when WFQ is used)
88
Zarlink Semiconductor Inc.
MVTX2804
11.9.8.4
•
QOSC09 - BYTE_C5_G1
I2C Address h05E, CPU Address:h520
Bits [7:0]:
11.9.8.5
•
•
•
•
Byte count threshold for C5 queue WRED (Default 8'h28)
(128 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC0A - BYTE_C6_G1
I2C Address h05F, CPU Address:h521
Bits [7:0]:
11.9.8.6
•
Data Sheet
•
•
•
Byte count threshold for C6 queue WRED (Default 8'h50)
(64 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC0B - BYTE_C7_G1
I2C Address h060, CPU Address:h522
Bits [7:0]:
•
•
•
Byte count threshold for C7 queue WRED (Default 8'h50)
(64 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC06 through QOSC0B represent the values F-A in Table 3. They are per-queue byte thresholds for random
early drop. QOSC0B represents A, and QOSC06 represents F. See QoS application note for more information
11.9.9
•
Classes Byte Gigabit Port 2
Accessed by CPU; serial interface and I 2C (R/W):
11.9.9.1
•
I2C Address h061, CPU Address:h523
Bits [7:0]:
11.9.9.2
•
•
•
•
Byte count threshold for C2 queue WRED (Default 8'h28)
(1024 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC0D - BYTE_C3_G2
I2C Address h062, CPU Address:h524
Bits [7:0]:
11.9.9.3
•
QOSC0C - BYTE_C2_G2
•
•
•
Byte count threshold for C3 queue WRED (Default 8'h28)
(512 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC0E - BYTE_C4_G2
I2C Address h063, CPU Address:h525
Bits [7:0]:
•
•
•
Byte count threshold for C4 queue WRED (Default 8'h28)
(256 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
89
Zarlink Semiconductor Inc.
MVTX2804
11.9.9.4
•
11.9.9.5
•
•
•
Byte count threshold for C5 queue WRED (Default 8'h28)
(128 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC10 - BYTE_C6_G2
I2C Address h065, CPU Address:h527
Bits [7:0]:
11.9.9.6
•
QOSC0F - BYTE_C5_G2
I2C Address h064, CPU Address:h526
Bits [7:0]:
•
Data Sheet
•
•
•
Byte count threshold for C6 queue WRED (Default 8'h50)
(64 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC11 - BYTE_C7_G2
I2C Address h066, CPU Address:h528
Bits [7:0]:
•
•
•
Byte count threshold for C7 queue WRED (Default 8'h50)
(64 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC0C through QOSC11 represent the values F-A in Table 3. They are per-queue byte thresholds for random
early drop. QOSC11 represents A, and QOSC0C represents F. See QoS application note for more information
11.9.10
•
Accessed by CPU; serial interface and I2C (R/W):
11.9.10.1
•
11.9.10.2
•
•
•
Byte count threshold for C2 queue WRED (Default 8'h28)
(1024 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC13 - BYTE_C3_G3
I2C Address h068, CPU Address:h52A
Bits [7:0]:
11.9.10.3
•
QOSC12 - BYTE_C2_G3
I2C Address h067, CPU Address:h529
Bits [7:0]:
•
Classes Byte Gigabit Port 3
•
•
•
Byte count threshold for C3 queue WRED (Default 8'h28)
(512 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC14 - BYTE_C4_G3
I2C Address h069, CPU Address:h52B
Bits [7:0]:
•
•
•
Byte count threshold for C4 queue WRED (Default 8'h28)
(256 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
90
Zarlink Semiconductor Inc.
MVTX2804
11.9.10.4
•
11.9.10.5
•
•
•
Byte count threshold for C5 queue WRED (Default 8'h28)
(128 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC16 - BYTE_C6_G3
I2C Address h06B, CPU Address:h52D
Bits [7:0]:
11.9.10.6
•
QOSC15 - BYTE_C5_G3
I2C Address h06A, CPU Address:h52C
Bits [7:0]:
•
Data Sheet
•
•
•
Byte count threshold for C6 queue WRED (Default 8'h50)
(64 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC17 - BYTE_C7_G3
I2C Address h06C, CPU Address:h52E
Bits [7:0]:
•
•
•
Byte count threshold for C7 queue WRED (Default 8'h50)
(64 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC12 through QOSC17 represent the values F-A in Table 3. They are per-queue byte thresholds for random
early drop. QOSC17 represents A, and QOSC12 represents F. See QoS application note for more information
11.9.11
•
Accessed by CPU; serial interface and I 2C (R/W):
11.9.11.1
•
11.9.11.2
•
•
•
Byte count threshold for C2 queue WRED (Default 8'h28)
(1024 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC019 - BYTE_C3_G4
I2C Address h06E, CPU Address:h530
Bits [7:0]:
11.9.11.3
•
QOSC18 - BYTE_C2_G4
I2C Address h06D, CPU Address:h52F
Bits [7:0]:
•
Classes Byte Gigabit Port 4
•
•
•
Byte count threshold for C3 queue WRED (Default 8'h28)
(512 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC1A - BYTE_C4_G4
I2C Address h06F, CPU Address:h531
Bits [7:0]:
•
•
•
Byte count threshold for C4 queue WRED (Default 8'h28)
(256 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
91
Zarlink Semiconductor Inc.
MVTX2804
11.9.11.4
•
11.9.11.5
•
•
•
Byte count threshold for C5 queue WRED (Default 8'h28)
(128 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC1C - BYTE_C6_G4
I2C Address h071, CPU Address:h533
Bits [7:0]:
11.9.11.6
•
QOSC1B - BYTE_C5_G4
I2C Address h070, CPU Address:h532
Bits [7:0]:
•
Data Sheet
•
•
•
Byte count threshold for C6 queue WRED (Default 8'h28)
(64 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC1D- BYTE_C7_G4
I2C Address h072, CPU Address:h534
Bits [7:0]:
•
•
•
Byte count threshold for C7 queue WRED (Default 8'h28)
(64 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC18 through QOSC1D represent the values F-A in Table 3. They are per-queue byte thresholds for random
early drop. QOSC1D represents A, and QOSC18 represents F. See QoS application note for more information
11.9.12
•
Accessed by CPU; serial interface and I 2C (R/W):
11.9.12.1
•
11.9.12.2
•
•
•
Byte count threshold for C2 queue WRED (Default 8'h28)
(1024 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC1F - BYTE_C3_G5
I2C Address h074, CPU Address:h536
Bits [7:0]:
11.9.12.3
•
QOSC1E- BYTE_C2_G5
I2C Address h073, CPU Address:h535
Bits [7:0]:
•
Classes Byte Gigabit Port 5
•
•
•
Byte count threshold for C3 queue WRED (Default 8'h28)
(512 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC20 - BYTE_C4_G5
I2C Address h075, CPU Address:h537
Bits [7:0]:
•
•
•
Byte count threshold for C4 queue WRED (Default 8'h28)
(256 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
92
Zarlink Semiconductor Inc.
MVTX2804
11.9.12.4
•
11.9.12.5
•
•
•
Byte count threshold for C5 queue WRED (Default 8'h28)
(128 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC22 - BYTE_C6_G5
I2C Address h077, CPU Address:h539
Bits [7:0]:
11.9.12.6
•
QOSC21 - BYTE_C5_G5
I2C Address h076, CPU Address:h538
Bits [7:0]:
•
Data Sheet
•
•
•
Byte count threshold for C6 queue WRED (Default 8'h50)
(64 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC23 - BYTE_C7_G5
I2C Address h078, CPU Address:h53A
Bits [7:0]:
•
•
•
Byte count threshold for C4 queue WRED (Default 8'h50)
(64 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC1E through QOSC23 represent the values F-A in Table 3. They are per-queue byte thresholds for random
early drop. QOSC23 represents A, and QOSC1E represents F. See QoS application note for more information
11.9.13
•
Accessed by CPU; serial interface and I2C (R/W):
11.9.13.1
•
11.9.13.2
•
•
•
Byte count threshold for C2 queue WRED (Default 8'h28)
(1024 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC25 - BYTE_C3_G6
I2C Address h07A, CPU Address:h53C
Bits [7:0]:
11.9.13.3
•
QOSC24 - BYTE_C2_G6
I2C Address h079, CPU Address:h53B
Bits [7:0]:
•
Classes Byte Gigabit Port 6
•
•
•
Byte count threshold for C3 queue WRED (Default 8'h28)
(512 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC26 - BYTE_C4_G6
I2C Address h07B, CPU Address:h53D
Bits [7:0]:
•
•
•
Byte count threshold for C4 queue WRED (Default 8'h28)
(256 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
93
Zarlink Semiconductor Inc.
MVTX2804
11.9.13.4
•
11.9.13.5
•
•
•
Byte count threshold for C5 queue WRED (Default 8'h28)
(128 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC28 - BYTE_C6_G6
I2C Address h07D, CPU Address:h53F
Bits [7:0]:
11.9.13.6
•
QOSC27 - BYTE_C5_G6
I2C Address h07C, CPU Address:h53E
Bits [7:0]:
•
Data Sheet
•
•
•
Byte count threshold for C6 queue WRED (Default 8'h50)
(64 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC29 - BYTE_C7_G6
I2C Address h07E, CPU Address:h540
Bits [7:0]:
•
•
•
Byte count threshold for C7 queue WRED (Default 8'h50)
(64 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC24 through QOSC29 represent the values F-A in Table 3. They are per-queue byte thresholds for random
early drop. QOSC29 represents A, and QOSC24 represents F. See QoS application note for more information.
11.9.14
•
Accessed by CPU; serial interface and I 2C (R/W):
11.9.14.1
•
11.9.14.2
•
•
•
Byte count threshold for C2 queue WRED (Default 8'h28)
(1024 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC2B - BYTE_C3_G7
I2C Address h080, CPU Address:h542
Bits [7:0]:
11.9.14.3
•
QOSC2A - BYTE_C2_G7
I2C Address h07F, CPU Address:h541
Bits [7:0]:
•
Classes Byte Gigabit Port 7
•
•
•
Byte count threshold for C3 queue WRED (Default 8'h28)
(512 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC2C - BYTE_C4_G7
I2C Address h081, CPU Address:h543
Bits [7:0]:
•
•
•
Byte count threshold for C4 queue WRED (Default 8'h28)
(256 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
94
Zarlink Semiconductor Inc.
MVTX2804
11.9.14.4
•
1QOSC2D - BYTE_C5_G7
I2C Address h082, CPU Address:h544
Bits [7:0]:
•
•
•
11.9.14.5
•
Byte count threshold for C5 queue WRED (Default 8'h28)
(128 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC2E - BYTE_C6_G7
I2C Address h083, CPU Address:h545
Bits [7:0]:
•
•
•
11.9.14.6
•
Data Sheet
Byte count threshold for C6 queue WRED (Default 8'h50)
(64 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC2F - BYTE_C7_G7
I2C Address h084, CPU Address:h546
Bits [7:0]:
•
•
•
Byte count threshold for C5 queue WRED (Default 8'h50)
(64 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC00 through QOSC05 represent the values F-A in Table 3. They are per-queue byte thresholds for random
early drop. QOSC05 represents A, and QOSC00 represents F. See QoS application note for more information.
11.9.15
•
Classes Byte Limit CPU
Accessed by CPU; serial interface and I 2C (R/W):
11.9.15.1
•
CPU Address:h547
Bits [7:0]:
11.9.15.2
•
•
Byte count threshold for C1 queue (256byte/unit)
QOSC31 - BYTE_C02
CPU Address:h548
Bits [7:0]:
11.9.15.3
•
QOSC30 - BYTE_C01
•
Byte count threshold for C2 queue (256byte/unit)
QOSC32 - BYTE_C03
CPU Address:h549
Bits [7:0]:
•
Byte count threshold for C3 queue (256byte/unit)
QOSC30 through QOSC32 represent the values C-A for CPU port. The values A-C are per-queue byte
thresholds for random early drop. QOSC32 represents A, and QOSC30 represents C. Queue 0 does not have
weighted random drop. See QoS application note for more information.
95
Zarlink Semiconductor Inc.
MVTX2804
11.9.16
•
Data Sheet
Classes WFQ Credit Set 0
Accessed by CPU only
11.9.16.1
•
QOSC33 - CREDIT_C0_G0
CPU Address:h54A
Bits [5:0]:
•
W0 - Credit register for WFQ. (Default 6'h04)
Bits [7:6]:
•
Priority type. Define one of the four QoS mode of operation for port 0
(Default 2'00)
See table below:
•
Queue
P6
P5
P4
P3
P2
P1
Option 1 Bit [7:6] = 2'B00
DELAY BOUND
BE
Option 2 Bit [7:6] = 2'B01
SP
DELAY BOUND
BE
Option 3 Bit [7:6] = 2'B10
SP
WFQ
Option 4 Bit [7:6] = 2'B11
WFQ
Credit for WFQ - Bit [5:0]
W7
11.9.16.2
•
P7
W6
W5
W4
W3
W2
W1
P0
W0
QOSC34 - CREDIT_C1_G0
CPU Address:h54B
Bits [7]:
•
Flow control allow during WFQ scheme. (Default 1'b1)
• 0 = Not support QoS when the Source port Flow control status is on.
• 1= Always support QoS)
Bits [6]:
•
Flow control BE Queue only. (Default 1'b1)
• 0= DO NOT send any frames if the XOFF is on.
• 1= the P7-P2 frames can be sent even the XOFF is ON
Bits [5:0]
•
W1 - Credit register. (Default 4'h04)
Fc_allow
Fc_be_only
Lost_ok
Egress- for dest fc_status
Ingress- for src fc
status
0
0
0
Go to BE Queue if (Src FC or Des FC on) otherwise Normal
0
0
1
Go to BE Queue if (Dest FC on) otherwise Normal
1
0
0
(WFQ only) Go to BE Queue if (Src FC on) otherwise BAD
1
0
1
(WFQ only)
Always Normal
X
1
0
Go to BE Queue if (Src FC on)
X
1
1
Always Normal
96
Zarlink Semiconductor Inc.
MVTX2804
11.9.16.3
•
Bits [5:0]:
•
W2 - Credit register. (Default 4'h04)
Bits [7:6]:
•
Reserved
Bits [5:0]:
•
W3 - Credit register. (Default 4'h04)
Bits [7:6]:
•
Reserved
Bits [5:0]:
•
W4 - Credit register. (Default 4'h04)
Bits [7:6]:
•
Reserved
Bits [5:0]:
•
W5 - Credit register. (Default 5'h8)
Bits [7:6]:
•
Reserved
QOSC39- CREDIT_C6_G0
CPU Address:h550
Bits [5:0]:
•
W6 - Credit register. (Default 5'h8)
Bits [7:6]:
•
Reserved
11.9.16.8
•
QOSC38 - CREDIT_C5_G0
CPU Address:h54F
11.9.16.7
•
QOSC37 - CREDIT_C4_G0
CPU Address:h54E
11.9.16.6
•
QOSC36 - CREDIT_C3_G0
CPU Address:h54D
11.9.16.5
•
QOSC35 - CREDIT_C2_G0
CPU Address:h54C
11.9.16.4
•
Data Sheet
QOSC3A- CREDIT_C7_G0
CPU Address:h551
Bits [5:0]:
•
W7 - Credit register. (Default 5'h10)
Bits [7:6]:
•
Reserved
QOSC33 through QOSC3Arepresents the set of WFQ parameters (see section 7.5) for Gigabit port 0. The
granularity of the numbers is 1, and their sum must be 64. QOSC33 corresponds to W0, and QOSC3A
corresponds to W7.
11.9.17
•
Classes WFQ Credit Port G1
Access by CPU only
97
Zarlink Semiconductor Inc.
MVTX2804
11.9.17.1
•
Data Sheet
QOSC3B - CREDIT_C0_G1
CPU Address:h552
Bits [5:0]:
•
W0 - Credit register for WFQ. (Default 6'h04)
Bits [7:6]:
•
•
Priority type. Define one of the four QoS mode of operation for port 1 (Default 2'00)
See table below:
Queue
P7
P6
Option 1 Bit [7:6] = 2'B00
P5
P4
SP
P1
Option 3 Bit [7:6] = 2'B10
SP
P0
BE
DELAY BOUND
BE
WFQ
Option 4 Bit [7:6] = 2'B11
WFQ
Credit for WFQ - Bit [5:0]
•
P2
DELAY BOUND
Option 2 Bit [7:6] = 2'B01
11.9.17.2
P3
W7
W6
W5
W4
W3
W2
W1
W0
QOSC3C - CREDIT_C1_G1
CPU Address:h54B
Bits [7]:
•
Flow control allow during WFQ scheme. (Default 1'b1)
• 0 = Not support QoS when the Source port Flow control status is on.
• 1= Always support QoS)
Bits [6]:
•
Flow control BE Queue only. (Default 1'b1)
• 0= DO NOT send any frames if the XOFF is on.
• 1= the P7-P2 frames can be sent even the XOFF is ON
Bits [5:0]
•
Fc_allow
W1 - Credit register. (Default 4'h04)
Fc_be_only
Lost_ok
Egress- for dest fc_status
Ingressfor src fc
status
0
0
0
Go to BE Queue if (Src FC or Des FC on) otherwise Normal
0
0
1
Go to BE Queue if (Dest FC on) otherwise Normal
1
0
0
(WFQ only) Go to BE Queue if (Src FC on) otherwise BAD
1
0
1
(WFQ only)
Always Normal
X
1
0
Go to BE Queue if (Src FC on)
X
1
1
Always Normal
98
Zarlink Semiconductor Inc.
MVTX2804
11.9.17.3
•
Bits [5:0]:
•
W2 - Credit register. (Default 4'h04)
Bits [7:6]:
•
Reserved
Bits [5:0]:
•
W3 - Credit register. (Default 4'h04)
Bits [7:6]:
•
Reserved
Bits [5:0]:
•
W4 - Credit register. (Default 4'h04)
Bits [7:6]:
•
Reserved
Bits [5:0]:
•
W5 - Credit register. (Default 5'h8)
Bits [7:6]:
•
Reserved
QOSC41- CREDIT_C6_G1
CPU Address:h557
Bits [5:0]:
•
W6 - Credit register. (Default 5'h8)
Bits [7:6]:
•
Reserved
11.9.17.8
•
QOSC40 - CREDIT_C5_G1
CPU Address:h556
11.9.17.7
•
QOSC3F - CREDIT_C4_G1
CPU Address:h555
11.9.17.6
•
QOSC3E - CREDIT_C3_G1
CPU Address:h554
11.9.17.5
•
QOSC3D - CREDIT_C2_G1
CPU Address:h553
11.9.17.4
•
Data Sheet
QOSC42- CREDIT_C7_G1
CPU Address:h558
Bits [5:0]:
•
W7 - Credit register. (Default 5'h10)
Bits [7:6]:
•
Reserved
QOSC3B through QOSC42 represents the set of WFQ parameters (see section 7.5) for Gigabit port 1. The
granularity of the numbers is 1, and their sum must be 64. QOSC3B corresponds to W0, and QOSC42
corresponds to W7
99
Zarlink Semiconductor Inc.
MVTX2804
11.9.18
•
Classes WFQ Credit Port G2
Access by CPU only
11.9.18.1
•
QOSC43 - CREDIT_C0_G2
CPU Address:h55A
Bits [5:0]:
•
W0 - Credit register for WFQ. (Default 6'h04)
Bits [7:6]:
•
•
Priority type. Define one of the four QoS mode of operation for port 2 (Default 2'00)
See table below:
Queue
P7
P6
P5
P4
P3
P2
P1
Option 1 Bit [7:6] = 2'B00
DELAY BOUND
BE
Option 2 Bit [7:6] = 2'B01
SP
DELAY BOUND
BE
Option 3 Bit [7:6] = 2'B10
SP
WFQ
Option 4 Bit [7:6] = 2'B11
WFQ
Credit for WFQ - Bit [5:0]
W7
11.9.18.2
•
Data Sheet
W6
W5
W4
W3
W2
W1
W0
QOSC44 - CREDIT_C1_G2
CPU Address:h55B
Bits [7]:
•
Flow control allow during WFQ scheme. (Default 1'b1)
• 0 = Not support QoS when the Source port Flow control status is on.
• 1= Always support QoS)
Bits [6]:
•
Flow control BE Queue only. (Default 1'b1)
• 0= DO NOT send any frames if the XOFF is on.
• 1= the P7-P2 frames can be sent even the XOFF is ON
Bits [5:0]
Fc_allow
•
W1 - Credit register. (Default 4'h04)
Fc_be_only
Lost_ok
Egress- for dest fc_status
Ingressfor src fc
status
0
0
0
Go to BE Queue if (Src FC or Des FC on) otherwise Normal
0
0
1
Go to BE Queue if (Dest FC on) otherwise Normal
1
0
0
(WFQ only) Go to BE Queue if (Src FC on) otherwise BAD
1
0
1
(WFQ only)
Always Normal
X
1
0
Go to BE Queue if (Src FC on)
X
1
1
Always Normal
100
Zarlink Semiconductor Inc.
MVTX2804
11.9.18.3
•
Bits [5:0]:
•
W2 - Credit register. (Default 4'h04)
Bits [7:6]:
•
Reserved
Bits [5:0]:
•
W3 - Credit register. (Default 4'h04)
Bits [7:6]:
•
Reserved
Bits [5:0]:
•
W4 - Credit register. (Default 4'h04)
Bits [7:6]:
•
Reserved
Bits [5:0]:
•
W5 - Credit register. (Default 5'h8)
Bits [7:6]:
•
Reserved
QOSC49- CREDIT_C6_G2
CPU Address:h560
Bits [5:0]:
•
W6 - Credit register. (Default 5'h8)
Bits [7:6]:
•
Reserved
11.9.18.8
•
QOSC48 - CREDIT_C5_G2
CPU Address:h55F
11.9.18.7
•
QOSC47 - CREDIT_C4_G2
CPU Address:h55E
11.9.18.6
•
QOSC46 - CREDIT_C3_G2
CPU Address:h55D
11.9.18.5
•
QOSC45 - CREDIT_C2_G2
CPU Address:h55C
11.9.18.4
•
Data Sheet
QOSC4A- CREDIT_C7_G2
CPU Address:h561
Bits [5:0]:
•
W7 - Credit register. (Default 5'h10)
Bits [7:6]:
•
Reserved
QOSC43 through QOSC4Arepresents the set of WFQ parameters (see section 7.5) for Gigabit port 2. The
granularity of the numbers is 1, and their sum must be 64. QOSC43 corresponds to W0, and QOSC4A
corresponds to W7.
101
Zarlink Semiconductor Inc.
MVTX2804
11.9.19
•
Classes WFQ Credit Port G3
Access by CPU only
11.9.19.1
•
QOSC4B - CREDIT_C0_G3
CPU Address:h562
Bits [5:0]:
•
W0 - Credit register for WFQ. (Default 6'h04)
Bits [7:6]:
•
•
Priority type. Define one of the four QoS mode of operation for port 3 (Default 2'00)
See table below:
Queue
P7
P6
P5
P4
P3
P2
P1
Option 1 Bit [7:6] = 2'B00
DELAY BOUND
BE
Option 2 Bit [7:6] = 2'B01
SP
DELAY BOUND
BE
Option 3 Bit [7:6] = 2'B10
SP
WFQ
Option 4 Bit [7:6] = 2'B11
WFQ
Credit for WFQ - Bit [5:0]
W7
11.9.19.2
•
Data Sheet
W6
W5
W4
W3
W2
W1
P0
W0
QOSC4 - CREDIT_C1_G3
CPU Address:h563
Bits [7]:
•
Flow control allow during WFQ scheme. (Default 1'b1)
• 0 = Not support QoS when the Source port Flow control status is on.
• 1= Always support QoS)
Bits [6]:
•
Flow control BE Queue only. (Default 1'b1)
• 0= DO NOT send any frames if the XOFF is on.
• 1= the P7-P2 frames can be sent even the XOFF is ON
Bits [5:0]
•
Fc_allow
W1 - Credit register. (Default 4’h04)
Fc_be_only
Lost_ok
Egress- for dest fc_status
Ingressfor src fc
status
0
0
0
Go to BE Queue if (Src FC or Des FC on) otherwise Normal
0
0
1
Go to BE Queue if (Dest FC on) otherwise Normal
1
0
0
(WFQ only) Go to BE Queue if (Src FC on) otherwise BAD
1
0
1
(WFQ only)
Always Normal
X
1
0
Go to BE Queue if (Src FC on)
X
1
1
Always Normal
102
Zarlink Semiconductor Inc.
MVTX2804
11.9.19.3
•
Bits [5:0]:
•
W2 - Credit register. (Default 4'h04)
Bits [7:6]:
•
Reserved
Bits [5:0]:
•
W3 - Credit register. (Default 4'h04)
Bits [7:6]:
•
Reserved
Bits [5:0]:
•
W4 - Credit register. (Default 4'h04)
Bits [7:6]:
•
Reserved
Bits [5:0]:
•
W5 - Credit register. (Default 5'h8)
Bits [7:6]:
•
Reserved
QOSC51- CREDIT_C6_G3
CPU Address:h568
Bits [5:0]:
•
W6 - Credit register. (Default 5'h8)
Bits [7:6]:
•
Reserved
11.9.19.8
•
QOSC50 - CREDIT_C5_G3
CPU Address:h567
11.9.19.7
•
QOSC4F - CREDIT_C4_G3
CPU Address:h566
11.9.19.6
•
QOSC4E - CREDIT_C3_G3
CPU Address:h565
11.9.19.5
•
QOSC4D - CREDIT_C2_G3
CPU Address:h564
11.9.19.4
•
Data Sheet
QOSC52- CREDIT_C7_G3
CPU Address:h569
Bits [5:0]:
•
W7 - Credit register. (Default 5'h10)
Bits [7:6]:
•
Reserved
QOSC4B through QOSC52 represents the set of WFQ parameters (see section 7.5) for Gigabit port 3. The
granularity of the numbers is 1, and their sum must be 64. QOSC4B corresponds to W0, and QOSC52
corresponds to W7.
103
Zarlink Semiconductor Inc.
MVTX2804
11.9.20
•
Classes WFQ Credit Port G4
Access by CPU only
11.9.20.1
•
QOSC53 - CREDIT_C0_G4
CPU Address:h56A
Bits [5:0]:
W0 - Credit register for WFQ. (Default 6'h04)
Bits [7:6]:
Priority type. Define one of the four QoS mode of operation for port 4 (Default 2'00)
See table below:
Queue
P7
P6
P5
P4
P3
P2
P1
Option 1 Bit [7:6] = 2'B00
DELAY BOUND
BE
Option 2 Bit [7:6] = 2'B01
SP
DELAY BOUND
BE
Option 3 Bit [7:6] = 2'B10
SP
WFQ
Option 4 Bit [7:6] = 2'B11
WFQ
Credit for WFQ - Bit [5:0]
W7
11.9.20.2
•
Data Sheet
W6
W5
W4
W3
W2
W1
P0
W0
QOSC54 - CREDIT_C1_G4
CPU Address:h56B
Bits [7]:
•
Flow control allow during WFQ scheme. (Default 1'b1)
• 0 = Not support QoS when the Source port Flow control status is on.
• 1= Always support QoS)
Bits [6]:
•
Flow control BE Queue only. (Default 1'b1)
• 0= DO NOT send any frames if the XOFF is on.
• 1= the P7-P2 frames can be sent even the XOFF is ON
Bits [5:0]
Fc_allow
•
W1 -Credit register. (Default 4'h04)
Fc_be_only
Egress- for dest fc_status
Lost_ok
Ingress- for src fc
status
0
0
0
Go to BE Queue if (Src FC or Des FC on) otherwise Normal
0
0
1
Go to BE Queue if (Dest FC on) otherwise Normal
1
0
0
(WFQ only) Go to BE Queue if (Src FC on) otherwise BAD
1
0
1
(WFQ only)
Always Normal
X
1
0
Go to BE Queue if (Src FC on)
X
1
1
Always Normal
104
Zarlink Semiconductor Inc.
MVTX2804
11.9.20.3
•
Bits [5:0]:
•
W2 - Credit register. (Default 4'h04)
Bits [7:6]:
•
Reserved
Bits [5:0]:
•
W3 - Credit register. (Default 4'h04)
Bits [7:6]:
•
Reserved
Bits [5:0]:
•
W4 - Credit register. (Default 4'h04)
Bits [7:6]:
•
Reserved
Bits [5:0]:
•
W5 - Credit register. (Default 5'h8)
Bits [7:6]:
•
Reserved
QOSC59- CREDIT_C6_G4
CPU Address:h570
Bits [5:0]:
•
W6 - Credit register. (Default 5'h8)
Bits [7:6]:
•
Reserved
11.9.20.8
•
QOSC58 - CREDIT_C5_G4
CPU Address:h56F
11.9.20.7
•
QOSC57 - CREDIT_C4_G4
CPU Address:h56E
11.9.20.6
•
QOSC56 - CREDIT_C3_G4
CPU Address:h56D
11.9.20.5
•
QOSC55 - CREDIT_C2_G4
CPU Address:h56C
11.9.20.4
•
Data Sheet
QOSC5A- CREDIT_C7_G4
CPU Address:h571
Bits [5:0]:
•
W7 - Credit register. (Default 5'h10)
Bits [7:6]:
•
Reserved
QOSC53 through QOSC5A represents the set of WFQ parameters (see section 7.5) for Gigabit port 4. The
granularity of the numbers is 1, and their sum must be 64. QOSC53 corresponds to W0, and QOSC5A
corresponds to W7.
105
Zarlink Semiconductor Inc.
MVTX2804
11.9.20.9
•
Classes WFQ Credit Port G5
Access by CPU only
11.9.20.10
•
QOSC5B - CREDIT_C0_G5
CPU Address:h572
Bits [5:0]:
•
W0 - Credit register for WFQ. (Default 6'h04)
Bits [7:6]:
•
Priority type. Define one of the four QoS mode of operation for port 5 (Default
2'00)
See table below:
•
Queue
P7
P6
P5
P4
P3
P2
P1
Option 1 Bit [7:6] = 2'B00
DELAY BOUND
BE
Option 2 Bit [7:6] = 2'B01
SP
DELAY BOUND
BE
Option 3 Bit [7:6] = 2'B10
SP
WFQ
Option 4 Bit [7:6] = 2'B11
WFQ
Credit for WFQ - Bit [5:0]
W7
11.9.20.11
•
Data Sheet
W6
W5
W4
W3
W2
W1
P0
W0
QOSC5C - CREDIT_C1_G5
CPU Address:h573
Bits [7]:
•
Flow control allow during WFQ scheme. (Default 1'b1)
• 0 = Not support QoS when the Source port Flow control status is on.
• 1= Always support QoS)
Bits [6]:
•
Flow control BE Queue only. (Default 1'b1)
• 0= DO NOT send any frames if the XOFF is on.
• 1= the P7-P2 frames can be sent even the XOFF is ON
Bits [5:0]
Fc_allow
•
W1 - Credit register. (Default 4'h04)
Fc_be_only
Egress- for dest fc_status
Lost_ok
Ingress- for src fc
status
0
0
0
Go to BE Queue if (Src FC or Des FC on) otherwise Normal
0
0
1
Go to BE Queue if (Dest FC on) otherwise Normal
1
0
0
(WFQ only) Go to BE Queue if (Src FC on) otherwise BAD
1
0
1
(WFQ only)
Always Normal
X
1
0
Go to BE Queue if (Src FC on)
X
1
1
Always Normal
106
Zarlink Semiconductor Inc.
MVTX2804
11.9.20.12
•
Bits [5:0]:
•
W2 - Credit register. (Default 4'h04)
Bits [7:6]:
•
Reserved
Bits [5:0]:
•
W3 - Credit register. (Default 4'h04)
Bits [7:6]:
•
Reserved
Bits [5:0]:
•
W4 - Credit register. (Default 4'h04)
Bits [7:6]:
•
Reserved
Bits [5:0]:
•
W5 - Credit register. (Default 5'h8)
Bits [7:6]:
•
Reserved
QOSC61- CREDIT_C6_G5
CPU Address:h578
Bits [5:0]:
•
W6 - Credit register. (Default 5'h8)
Bits [7:6]:
•
Reserved
11.9.20.17
•
QOSC60 - CREDIT_C5_G5
CPU Address:h577
11.9.20.16
•
QOSC5F - CREDIT_C4_G5
CPU Address:h576
11.9.20.15
•
QOSC5E - CREDIT_C3_G5
CPU Address:h575
11.9.20.14
•
QOSC5D - CREDIT_C2_G5
CPU Address:h574
11.9.20.13
•
Data Sheet
QOSC62- CREDIT_C7_G5
CPU Address:h579
Bits [5:0]:
•
W7 - Credit register. (Default 5'h10)
Bits [7:6]:
•
Reserved
QOSC5B through QOSC62 represents the set of WFQ parameters (see section 7.5) for Gigabit port 5. The
granularity of the numbers is 1, and their sum must be 64. QOSC5B corresponds to W0, and QOSC62
corresponds to W7.
107
Zarlink Semiconductor Inc.
MVTX2804
11.9.21
•
Classes WFQ Credit Port G6
Access by CPU only
11.9.21.1
•
QOSC63 - CREDIT_C0_G6
CPU Address:h57A
Bits [5:0]:
•
W0 - Credit register for WFQ. (Default 6'h04)
Bits [7:6]:
•
•
Priority type. Define one of the four QoS mode of operation for port 6 (Default 2'00)
See table below:
Queue
P7
P6
P5
P4
P3
P2
P1
Option 1 Bit [7:6] = 2'B00
DELAY BOUND
BE
Option 2 Bit [7:6] = 2'B01
SP
DELAY BOUND
BE
Option 3 Bit [7:6] = 2'B10
SP
WFQ
Option 4 Bit [7:6] = 2'B11
WFQ
Credit for WFQ - Bit [5:0]
W7
11.9.21.2
•
Data Sheet
W6
W5
W4
W3
W2
W1
P0
W0
QOSC64 - CREDIT_C1_G6
CPU Address:h57B
Bits [7]:
•
Flow control allow during WFQ scheme. (Default 1'b1)
• 0 = Not support QoS when the Source port Flow control status is on.
• 1= Always support QoS)
Bits [6]:
•
Flow control BE Queue only. (Default 1'b1)
• 0= DO NOT send any frames if the XOFF is on.
• 1= the P7-P2 frames can be sent even the XOFF is ON
Bits [5:0]
Fc_allow
•
W1 - Credit register. (Default 4'h04)
Fc_be_only
Lost_ok
Egress- for dest fc_status
Ingressfor src fc
status
0
0
0
Go to BE Queue if (Src FC or Des FC on) otherwise Normal
0
0
1
Go to BE Queue if (Dest FC on) otherwise Normal
1
0
0
(WFQ only) Go to BE Queue if (Src FC on) otherwise BAD
1
0
1
(WFQ only)
Always Normal
X
1
0
Go to BE Queue if (Src FC on)
X
1
1
Always Normal
108
Zarlink Semiconductor Inc.
MVTX2804
11.9.21.3
•
Bits [5:0]:
•
W2 - Credit register. (Default 4'h04)
Bits [7:6]:
•
Reserved
Bits [5:0]:
•
W3 - Credit register. (Default 4'h04)
Bits [7:6]:
•
Reserved
Bits [5:0]:
•
W4 - Credit register. (Default 4'h04)
Bits [7:6]:
•
Reserved
Bits [5:0]:
•
W5 - Credit register. (Default 5'h8)
Bits [7:6]:
•
Reserved
QOSC69- CREDIT_C6_G6
CPU Address:h580
Bits [5:0]:
•
W6 - Credit register. (Default 5'h8)
Bits [7:6]:
•
Reserved
11.9.21.8
•
QOSC68 - CREDIT_C5_G6
CPU Address:h57F
11.9.21.7
•
QOSC67 - CREDIT_C4_G6
CPU Address:h57E
11.9.21.6
•
QOSC66 - CREDIT_C3_G6
CPU Address:h57D
11.9.21.5
•
QOSC65 - CREDIT_C2_G6
CPU Address:h57C
11.9.21.4
•
Data Sheet
QOSC6A- CREDIT_C7_G6
CPU Address:h581
Bits [5:0]:
•
W7 - Credit register. (Default 5'h10)
Bits [7:6]:
•
Reserved
QOSC63 through QOSC6A represents the set of WFQ parameters (see section 7.5) for Gigabit port 6. The
granularity of the numbers is 1, and their sum must be 64. QOSC63 corresponds to W0, and QOSC6A
corresponds to W7.
109
Zarlink Semiconductor Inc.
MVTX2804
11.9.22
•
Data Sheet
Classes WFQ Credit Port G7
Access by CPU only
11.9.22.1
•
QOSC6B - CREDIT_C0_G7
CPU Address:h582
Bits [5:0]:
•
W0 - Credit register for WFQ. (Default 6'h04)
Bits [7:6]:
•
Priority type. Define one of the four QoS mode of operation for port 7 (Default
2'00)
See table below:
•
Queue
11.9.22.2
•
P7
P6
P5
P4
P3
P2
P1
Option 1 Bit [7:6] = 2'B00
DELAY BOUND
BE
Option 2 Bit [7:6] = 2'B01
SP
DELAY BOUND
BE
Option 3 Bit [7:6] = 2'B10
SP
WFQ
Option 4 Bit [7:6] = 2'B11
WFQ
Credit for WFQ - Bit [5:0]
W7
W6
W5
W4
W3
W2
W1
P0
W0
QOSC6C - CREDIT_C1_G7
CPU Address:h583
Bits [7]:
•
Flow control allow during WFQ scheme. (Default 1'b1)
• 0 = Not support QoS when the Source port Flow control status is on.
• 1= Always support QoS)
Bits [6]:
•
Flow control BE Queue only. (Default 1'b1)
• 0= DO NOT send any frames if the XOFF is on.
• 1= the P7-P2 frames can be sent even the XOFF is ON
Bits [5:0]
Fc_allow
•
W1 - Credit register. (Default 4'h04)
Fc_be_only
Lost_ok
Egress- for dest fc_status
Ingress- for src fc
status
0
0
0
Go to BE Queue if (Src FC or Des FC on) otherwise Normal
0
0
1
Go to BE Queue if (Dest FC on) otherwise Normal
1
0
0
(WFQ only) Go to BE Queue if (Src FC on) otherwise BAD
1
0
1
(WFQ only)
Always Normal
X
1
0
Go to BE Queue if (Src FC on)
X
1
1
Always Normal
110
Zarlink Semiconductor Inc.
MVTX2804
11.9.22.3
•
Bits [5:0]:
•
W2 - Credit register. (Default 4'h04)
Bits [7:6]:
•
Reserved
Bits [5:0]:
•
W3 - Credit register. (Default 4'h04)
Bits [7:6]:
•
Reserved
Bits [5:0]:
•
W4 - Credit register. (Default 4'h04)
Bits [7:6]:
•
Reserved
Bits [5:0]:
•
W5 - Credit register. (Default 5'h8)
Bits [7:6]:
•
Reserved
QOSC71- CREDIT_C6_G7
CPU Address:h588
Bits [5:0]:
•
W6 - Credit register. (Default 5'h8)
Bits [7:6]:
•
Reserved
11.9.22.8
•
QOSC70 - CREDIT_C5_G7
CPU Address:h587
11.9.22.7
•
QOSC6F - CREDIT_C4_G7
CPU Address:h586
11.9.22.6
•
QOSC6E - CREDIT_C3_G7
CPU Address:h585
11.9.22.5
•
QOSC6D - CREDIT_C2_G7
CPU Address:h584
11.9.22.4
•
Data Sheet
QOSC72- CREDIT_C7_G7
CPU Address:h589
Bits [5:0]:
•
W7 - Credit register. (Default 5'h10)
Bits [7:6]:
•
Reserved
QOSC6B through QOSC72 represents the set of WFQ parameters (see section 7.5) for Gigabit port 7. The
granularity of the numbers is 1, and their sum must be 64. QOSC6B corresponds to W0, and QOSC72
corresponds to W7.
111
Zarlink Semiconductor Inc.
MVTX2804
11.9.23
•
QOSC73 - TOKEN_RATE_G0
CPU Address:h58A
Bits [7:0]:
11.9.23.2
•
Class 6 Shaper Control Port G0
Accessed by CPU only
11.9.23.1
•
Data Sheet
•
Bytes allow to transmit every frame time (0.512usec) when regulated by
Shaper logic. (Default: 8'h08)
QOSC74 - TOKEN_LIMIT_G0
CPU Address:h58B
Bits [7:0]:
•
Bytes allow to continue transmit out when regulated by Shaper logic. (16byte/unit)
(Default: 8'hC0)
QOSC73 and QOSC74 correspond to parameters from section 7.6 on the shaper for EF traffic. QOSC73 is an
integer less than 64 (average rate), with granularity 1. QOSC74 is the programmed maximum value of the
counter (maximum burst size). This value is expressed in multiples of 16. QOSC73 and QOSC74 apply to
Gigabit port 0. Register QOSC39-CREDIT_C6_G0 programs the peak rate. See QoS application note for more
information.
11.9.23.3
•
Accessed by CPU only
11.9.23.4
•
QOSC75 - TOKEN_RATE_G1
CPU Address:h58C
Bits [7:0]:
11.9.23.5
•
Class 6 Shaper Control Port G1
•
Bytes allow to transmit every frame time (0.512usec) when regulated by Shaper logic.
(Default: 8'h08)
QOSC76 - TOKEN_LIMIT_G1
CPU Address:h58D
Bits [7:0]:
•
Bytes allow to continue transmit out when regulated by Shaper logic. (16byte/unit)
(Default: 8'hC0)
QOSC75 and QOSC76 correspond to parameters from section 7.6 on the shaper for EF traffic. QOSC75 is an
integer less than 64 (average rate), with granularity 1. QOSC76 is the programmed maximum value of the
counter (maximum burst size). This value is expressed in multiples of 16. QOSC75 and QOSC76 apply to
Gigabit port 0. Register QOSC41-CREDIT_C6_G1 programs the peak rate. See QoS application note for more
information.
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Zarlink Semiconductor Inc.
MVTX2804
11.9.24
•
Class 6 Shaper Control Port G2
Accessed by CPU only
11.9.24.1
•
QOSC77 - TOKEN_RATE_G2
CPU Address:h58E
Bits [7:0]:
11.9.24.2
•
Data Sheet
•
Bytes allow to transmit every frame time (0.512usec) when regulated by Shaper logic.
(Default: 8'h08)
QOSC78 - TOKEN_LIMIT_G2
CPU Address:h58F
Bits [7:0]:
•
Bytes allow to continue transmit out when regulated by Shaper logic. (16byte/unit)
(Default: 8'hC0)
QOSC77 and QOSC78 correspond to parameters from section 7.6 on the shaper for EF traffic. QOSC77 is an
integer less than 64 (average rate), with granularity 1. QOSC78 is the programmed maximum value of the
counter (maximum burst size). This value is expressed in multiples of 16. QOSC77 and QOSC78 apply to
Gigabit port 2. QOSC49-CREDIT_C6_G2 programs the peak rate. See QoS application note for more
information.
11.9.25
•
Accessed by CPU only
11.9.25.1
•
QOSC79 - TOKEN_RATE_G3
CPU Address:h590
Bits [7:0]:
11.9.25.2
•
Class 6 Shaper Control Port G3
•
Bytes allow to transmit every frame time (0.512usec) when regulated by Shaper logic.
(Default: 8'h08)
QOSC7A - TOKEN_LIMIT_G3
CPU Address:h591
Bits [7:0]:
•
Bytes allow to continue transmit out when regulated by Shaper logic. (16byte/unit)
(Default: 8'hC0)
QOSC79 and QOSC7A correspond to parameters from section 7.6 on the shaper for EF traffic. QOSC79 is an
integer less than 64 (average rate), with granularity 1. QOSC7A is the programmed maximum value of the
counter (maximum burst size). This value is expressed in multiples of 16. QOSC79 and QOSC7A apply to
Gigabit port 3. QOSC51-CREDIT_C6_G3 programs the peak rate. See QoS application note for more
information.
113
Zarlink Semiconductor Inc.
MVTX2804
11.9.26
•
QOSC7B - TOKEN_RATE_G4
CPU Address:h592
Bits [7:0]:
11.9.26.2
•
Class 6 Shaper Control Port G4
Accessed by CPU only
11.9.26.1
•
Data Sheet
•
Bytes allow to transmit every frame time (0.512usec) when regulated by Shaper logic.
(Default: 8'h08)
QOSC7C - TOKEN_LIMIT_G4
CPU Address:h593
Bits [7:0]:
•
Bytes allow to continue transmit out when regulated by Shaper logic. (16byte/unit)
(Default: 8'hC0)
QOSC7B and QOSC7C correspond to parameters from section 7.6 on the shaper for EF traffic. QOSC7B is an
integer less than 64, with granularity 1 (average rate). QOSC7C is the programmed maximum value of the
counter (maximum burst size). This value is expressed in multiples of 16. QOSC7B and QOSC7C apply to
Gigabit port 4. QOSC59-CREDIT_C6_G4 programs the peak rate. See QoS application note for more
information.
11.9.27
•
Accessed by CPU only
11.9.27.1
•
QOSC7D - TOKEN_RATE_G5
CPU Address:h594
Bits [7:0]:
11.9.27.2
•
Class 6 Shaper Control Port G5
•
Bytes allow to transmit every frame time (0.512usec) when regulated by Shaper logic.
(Default: 8'h08)
QOSC7E - TOKEN_LIMIT_G5
CPU Address:h595
Bits [7:0]:
•
Bytes allow to continue transmit out when regulated by Shaper logic. (16byte/unit)
(Default: 8'hC0)
QOSC7D and QOSC7E correspond to parameters from section 7.6 on the shaper for EF traffic. QOSC7D is an
integer less than 64 (average rate), with granularity 1. QOSC7E is the programmed maximum value of the
counter C1 (maximum burst size). This value is expressed in multiples of 16. QOSC7D and QOSC7E apply to
Gigabit port 5. QOSC60-CREDIT_C6_G5 programs the peak rate. See QoS application note for more
information.
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Zarlink Semiconductor Inc.
MVTX2804
11.9.28
Class 6 Shaper Control Port G6
11.9.28.1
Accessed by CPU only
11.9.28.2
QOSC7F - TOKEN_RATE_G6
•
CPU Address:h596
Bits [7:0]:
11.9.28.3
•
Data Sheet
•
Bytes allow to transmit every frame time (0.512usec) when regulated by Shaper logic.
(Default: 8'h08)
QOSC80 - TOKEN_LIMIT_G6
CPU Address:h597
Bits [7:0]:
•
Bytes allow to continue transmit out when regulated by Shaper logic. (16byte/unit)
(Default: 8'hC0)
QOSC7F and QOSC80 correspond to parameters from section 7.6 on the shaper for EF traffic. QOSC7F is an
integer less than 64 (average rate), with granularity 1. QOSC80 is the programmed maximum value of the
counter C1 (maximum burst size). This value is expressed in multiples of 16. QOSC7F and QOSC80 apply to
Gigabit port 6. QOSC69-CREDIT_C6_G6 programs the peak rate. See QoS application note for more
information.
11.9.29
•
Accessed by CPU only
11.9.29.1
•
QOSC81 - TOKEN_RATE_G7
CPU Address:h598
Bits [7:0]:
11.9.29.2
•
Class 6 Shaper Control Port G7
•
Bytes allow to transmit every frame time (0.512usec) when regulated by Shaper logic.
(Default: 8'h08)
QOSC82 - TOKEN_LIMIT_G7
CPU Address:h599
Bits [7:0]:
•
Bytes allow to continue transmit out when regulated by Shaper logic. (16byte/unit)
(Default: 8'hC0)
QOSC81 and QOSC82 correspond to parameters from section 7.6 on the shaper for EF traffic. QOSC81 is an
integer less than 64 (average rate), with granularity 1. QOSC82 is the programmed maximum value of the
counter C1 (maximum burst size). This value is expressed in multiples of 16. QOSC81 and QOSC82 apply to
Gigabit port 7. QOSC6F-CREDIT_C6_G7 programs the peak rate. See QoS application note for more
information.
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Zarlink Semiconductor Inc.
MVTX2804
11.9.30
•
•
RDRC0 - WRED Rate Control 0
I2C Address:h085, CPU Address:h59A
Accessed by CPU, Serial Interface and I2C (R/W)
7
4 3
X Rate
Y Rate
•
Corresponds to the percentage X% in Chapter 7. Used for random early drop.
Granularity 6.25%. (Default: 4'h8)
Bits[3:0]:
•
Corresponds to the percentage Y% in Chapter 7. Used for random early drop.
Granularity 6.25%.(Default: 4'hE)
RDRC1 - WRED Rate Control 1
I2C Address:h086, CPU Address:h59B
Accessed by CPU, Serial Interface and I2C (R/W)
7
4 3
Z Rate
0
B Rate
Bits [7:4]:
•
Corresponds to the percentage Z% in Chapter 7. Used for random early drop.
Granularity 6.25%.%. (Default: 4'h6)
Bits[3:0]:
•
Corresponds to the best effort frame drop percentage B%, when shared pool is all in use and
destination port best effort queue reaches UCC. Used for random early drop.
Granularity 6.25%.%. (Default: 4'h8)
11.10
Group 6 Address
11.10.1
MISC Group
11.10.1.1
•
•
0
Bits [7:4]:
11.9.31
•
•
Data Sheet
MII_OP0 - MII REGISTER OPTION 0
I2C Address:h0B1, CPU Address:h600
Accessed by CPU, serial interface and I 2C (R/W)
7
Hfc
Bit [7]:
6
5
1prst
4
NP
0
Vendor Spc. Reg Addr
• Half duplex flow control (Do not use half duplex mode)
0 = Half duplex flow control always enable
1 = Half duplex flow control by negotiation
Bit[6]:
•
Link partner reset auto-negotiate disable
Bit [5]
• Next page enable
1: enable
0: disable
Bit[4:0]:
•
Vendor specified link status register address (null value means don't use it) (Default 00)
116
Zarlink Semiconductor Inc.
MVTX2804
11.10.1.2
•
•
MII_OP1 - MII REGISTER OPTION 1
I2C Address:0B2, CPU Address:h601
Accessed by CPU, serial interface and I 2C (R/W)
7
4
3
Speed bit location
0
Duplex bit location
Bits[3:0]:
•
Duplex bit location in vendor specified register
Bits [7:4]:
•
Speed bit location in vendor specified register (Default 00)
11.10.1.3
•
•
Data Sheet
FEN - FEATURE REGISTER
I2C Address:h0B3, CPU Address:h602
Accessed by CPU, serial interface and I 2C (R/W)
7
6
DML
Bits [0]:
•
MII
5
4
3
Rp
IP Mul
V-Sp
2
DS
1
0
SC
Statistic Counter Enable (Default 0)
• 0 - Disable
• 1 - Enable
•
When statistic counter is enable, an interrupt control frame is generated to the CPU, every
time a counter wraps around. This feature requires an external CPU.
Bits[1]:
•
Reserved
Bit [2]:
•
Support DS EF Code. (Default 0)
• 0 - Disable
• 1 - Enable (all ports)
Bit [3]:
•
When 101110 is detected in DS field (TOS[7:2]), the frame priority is set for 110 and drop is set
for 0.
•
Enable VLAN spanning tree support (Default 0)
• 0 - Disable
• 1 - Enable
Bit [4]:
•
When VLAN spanning tree is enable the register ECR1Pn are not used to program the port
spanning tree status. The port spanning tree status is programmed in the VLAN status field.
•
Disable IP Multicast Support (Default 1)
• 0 - Enable IP Multicast Support
• 1 - Disable IP Multicast Support
Bit [5]:
•
When enable, IGMP packets are identified by search engine and are passed to the CPU for
processing. IP multicast packets are forwarded to the IP multicast group members according
to the VLAN port mapping table.
•
Enable report of new MAC and VLAN (Default 0)
• 0 - Disable report to CPU
• 1 - Enable report to CPU
Bit [6]:
•
When disable: new VLAN port association report, new MAC address report and aging report
are disable for all ports. When enable, register SE_OPEMODE is used to enable/disable
selectively each function.
•
•
0: Enable MII Management State Machine (Default 0)
1: Disable MII Management State Machine
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Bit [7]:
11.10.1.4
•
•
Data Sheet
0: Enable using MCT Link List structure
1: Disable using MCT Link List structure
MIIC0 - MII COMMAND REGISTER 0
• CPU Address:h603
• Accessed by CPU and serial interface only (R/W)
• Bit [7:0] MII Data [7:0]
Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY, and no VALID; then
program MII command.
11.10.1.5
MIIC1 - MII COMMAND REGISTER 1
• CPU Address:h604
• Accessed by CPU and serial interface only (R/W)
• Bit [7:0] MII Data [15:8]
Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then
program MII command.
11.10.1.6
•
•
MIIC2 - MII COMMAND REGISTER 2
CPU Address:h605
Accessed by CPU and serial interface only (R/W)
7
6
5
MII OP
4
0
Register address
Bits [4:0]:
REG_AD - Register PHY Address
Bit [6:5]
OP - Operation code “10” for read command and “01” for write command
Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then
program MII command.
11.10.1.7
•
•
MIIC3 - MII COMMAND REGISTER 3
CPU Address:h606
Accessed by CPU and serial interface only (R/W)
7
6
Rdy
Valid
5
4
0
PHY address
Bits [4:0]:
PHY_AD - 5 Bit PHY Address
Bit [6]
VALID - Data Valid from PHY (Read Only)
Bit [7]
RDY - Data is returned from PHY (Ready Only)
Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then
program MII command.
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MVTX2804
11.10.1.8
•
•
•
MIID0 - MII DATA REGISTER 0
CPU Address:h607
Accessed by CPU and serial interface only (RO)
Bit [7:0] MII Data [7:0]
11.10.1.9
•
•
•
MIID1 - MII DATA REGISTER 0
CPU Address:h608
Accessed by CPU and serial interface only (RO)
Bit [7:0] MII Data [15:8]
11.10.1.10
•
•
Data Sheet
LED MODE - LED CONTROL
I2C Address:h0B4; CPU Address:h609
Accessed by CPU, serial interface and I 2C (R/W)
7
6
5
lpbk
Bit[1:0]
4
Out
Pattern
3
2
Clock rate
• Sample hold time(Default 2'b00)
2'b00- 8 msec
2'b01- 16 msec
2'b10- 32 msec
2'b11- 64 msec
Bit[3:2]
• LED clock speed (serial mode) (Default 2'b10)
2'b00- sclk/1282'b01- sclk/256
2'b10- sclk/10242'b11- sclk/2048
• LED clock speed (parallel mode) (Default 2'b10)
2'b00- sclk/10242'b01- sclk/4096
2'b10- sclk/20482'b11- sclk/8192
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1
0
Hold Time
MVTX2804
Bit[5:4]
LED indicator out pattern (Default 2'b11)
2'b00- Normal output, LED signals go straight out, no logical combination
2'b01- 4 bi-color LED mode
2'b10- 3 bi-color LED mode
2'b11- programmable mode
1. Normal mode:
LED_BYTEOUT_[7]:Collision (COL)
LED_BYTEOUT_[6]:Full duplex (FDX)
LED_BYTEOUT_[5]:Speed[1] (SP1)
LED_BYTEOUT_[4]:Speed[0] (SP0)
LED_BYTEOUT_[3]:Link (LNK)
LED_BYTEOUT_[2]:Rx (RXD)
LED_BYTEOUT_[1]:Tx (TXD)
LED_BYTEOUT_[0]:Flow Control (FC)
2. 4 bi-color LED mode
LED_BYTEOUT_[7]:COL
LED_BYTEOUT_[6]:1000FDX
LED_BYTEOUT_[5]:1000HDX
LED_BYTEOUT_[4]:100FDX
LED_BYTEOUT_[3]:100HDX
LED_BYTEOUT_[2]:10FDX
LED_BYTEOUT_[1]:10HDX
LED_BYTEOUT_[0]:ACT
Note: All output qualified by Link signal
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Data Sheet
MVTX2804
Data Sheet
3. 3 bi-color LED mode:
LED_BYTEOUT_[7]:COL
LED_BYTEOUT_[6]:LNK
LED_BYTEOUT_[5]:FC
LED_BYTEOUT_[4]:SPD1000
LED_BYTEOUT_[3]:SPD100
LED_BYTEOUT_[2]:FDX
LED_BYTEOUT_[1]:HDX
LED_BYTEOUT_[0]:ACT
Note: All output qualified by Link signal
4. Programmable mode:
LED_BYTEOUT_[7]:Link
LED_BYTEOUT_[6:0]:Defined by the LEDSIG6 ~ LEDSIG0
programmable registers.
Note: All output qualified by Link signal
Bit[6]:
•
Reserved. Must be '0'
Bit[7]:
•
Enable internal loop back. When this bit is set to '1' all ports work in internal loop back mode.
For normal operation must be '0'.
11.10.2
•
•
I2C Address h0C5, CPU Address:h60B
Accessed by CPU, serial interface and I 2C (R/W)
Bit[7:0]:
11.10.3
11.10.3.1
•
•
CHECKSUM - EEPROM Checksum
(Default 00)
LED User
LEDUSER0
I2C Address h0BB, CPU Address:h60C
Accessed by CPU, serial interface and I 2C (R/W)
7
0
LED USER0
Bit[7:0]:
(Default 00)
Content will send out by LED serial logic
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MVTX2804
11.10.3.2
•
•
Data Sheet
LEDUSER1
I2C Address h0BC, CPU Address:h60D
Accessed by CPU, serial interface and I 2C (R/W)
7
0
LED USER1
Bit[7:0]:
(Default 00)
Content will send out by LED serial logic
11.10.3.3
LEDUSER2/LEDSIG2
• I2C Address h0BD, CPU Address:h60E
• Accessed by CPU, serial interface and I 2C (R/W)
In serial mode:
7
0
LED USER2
Bit[7:0]:
(Default 00)
Content will be sent out by LED serial shift logic
In parallel mode: this register is used for programming the LED pin - led_byteout_[2]
7
COL
FDX
SP1
Bit [3:0]:
(Default 4'H0)
Signal polarity:
0: not invert polarity (high true)
1: invert polarity
Bit [7:4]
(Default 4'H8)
4
3
SP0
COL
0
FDX
SP1
SP0
Signal Select:
0: not select
1: select the corresponding bit
When bits get selected, the led_byteout_[2] = AND (all selected bits)
11.10.3.4
LEDUSER3/LEDSIG3
• I2C Address:h0BE, CPU Address:h60F
• Access by CPU, serial interface (R/W)
In serial mode:
0
7
LED USER3
Bit [7:0]:
(Default 8'H33)
Content will be sent out by LED serial shift logic.
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Data Sheet
In parallel mode: this register is used for programming the LED pin - led_byteout_[3]
0
7
COL
FDX
SP1
Bit [3:0]:
(Default 4'H3)
Signal polarity:
0: not invert polarity (high true)
1: invert polarity
Bit [7:4]
(Default 4'H3)
SP0
COL
FDX
SP1
SP0
Signal Select:
0: not select
1: select the corresponding bit
When bits get selected, the led_byteout_[3] = AND (all selected bits)
11.10.3.5
•
•
LEDUSER4/LEDSIG4
I2C Address:h0BF, CPU Address:h610
Access by CPU, serial interface (R/W)
0
7
LED USER4
Bit [7:0]
(Default 8'H32)
Content will be sent out by LED serial shift logic.
In parallel mode: this register is used for programming the LED pin - led_byteout_[4]
7
COL
SP1
3
SP0
COL
0
FDX
SP1
SP0
Bit [3:0]:
(Default 4'H2)
Signal polarity:
0: not invert polarity (high true)
1: invert polarity
Bit [7:4]
(Default 4'H3)
Signal Select:
0: not select
1: select the corresponding bit
When bits get selected, the led_byteout_[4] = AND (all selected bits)
11.10.3.6
•
•
FDX
4
LEDUSER5/LEDSIG5
I2C Address:h0C0, CPU Address:h611
Access by CPU, serial interface (R/W)
0
7
LED USER5
Bit [7:0]
(Default 8'H20)
Content will be sent out by LED serial shift logic.
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MVTX2804
Data Sheet
In parallel mode: this register is used for programming the LED pin - led_byteout_[5]
7
COL
FDX
SP1
Bit [3:0]
(Default 4'H0)
Signal polarity:
0: not invert polarity (high true)
1: invert polarity
Bit [7:4]
(Default 4'H2)
4
3
SP0
COL
0
FDX
SP1
SP0
Signal Select:
0: not select
1: select the corresponding bit
When bits get selected, the led_byteout_[5] = AND (all selected
bits)
11.10.3.7
•
•
LEDUSER6/LEDSIG6
I2C Address:h0C1, CPU Address:h612
Access by CPU, serial interface (R/W)
0
7
LED USER6
Bit [7:0]
(Default 8'H40)
Content will be sent out by LED serial shift logic.
In parallel mode: this register is used for programming the LED pin - led_byteout_[6]
7
COL
FDX
SP1
4
3
SP0
COL
0
FDX
SP1
SP0
Bit [3:0]
(Default 4'B0000)
Signal polarity:
0: not invert polarity (high true)
1: invert polarity
Bit [7:4]
(Default 4'b0100)
Signal Select:
0: not select
1: select the corresponding bit
When bits get selected, the led_byteout_[6] = AND (all selected bits), or the polarity of
led_byteout_[6] is controlled by LEDSIG1_0[3]
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MVTX2804
11.10.3.8
•
•
Data Sheet
LEDUSER7/LEDSIG1_0
I2C Address:h0C2, CPU Address:h613
Access by CPU, serial interface (R/W)
0
7
LED USER7
Bit [7:0]
(Default 8'H61)
Content will be sent out by LED serial shift logic.
In parallel mode: this register is used for programming the LED pin - led_byteout_[2]
7
GP
RX
TX
0
3
FC
P6
RX
TX
FC
Bit [7]
(Default 1'B0)
Global output polarity: this bit controls the output polarity of all led_byteout_ and led_port_sel pins.
0: no invert polarity - (led_byteout_[7:0] are high activated, led_port_sel[9:0] are low activated)
1: invert polarity - (led_byteout_[7:0] are low activated, led_port_sel[9:0] are high activated)
Bit [6:4]
(Default 3'B110)
Signal Select:
0: not select
1: select the corresponding bit
When bits get selected, the led_byteout_[6] = OR (all selected bits)
Bit[3]
(Default 1'B0)
Polarity control of led_byteout_[6]
0: not invert
1: invert
Bit [2:0]
(Default 3'b001)
Signal Select:
0: not select
1: select the corresponding bit
When bits get selected, the led_byteout_[0] = OR (all selected bits)
11.10.4
•
•
4
MIINP0 - MII Next Page Data Register 0
I2C Address:h0C3, CPU Address:h614
Access by CPU and serial interface only (R/W)
Bit [7:0]
11.10.5
MII next page Data [7:0]
MIINP1 - MII Next Page Data Register 1
• I2C Address:h0C4, CPU Address:h615
Access by CPU and serial interface only (R/W)
Bit [7:0]
MII next page Data [15:8]
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Zarlink Semiconductor Inc.
MVTX2804
11.11
Group F Address
11.11.1
11.11.1.1
•
•
CPU Access Group
GCR-GLOBAL CONTROL REGISTER
CPU Address: hF00
Accessed by CPU and serial interface. (R/W)
7
5
4
3
2
1
0
Init
Reset
Bist
SR
SC
Bit [0]:
Store configuration (Default = 0)
Write '1' followed by '0' to store configuration into external EEPROM
Bit[1]:
Store configuration and reset (Default = 0)
Write '1' to store configuration into external EEPROM and reset chip
Bit[2]:
Start BIST (Default = 0)
Write '1' followed by '0' to start the device's built-in self-test. The result is found in the DCR register.
Bit[3]:
Soft Reset (Default = 0)
Write '1' to reset the chip
Bit[4]:
Initialization Done (Default = 0)
This bit is meaningless when CPU is not installed. In managed mode, CPU write this bit with “1” to
indicate initialization is completed and ready to forward packets.
1 - initialization is done
0 - initialization is not completed.
Bit[7]
Interrupt Polarity (Default = 0)
1 - interrupt active high
0 - interrupt active low
11.11.1.2
•
•
Data Sheet
DCR-DEVICE STATUS AND SIGNATURE REGISTER
CPU Address: hF01
Accessed by CPU and serial interface. (RO)
6
7
Revision
5
4
Signature
3
RE
2
1
BinP
BR
Bit [0]:
1 - Busy writing configuration to I2C
0 - Not Busy writing configuration to I2C
Bit[1]:
1 - Busy reading configuration from I2C
0 - Not Busy reading configuration from I2C
Bit[2]:
1 - BIST in progress
0 - BIST not running
Bit[3]:
1 - RAM Error
0 - RAM OK
Bit[5:4]:
Device Signature
00 - 4 Ports Device, non-management mode
01 - 8 Ports Device, non-management mode
10 - 4 Ports Device, management mode possible (need to install CPU)
11 - 8 Ports Device, management mode possible (need to install CPU)
126
Zarlink Semiconductor Inc.
0
BW
MVTX2804
Bit [7:6]:
11.11.1.3
•
•
Revision
DCR01-GIGA PORT STATUS
CPU Address: hF02
Accessed by CPU and serial interface. (RO)
6
7
4 3
CIC
2
1
GIGA1
0
GIGA0
Bit [1:0]:
Giga port 0 strap option
- 00 - 100Mb MII mode
- 01 - 2G mode
- 10 - GMII
- 11 - PCS
Bit[3:2]
Giga port 1 strap option
- 00 - 100Mb MII mode
- 01 - Reserved
- 10 - GMII
- 11 - PCS
Bit [7]
Chip initialization completed.
Note: DCR01[7], DCR23[7], DCR45[7] and DCR67[7] have the same function.
11.11.1.4
•
•
Data Sheet
DCR23-GIGA PORT STATUS
CPU Address: hF03
Accessed by CPU and serial interface. (RO)
7
6
4
3
CIC
Bit [1:0]:
Giga port 2 strap option- 00 - 100Mb MII mode
- 00 - 100Mb MII mode
- 01 - Reserved
- 10 - GMII
- 11 - PCS
Bit[3:2]
Giga port 3 strap option
- 00 - 100Mb MII mode
- 01 - 2G mode
- 10 - GMII
- 11 - PCS
Bit [7]
Chip initialization completed
127
Zarlink Semiconductor Inc.
2
1
0
GIGA3
GIGA2
MVTX2804
11.11.1.5
•
•
DCR45-GIGA PORT STATUS
CPU Address: hF04
Accessed by CPU and serial interface. (RO)
6
7
4 3
CIC
2 1
GIGA5
Bit [1:0]:
Giga port 4 strap option
- 00 - 100Mb MII mode
- 01 - Reserved
- 10 - GMII
- 11 - PCS
Bit[3:2]
Giga port 5 strap option
- 00 - 100Mb MII mode
- 01 - 2G mode
- 10 - GMII
- 11 - PCS
Bit [7]
Chip initialization completed
11.11.1.6
•
•
Data Sheet
0
GIGA4
DCR67-GIGA PORT STATUS
CPU Address: hF05
Accessed by CPU and serial interface. (RO)
6
7
4 3
CIC
Bit [1:0]:
Giga port 6 strap option
- 00 - 100Mb MII mode
- 01 - 2G mode
- 10 - GMII
- 11 - PCS
Bit[3:2]
Giga port 7 strap option
- 00 - 100Mb MII mode
- 01 - Reserved
- 10 - GMII
- 11 - PCS
Bit [7]
Chip initialization completed
2
GIGA7
128
Zarlink Semiconductor Inc.
1
0
GIGA6
MVTX2804
11.11.1.7
•
•
DPST - DEVICE PORT STATUS REGISTER
CPU Address:hF06
Accessed by CPU and serial interface (R/W)
Bit[2:0]:
11.11.1.8
•
•
Data Sheet
Read back index register. This is used for selecting what to read back from DTST.
(Default 00)
- 3'B000 - Port 0 Operating mode and Negotiation status
- 3'B001 - Port 1 Operating mode and Negotiation status
- 3'B010 - Port 2 Operating mode and Negotiation status
- 3'B011 - Port 3 Operating mode and Negotiation status
- 3'B100 - Port 4 Operating mode and Negotiation status
- 3'B101 - Port 5 Operating mode and Negotiation status
- 3'B110 - Port 6 Operating mode and Negotiation status
- 3'B111 - Port 7 Operating mode and Negotiation status
DTST - Data Read Back Register
CPU Address: hF07
Accessed by CPU and serial interface (RO)
7
6
5
4
3
2
1
0
MD
InfoDet
SigDet
Giga
lnkdn
FE
Fdpx
Fc_en
This register provides various internal information as selected in DPST bit[2:0]
Bit[0]:
Flow control enabled
Bit[1]:
Full duplex port
Bit[2]:
Fast ethernet port (if not giga)
Bit[3]:
Link is down
Bit[4]:
GIGA port
Bit[5]:
Signal detect (when PCS interface mode)
Bit[6]:
Pipe signal detected (pipe mode only)
Bit[7]:
Module detected (for hot swap purpose)
129
Zarlink Semiconductor Inc.
MVTX2804
12.0
BGA and Ball Signal Description
12.1
BGA Views (Top-View)
A
1
2
AVDD
NC9
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Data Sheet
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SCAN_ LB_D[0] LB_D[4] LB_D[5] LB_D[10 LB_D[16 LB_D[19] LB_D[26 LB_D[31 LB_D[32 LB_D[36 LB_D[40 LB_D[45 S_CLK LB_D[60 LB_A[3] LB_A[7] LB_A[11 LB_A[15 B_A[16] B_A[12] B_A[7]
EN
]
]
]
]
]
]
]
]
]
]
]
B_A[2]
B_OE# B_D[27] B_D[26]
NC4
NC3
LB_D[1] LB_D[3] LB_D[6] LB_D[12 LB_D[17 LB_D[20] LB_D[28 LB_CS0 LB_D[33 LB_D[37 LB_D[41 LB_D[47 LB_D[54 LB_D[58 LB_D[62 LB_A[6] LB_A[10 LB_A[13 B_A[17] B_A[13] B_A[8]
]
]
]
#
]
]
]
]
]
]
]
]
]
B_A[3]
B_WE# B_D[30] DEV_CF
G[1]
NC5
B_D[25]
B
DEV_CF LA_D[0]
[0]
C
LA_D[1] LA_CLK LA_D[3]
NC6
LB_D[2] LB_D[8] LB_D[15 LB_D[18 LB_D[21]
]
]
D
LA_D[2] LA_D[5] LA_D[9]
NC8
LB_CLK LB_D[9] LB_D[13 LB_D[23 LB_D[22] LB_D[24 LB_D[25 LB_D[35 LB_D[42 LB_D[44 LB_D[50 LB_D[51 LB_D[55 LB_D[63 LB_A[14 LB_A[18 LB_A[16 LB_A[19 B_A[9] B_A[10] B_ADSC
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
#
E
LA_D[8] LA_D[7] LA_D[6] LA_D[4]
F
LA_D[10 LA_D[11 LA_D[1 LA_D[13] LA_D[14
]
]
2]
]
VSS
G
LA_D[15 LA_D[16 LA_D[1 LA_D[18] LA_D[17
]
]
9]
]
VDD
H
LA_D[20 LA_D[21 LA_D[2 LA_D[29] LA_D[24
]
]
2]
]
J
LA_D[23 LA_D[25 LA_D[2 LA_D[27] LA_D[31
]
]
6]
]
VDD
K
LA_D[28 LA_D[30 LA_CS0 LA_D[37] LA_D[33
]
]
]
#
VDD
L
LA_CS1 LA_RW# LA_D[3 LA_D[46] LA_D[41
#
2]
]
M
LA_D[34 LA_D[35 LA_D[3 LA_D[53] LA_D[48
]
]
6]
]
VCC
N
LA_D[38 LA_D[40 LA_D[4 LA_D[61] LA_D[56
]
]
2]
]
VCC
VSS
VSS
VSS
VSS
VSS
P
LA_D[43 LA_D[44 LA_D[4 LA_A[4] LA_D[39
]
]
5]
]
VCC
VSS
VSS
VSS
VSS
R
LA_D[49 LA_D[50 LA_D[5 LA_D[52] LA_D[47
]
]
1]
]
VSS
VSS
VSS
VSS
T
LA_D[58 LA_D[57 LA_D[5 LA_D[54] LA_A[7]
]
]
5]
VSS
VSS
VSS
U
LA_D[63 LA_D[62 LA_D[6 LA_D[59] LA_A[11
]
]
0]
]
VCC
VSS
V
LA_A[6] LA_A[5] LA_A[3] LA_A[14] LA_A[18
]
VCC
VSS
W
LA_A[10 LA_A[9] LA_A[8] LA_A[20] G0_TXD
]
[1]
VCC
Y
LA_A[15 LA_A[13 LA_A[12 G0_CRS/ G0_TXD
]
]
]
L
[4]
NC7
AGND
L_D[29] LB_RW# LB_D[34 LB_D[39 LB_D[43 LB_BD[4 LB_D[52 LB_D[57 LB_D[61 LB_A[4] LB_A[8] LB_A[12 B_A[18] B_A[14] B_A[11] B_A[5]
]
]
]
8]
]
]
]
]
LB_D[7] LB_D[14 LB_D[11 LB_D[27] LB_D[30 LB_CS1 LB_D[38 LB_D[46 LB_D[49 LB_D[53 LB_D[56 LB_D[59 LB_A[5] LB_A[9] LB_A[17 LB_A[20 B_A[15] B_A[6] B_D[31]
]
]
]
#
]
]
]
]
]
]
]
]
VSS
VDD
VDD
VCC
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VDD
VDD
VSS
AGND
VSS
VDD
B_A[4] B_D[28]
NC2
AVDD
B_CLK B_D[22]
B_D[29] B_D[24] B_D[18] B_D[21]
B_D[17] B_D[23] B_D[19] B_D[16] B_D[14]
NC1
B_D[9] B_D[10] B_D[11] B_D[12]
B_D[20] B_D[4]
B_D[3]
B_D[6]
B_D[7]
B_D[15] B_D[8]
P_INT#
B_D[1]
B_D[2]
VDD
B_D[13] P_A[1]
P_A[2]
P_WE# P_RD#
VDD
B_D[5] P_D[15] P_D[11] P_D[12] P_D[13]
P_CS# P_D[14] P_D[7]
P_D[8] P_D[10]
VCC
P_A[0]
B_D[0]
P_D[3]
P_D[4]
P_D[5]
VSS
VCC
P_D[6]
P_D[9]
P_D[0]
P_D[1]
P_D[2]
VSS
VSS
VCC
T_D[15] T_D[11] T_D[12] T_D[13] T_D[14]
VSS
VSS
VSS
VSS
T_D[10] T_D[5]
T_D[7]
T_D[8]
T_D[9]
VSS
VSS
VSS
VSS
VSS
T_D[6]
T_D[2]
T_D[1]
T_D[0]
VSS
VSS
VSS
VSS
VSS
VCC
S_RST# T_D[3] TMODE[ TMODE[ RESOU
1]
0]
T#
VSS
VSS
VSS
VSS
VSS
VCC
G7_RX G7_RX_ LESYNO LE_CLK LE_DO
D[7]
ER
#
0
VCC
G7_RX G7_RXD G7_RX_ G7_RXD G7_RXD
D[3]
[1]
DV
[6]
[5]
T_D[4]
G7_TXD G7_TX_ G7_RXD G7_RXD G7_RXD
[6]
EN
[4]
[2]
[0]
AA LA_A[19 LA_A[17 LA_A[16 GREFC[ G0_TXD
]
]
]
0]
[7]
VDD
VDD
G7_TXD G7_TXD G7_COL G7_RXC MIITXCK
[0]
[3]
LK
[7]
AB MIITXCK G0_TXD G0_TX G0_TXC G0_TX_
[0]
[2]
D[0]
LK
ER
VDD
VDD
G6_RX G7_TX_ G7_TXD G7_TXD G7_TXD
D[7]
ER
[7]
[5]
[4]
AC G0_RXC G0_TXD G0_TX G0_RXD[ G0_RXD
LK
[5]
D[3]
2]
[6]
G6_RXD G6_RXD G7_TXD G7_TXD G7_CRS
[2]
[4]
[2]
[1]
/L
AD G0_RXD G0_TX_ G0_CO G0_TXD[ G0_RX_
[0]
EN
L
6]
DV
VSS
AE G0_RXD G0_RXD G0_RX G0_RXD[ G1_TXD
[5]
[4]
D[3]
1]
[0]
VSS
VDD
VDD
VDD
VCC
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VDD
VDD
VSS
VDD
G6_RX G6_RX_ G7_TXC GREFC[ G6_RX_
D[0]
ER
LK
7]
DV
VSS
G6_TXD G6_RXD G6_RXD G6_RXD G6_RXD
[7]
[6]
[5]
[3]
[1]
AF G0_RXD G0_RX_ GREFC[ G1_RXD[ G1_RXD G1_RXD G2_TXD G2_TXD G2_RXD[2] G2_RXD G2_RXD G3_TXD G3_TXD G3_COL G3_RXD G3_RXD IND_CM G3_RXD G3_RX_ G4_TXD G4_RXD G4_RXD G5_TXD G5_TXD G5_TX_ G5_RXD G6_RXC G6_TXD G6_COL G6_TX_
[7]
ER
1]
2]
[5]
[7]
[0]
[7]
[4]
[5]
[1]
[6]
[3]
[6]
[4]
ER
[3]
[1]
[4]
[2]
[4]
ER
[5]
LK
[6]
ER
AG G1_TXD G1_TXC G1CRS/ G1_TXD[ G2_TXC G1_RXD G2_TXD G2_TXD G2_RXD[3] G2_RXC G2_RXD G2_RX_ G3_TX_ G3_RXD G3_RXD G3_RXD GREFC[ M_MDIO G4_TXD G4_RXD G4_RXD G4_RXD G5_CRS G5_TXD MIITXCK G5_RXD G6_TXD G6_TXD G6_TX_ G6_TXD
[1]
LK
L
7]
LK
[4]
[4]
[3]
LK
[7]
ER
EN
[0]
[5]
[7]
4]
[1]
[5]
[6]
[7]
/L
[5]
[5]
[1]
[3]
[4]
EN
[5]
AH G1_TXD G1_TXD MIITXC G1_RXD[ G1_RXC G2CRS/ MIITXCK G2_TX_ G2_RXD[1] G2_RX_ G3_TXC G3_TXD G3_TXD G3_RXC G3_RXD G3_RX_ G4_TXC G4_TXD G4_TXD G4_TX_ G4_RXC G4_RX_ G4_RX_ G5_TXD G5_TX_ G5_RXD G5_RXD G6_TXD G6_TXD G6_TXC
[2]
[3]
K[1]
0]
LK
L
[2]
EN
DV
LK
[3]
[5]
LK
[2]
DV
LK
[4]
[6]
ER
LK
DV
ER
[3]
EN
[3]
[6]
[1]
[2]
LK
AJ G1_TXD G1_TXD G1_TX_ G1_COL G1_RXD GREFC[ G2_TXD G2_TXD G2_RXD[0] G2_RXD GREFC[ G3_TXD MIITXCK G3_TX_ G3_RXD M_MDC G4_TXD G4_TXD G4_TXD G4_RXD G4_COL GREFC[ G5_TXD G5_TXD G5_RXD G5_COL G5_RXD G5_RX_ G6_CRS G6_TXD
[5]
[4]
ER
[6]
2]
[2]
[6]
[6]
3]
[2]
[3]
ER
[1]
[0]
[5]
[7]
[0]
5]
[0]
[6]
[0]
[4]
ER
/L
[0]
AK G1_TXD G1_TX_ G1_RX G1_RXD[ G1_RX_ G1_RX_ G2_TXD G2_TXD G2_TX_ER G2_COL G3_CRS G3_TXD G3_TXD G3_TXD CM_CLK G4CRS/ G4_TXD MIITXCK G4_TX_ G4_RXD G4_RXD G5_TXC G5_TXD G5_TXD G5_RXD G5_RXC G5_RXD G5_RX_ MIITXCK GREFC[
[6]
EN
D[1]
3]
DV
ER
[1]
[5]
/L
[0]
[4]
[7]
L
[2]
[4]
EN
[2]
[3]
LK
[1]
[7]
[2]
LK
[7]
DV
[6]
6]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
130
Zarlink Semiconductor Inc.
18
19
20
21
22
23
24
25
26
27
28
29
30
MVTX2804
12.2
Data Sheet
Ball-Signal Descriptions
All pins are CMOS type; all Input pins are 5 Volt tolerance, and all output pins are 3.3 CMOS drive.
12.2.1
Ball Signal Description in Managed Mode
Ball No(s)
Symbol
I/O
Description
CPU Bus Interface
K27, L27, K30, K29, K28,
L30, N27, L29, L28, N26,
M30, M29, M28, N30,
N29, N28
P_DATA[15:0] I/O-TS with pull up
Processor Bus Data Bit [15:0]
J28, J27, M26
P_A[2:0]
Input
Processor Bus Address Bit [2:0]
J29
P_WE#
Input with weak internal
pull up
CPU Bus-Write Enable
J30
P_RD#
Input with weak internal
pull up
CPU Bus-Read Enable
L26
P_CS#
Input with weak internal
pull up
Chip Select
H28
P_INT#
Output
CPU Interrupt
Frame Buffer Interface
U1, U2, N4, U3, U4, T1,
T2, N5, T3, T4, M4, R4,
R3, R2, R1, M5, R5, L4,
P3, P2, P1, N3, L5, N2,
P5, N1, K4, M3, M2, M1,
K5, L3, J5, K2, H4, K1,
J4, J3, J2, H5, J1, H3,
H2, H1, G3, G4, G5, G2,
G1, F5, F4, F3, F2, F1,
D3, E1, E2, E3, D2., E4,
C3, D1, C1, B2
LA_D[63:0]
I/O-TS with pull up
Frame Bank A- Data Bit [63:0]
AA1, V5, AA2, AA3, Y1,
V4, Y2, Y3, U5, W1, W2,
W3, T5, V1, V2, P4, V3
LA_A[19:3]
Output
Frame Bank A - Address Bit [19:3]
W4
LA_A[20]
Output with pull up
Frame Bank A - Address Bit [20]
C2
LA_CLK
Output
Frame Bank A Clock Input
K3
LA_CS0#
Output with pull up
Frame Bank A Low Portion Chip
Selection
L1
LA_CS1#
Output with pull up
Frame Bank A High Portion Chip
Selection
L2
LA_RW#
Output with pull up
Frame Bank A Read/Write
131
Zarlink Semiconductor Inc.
MVTX2804
Ball No(s)
Symbol
I/O
Data Sheet
Description
CPU Bus Interface
D18, B18, C18, A17, E17,
B17, C17, E16, D17, B16,
E15, C16, D16, D15, E14,
C15, B15, E13, A15, D14,
C14, D13, B14, A14, C13,
E12, B13, A13, D12, C12,
B12, A12, A11, E10, C10,
B10, E9, A10, D11, D10,
D8, D9, C9, B9, A9, C8,
B8, A8, C7, E7, D7, B7,
E8, A7, D6, C6, E6, B6,
A6, A5, B5, C5, B4,A4
LB_D[63:0]
I/O-TS with pullup
Frame Bank B- Data Bit [63:0]
D22, D20, E20, D21, A21,
D19, B21, C21, A20, B20,
E19, C20, A19, B19, E18,
C19, A18
LB_A[19:3]
Output
Frame Bank B - Address Bit [19:3]
E21
LB_A[20]
Output with pull up
Frame Bank B - Address Bit [20]
D5
LB_CLK
Output
Frame Bank B Clock Input
B11
LB_CS0#
Output with pull up
Frame Bank B Low Portion Chip
Selection
E11
LB_CS1#
Output with pull up
Frame Bank B High Portion Chip
Selection
C11
LB_RW#
Output with pull up
Frame Bank B Read/Write
E24,B27, D27, C27, A27,
A28, B30, D28, E27, C30,
D30, G26, E28, D29,
E26, E29, H26, E30, J26,
F30, F29, F28, F27, H27,
G30, G29, K26, G27,
G28, H30, H29, M27
B_D[31:0]
I/O-TS with pull up
Switch Database Domain
C22, B22, A22, E22, C23,
B23, A23, C24, D24, D23,
B24, A24, E23, C25, C26,
B25, A25
B_A[18:2]
Switch Database Interface
- Data Bit [31:0]
Output
Switch Database Address (512K)
- Address Bit [18:2]
C29
B_CLK
Output
Switch Database Clock Input
D25
B_ADSC#
Output with pull up
Switch Database Address Status
Control
B26
B_WE#
Output with pull up
Switch Database Write Chip Select
A26
B_OE#
Output with pull up
Switch Database Read Chip Select
M_MDC
Output
MII Management Data Clock - (common
for all MII Ports [7:0])
MII Management Interface
AJ16
132
Zarlink Semiconductor Inc.
MVTX2804
Ball No(s)
Symbol
I/O
Data Sheet
Description
CPU Bus Interface
AG18
M_MDIO
I/O-TS with pull up
MII Management Data I/O (common for all MII Ports -[7:0]))
2.5Mhz
GMII / MII Interface (193) Gigabit Ethernet Access Port
GREF_CLK
[7:0]
Input w/ pull up
Giga Reference Clock
AK15
CM_CLK
Input w/ pull up
Common Clock shared by port G[7:0]
AF17
IND/CM
Input w/ pull up
1: select GREF_CLK[7:0] as clock
0: select CM_CLK as clock for all ports
AA30, AK29, AG25,
AK18, AJ13, AH7, AH3,
AB1
MII TX
CLK[7:0]
Input w/ pull up
Input w/ pull up
V26, W29, W30, Y28,
W26, Y29, W27, Y30,
G7_RXD[7:0]
Input w/ pull up
G[7:0] port - Receive Data Bit [7:0]
AB26, AE27, AE28,
AC27, AE29, AC26,
AE30, AD26
G6_RXD[7:0]
AK27, AH27, AF26, AJ27,
AH26, AK25, AG26, AJ25
G5_RXD[7:0]
AG22, AG21, AG20,
AF22, AK21, AK20,
AF21, AJ20
G4_RXD[7:0]
AG16, AF16, AG15,
AF18, AF15, AH15, AJ15,
AG14
G3_RXD[7:0]
AG11, AJ10, AF11, AF10,
AG9, AF9, AH9, AJ9
G2_RXD[7:0]
AF6, AJ5, AF5, AG6,
AK4, AF4, AK3, AH4
G1_RXD[7:0]
AF1, AC5, AE1, AE2,
AE3, AC4, AE4, AD1
G0_RXD[7:0]
AD29, AK30, AJ22,
AG17, AJ11, AJ6,
AF3,AA4
W28, AD30, AK28, AH22,
AH16, AH10, AK5, AD5
G[7:0]_RX_DV Input w/ pull down
G[7:0]port - Receive Data Valid
V27, AD27, AJ28, AH23,
AF19, AG12, AK6, AF2
G[7:0]_RX_ER Input w/ pull up
G[7:0]port - Receive Error
AC30, AJ29, AG23,
AK16, AK11, AH6, AG3,
Y4
G[7:0]_CRS/LI Input w/ pull down
NK
G[7:0]port - Carrier Sense
133
Zarlink Semiconductor Inc.
MVTX2804
Ball No(s)
Symbol
I/O
Data Sheet
Description
CPU Bus Interface
AA28, AF29, AJ26,
AJ21, AF14, AK10, AJ4,
AD3
AA29, AF27, AK26,
AH21, AH14, AG10,
AH5, AC1
G[7:0]_COL
Input w/ pull up
G[7:0]_RXCLK Input w/ pull up
AB28, Y26, AB29, AB30,
AA27, AC28, AC29, AA26
G7_TXD[7:0]
AE26, AF28, AG30,
AG28, AG27, AH29,
AH28, AJ30
G6_TXD[7:0]
AK24, AJ24, AG24,
AF24, AH24, AF23,
AK23, AJ23
G5_TXD[7:0]
AJ19, AH19, AJ18, AH18,
AF20, AK17, AG19, AJ17
G4_TXD[7:0]
AK14, AF13, AH13,
AK13, AH12, AJ12, AF12,
AK12
G3_TXD[7:0]
AF8, AJ8, AK8, AG7,
AG8, AJ7, AK7, AF7
G2_TXD[7:0]
AG4, AK1, AJ1, AJ2,
AH2, AH1, AG1, AE5
G1_TXD[7:0]
AA5, AD4, AC2, Y5, AC3,
AB2, W5, AB3
G0_TXD[7:0]
Output
G[7:0]port - Collision Detected
G[7:0]port - Receive Clock
G[7:0]port - Transmit Data Bit [7:0]
Y27, AG29, AH25, AK19,
AG13, AH8, AK2, AD2
G[7:0]_TX_EN Output w/ pull up
G[7:0]port - Transmit Data Enable
AB27, AF30, AF25,
AH20, AJ14, AK9, AJ3,
AB5
G[7:0]_TX_ER Output w/ pull up
G[7:0]port - Transmit Error
AD28, AH30, AK22,
AH17, AH11, AG5, AG2,
AB4
G[7:0]_
TXCLK
Output
G[7:0]port - Gigabit Transmit Clock
PMA Interface (193) Gigabit Ethernet Access Port (PCS)
GREF_CLK
[7:0]
Input w/ pull up
Gigabit Reference Clock
AK15
CM_CLK
Input w/ pull up
Common Clock shared by port G[7:0]
AF17
IND/CM
Input w/ pull up
I: select GREF_CLK[7:0] as clock
0: select CM_CLK as clock for all port
AD29, AK30, AJ22,
AG17, AJ11, AJ6,
AF3,AA4
134
Zarlink Semiconductor Inc.
MVTX2804
Ball No(s)
Symbol
I/O
Data Sheet
Description
CPU Bus Interface
V26, W29, W30, Y28,
W26, Y29, W27, Y30
G7_RXD[7:0]
AB26, AE27, AE28,
AC27, AE29, AC26,
AE30, AD26
G6_RXD[7:0]
AK27, AH27, AF26, AJ27,
AH26, AK25, AG26, AJ25
G5_RXD[7:0]
AG22, AG21, AG20,
AF22, AK21, AK20,
AF21, AJ20
G4_RXD[7:0]
AG16, AF16, AG15,
AF18, AF15, AH15, AJ15,
AG14
G3_RXD[7:0]
AG11, AJ10, AF11, AF10,
AG9, AF9, AH9, AJ9
G2_RXD[7:0]
AF6, AJ5, AF5, AG6,
AK4, AF4, AK3, AH4
G1_RXD[7:0]
AF1, AC5, AE1, AE2,
AE3, AC4, AE4, AD1
G0_RXD[7:0]
Input w/ pull up
G[7:0]port - PMA Receive Data Bit [7:0]
W28, AD30, AK28,
AH22, AH16, AH10,
AK5, AD5
GP[7:0]_RX_D Input w/ pull down
[8]
G[7:0]port - PMA Receive Data Bit [8]
V27, AD27, AJ28, AH23,
AF19, AG12, AK6, AF2
GP[7:0]_RX_D Input w/ pull up
[9]
G[7:0]port - PMA Receive Data Bit [9]
AA28, AF29, AJ26,
AJ21, AF14, AK10, AJ4,
AD3
AA29, AF27, AK26,
AH21, AH14, AG10,
AH5, AC1
GP[7:0]_
RXCLK 1
Input w/ pull up
G[7:0]port - PMA Receive Clock 1
GP[7:0]_RXCL Input w/ pull up
K0
G[7:0]port - PMA Receive Clock 0
135
Zarlink Semiconductor Inc.
MVTX2804
Ball No(s)
Symbol
I/O
Data Sheet
Description
CPU Bus Interface
AB28, Y26, AB29, AB30,
AA27, AC28, AC29, AA26
G7_TXD[7:0]
Output
G[7:0]port - PMA Transmit Data Bit [7:0]
AE26, AF28, AG30,
AG28, AG27, AH29,
AH28, AJ30
G6_TXD[7:0]
AK24, AJ24, AG24,
AF24, AH24, AF23,
AK23, AJ23
G5_TXD[7:0]
AJ19, AH19, AJ18, AH18,
AF20, AK17, AG19, AJ17
G4_TXD[7:0]
AK14, AF13, AH13,
AK13, AH12, AJ12, AF12,
AK12
G3_TXD[7:0]
AF8, AJ8, AK8, AG7,
AG8, AJ7, AK7, AF7
G2_TXD[7:0]
AG4, AK1, AJ1, AJ2,
AH2, AH1, AG1, AE5
G1_TXD[7:0]
AA5, AD4, AC2, Y5, AC3,
AB2, W5, AB3
G0_TXD[7:0]
Y27, AG29, AH25, AK19,
AG13, AH8, AK2, AD2
GP[7:0]_TXD[
8]
Output w/ pull up
G[7:0]port - PMA Transmit Data Bit [8]
AB27, AF30, AF25,
AH20, AJ14, AK9, AJ3,
AB5
GP[7:0]_TXD[
9]
Output w/ pull up
G[7:0]port - PMA Transmit Data Bit [9]
AD28, AH30, AK22,
AH17, AH11, AG5, AG2,
AB4
G[7:0]_
TXCLK
Output
G[7:0]port - PMA Gigabit Transmit Clock
Test Facility (3)
U29
T_MODE0
I/O-TS with pull up
Test - Set upon Reset, and provides
NAND Tree test output during test mode
Use external Pull up for normal
operation
U28
T_MODE1
I/O-TS with pull up
Test - Set upon Reset, and provides
NAND Tree test output during test mode
Use external Pull up for normal
operation
A3
SCAN_EN
Input w/ pull down
Enable test mode
For normal operation leave it open
136
Zarlink Semiconductor Inc.
MVTX2804
Ball No(s)
Symbol
Data Sheet
I/O
Description
CPU Bus Interface
LED Interface (serial and parallel)
R28, T26, R27, T27, U27,
T28, T29, T30
T_D[7:0]/
Output
While resetting, T_D[7,0] are in input
mode and are used as strapping pins.
Internal pullup
LED_PD - Parallel Led data [7:0]
Output
While resetting, T_D[15:8] are in input
mode and are used as strapping pins.
Internal pullup
LED_PD[7:0]
P26, P30, P29, P28, P27,
R26, R30, R29
T_D[15:8]/
LED_PT[7:0]
LED_PR[7:0] - Parallel Led port sel [7:0]
V29
LED_CLK0/
Output
LED_CLK0 - LED Serial Interface
Output Clock
LED_PT[8]
LED_PT[8] - Parallel Led port sel [8]
V30
LED_BLINK/
LED_DO/
LED_PT[9]
Output
While resetting, LED-BLINK is in input
mode and is used as strapping pin. 1:
No Blink, 0: Blink. Internal pullup.
LED_DO - LED Serial Data Output
Stream
LED_PT[9] - Parallel Led port sel [9]
V28
LED_PM/
Output w/ pull up
LED_SYNCO#
While resetting, LED_PM is in input
mode and is used as strapping pin.
Internal pull up. 1: Enable parallel
interface, 0: enable serial interface.
LED_SYNCO# - LED Output Data
Stream Envelop
System Clock, Power, and Ground Pins
A16
S_CLK
Input
System Clock at 133 MHz
U26
S_RST#
Input - ST
Reset Input
U30
RESOUT#
Output
Reset PHY
B1
DEV_CFG[0]
Input w/ pull down
Not used
B28
DEV_CFG[1]I
Input w/ pull down
Not used
Power core
+2.5 Volt DC Supply
AE7, AE9, F10, F21, F22,
F9, G25, G6, J25, J6,
K25, K6, AA25, AA6,
AB25, AB6, AD25, AE10,
AE21, AE22
VDD
137
Zarlink Semiconductor Inc.
MVTX2804
Ball No(s)
Symbol
Data Sheet
I/O
Description
CPU Bus Interface
VSS
Ground
Ground
A1, C28
AVDD
Power
Analog +2.5 Volt DC Supply
E5, E25
AVSS
Ground
Analog Ground
AE12, AE13, AE14,
AE17, AE18, AE19, F12,
F13, F14, F17, F18, F19,
M25, M6, N25, N6, P25,
P6, U25, U6, V25, V6,
W25, W6
VCC
Power I/O
+3.3 Volt DC Supply
V14, V15, V16, V17, V18,
F16, F24, F25, F6, F7,
N13, N14, N15, N16,
N17, N18, P13, P14, P15,
P16, P17, P18, R13, R14,
R15, R16, R17, R18,
R25, R6, T13, T14, T15,
T16, T17, T18, T25, T6,
U13, U14, U15, U16,
U17, U18, V13, AD6,
AE15, AE16, AE24,
AE25, AE6, F15
Bootstrap Pins (Default= pull up, 1= pull up 0= pull down)
AD2,AB5
G0_TX_EN
G0_TX_ER
Default: PCS
Giga0
Mode: G0_TXEN G0_TXER
0
0
MII
0
1
Rsvd
1
0
GMII
1
1
PCS
AK2,AJ3
G1_TX_EN
G1_TXER
Default: PCS
Giga1
Mode: G1_TXEN G1_TXER
0
0
MII
0
1
Rsvd
1
0
GMII
1
1
PCS
AH8,AK9
G2_TX_EN
G2_TX_ER
Default: PCS
Giga2
Mode: G2_TXEN G2_TXER
0
0
MII
0
1
Rsvd
1
0
GMII
1
1
PCS
AG13,AJ14
G3_TX_EN
G3_TX_ER
Default: PCS
Giga3
Mode: G3_TXEN G3_TXER
0
0
MII
0
1
Rsvd
1
0
GMII
1
1
PCS
138
Zarlink Semiconductor Inc.
MVTX2804
Ball No(s)
Symbol
I/O
Data Sheet
Description
CPU Bus Interface
AK19,AH20
G4_TX_EN
G4_TX_ER
Default: PCS
Giga4
Mode: G4_TXEN G4_TXER
0
0
MII
0
1
Rsvd
1
0
GMII
1
1
PCS
AH25,AF25
G5_TX_EN
G5_TX_ER
Default: PCS
Giga5
Mode: G5_TXEN G5_TXER
0
0
MII
0
1
Rsvd
1
0
GMII
1
1
PCS
AG29,AF30
G6_TX_EN
G6_TX_ER
Default: PCS
Giga6
Mode: G6_TXEN G6_TXER
0
0
0
1
1
0
1
1
MII
Rsvd
GMII
PCS
Giga7
Mode: G7_TXEN G7_TXER
0
0
0
1
1
0
1
1
MII
Rsvd
GMII
PCS
Y27,AB27
G7_TX_EN
G7_TX_ER
Default: PCS
After reset T_D[15:0] are used by the LED interface
T30
T_D[0]
1
Giga link active status
0 - active low
1 - active high
T29
T_D[1]
1
Power saving
0 - No power saving
1 - Power saving
Stop MAC clock if no MAC activity.
T28
T_D[2]
Must be pulled-down
Reserved - Must be pulled-down
U27
T_D[3]
1
Hot plug port module detection enable
0 - module detection enable
1 - module detection disable
T27
T_D[4]
Must be pulled-down
Reserved - Must be pulled-down
R27
T_D[5]
1
SRAM memory size
0 - 512K SRAM
1 - 256K SRAM
T26
T_D[6]
1
CPU Port mode
0 – 8 bit cpu data bus
1 – 16 bit cpu data bus
R28
T_D[7]
1
FDB memory depth
1- one memory layer
0 - two memory layers
139
Zarlink Semiconductor Inc.
MVTX2804
Ball No(s)
Symbol
Data Sheet
I/O
Description
CPU Bus Interface
W4, E21
LA_A[20],
LB_A[20]
1
FDB memory size
11 - 2M per bank = 4M total
10 - 1M per bank = 2M total
0x - 512K per bank = 1M total
R29
T_D[8]
1
EEPROM installed
0 - EEPROM is installed
1 - EEPROM is not installed
R30
T_D[9]
1
MCT Aging enable
0 - MCT aging disable
1 - MCT aging enable
R26
T_D[10]
1
FCB handle aging enable
0 - FCB handle aging disable
1 - FCB handle aging enable
P27
T_D[11]
1
Timeout reset enable
0 - timeout reset disable
1 - timeout reset enable
Issue reset if any state machine did not
go back to idle for 5sec.
T_D[13:12]
1
Reserved
P30
T_D[14]
1
CPU installed
0 - CPU installed
1 - CPU is not installed
P26
T_D[15]
1
External RAM test
0 - Perform the infinite loop of ZBT
RAM BIST. Debug test only
1 - Regular operation.
P28, P29
After reset P_D[8:0] are used by the CPU bus interface
N30, N29, N28
P_D[2:0]
111
ZBT RAM la_clk turning
3'b000 - control by reg. LCLKCR[2:0]
3'b001 - delay by method # 0
3'b010 - delay by method # 1
3'b011 - delay by method # 2
3'b100 - delay by method # 3
3'b101 - delay by method # 4
3'b110 - delay by method # 5
3'b111 - delay by method # 6
USE METHOD 6 FOR NORMAL
OPERATION. External pull up not
required
140
Zarlink Semiconductor Inc.
MVTX2804
Ball No(s)
Symbol
I/O
Data Sheet
Description
CPU Bus Interface
M30, M29, M28
P_D[5:3]
111
ZBT RAM lb_clk turning
3'b000 - control by reg. LCLKCR[6:4]
3'b001 - delay by method # 0
3'b010 - delay by method # 1
3'b011 - delay by method # 2
3'b100 - delay by method # 3
3'b101 - delay by method # 4
3'b110 - delay by method # 5
3'b111 - delay by method # 6
USE METHOD 6 FOR NORMAL
OPERATION. External pull up not
required
L29, L28, N26
P_D[8:6]
111
SBRAM b_clk turning
3'b000 - control by BCLKCR[2:0]
3'b001 - delay by method # 0
3'b010 - delay by method # 1
3'b011 - delay by method # 2
3'b100 - delay by method # 3
3'b101 - delay by method # 4
3'b110 - delay by method # 5
3'b111 - delay by method # 6
USE METHOD 6 FOR NORMAL
OPERATION. External pull up not
required
Notes
# =
Input =
In-ST =
Output =
Out-OD=
I/O-TS =
I/O-OD =
Active low signal
Input signal
Input signal with Schmitt-Trigger
Output signal (Tri-State driver)
Output signal with Open-Drain driver
Input & Output signal with Tri-State driver
Input & Output signal with Open-Drain driver
141
Zarlink Semiconductor Inc.
MVTX2804
12.2.2
Data Sheet
Ball - Signal Description in Unmanaged Mode
Ball No(s)
Symbol
K27, L27, K30, K29, K28
P_DATA[15:11]
I/O-TS with pull up
Not used - leave unconnected
L30
P_DATA[10]
I/O - TS with pull up
Trunk enable in unmanaged mode
External pull up or unconnected disable trunk group 0 and 1
External pull down - enable trunk
group 0 and 1
See register TRUNK0_MODE for
port selection and trunk enable.
N27
P_DATA[9]
I/O - TS with pull up
Trunk enable in unmanaged mode
External pull up or unconnected disable trunk group 2 and 3
External pull down - enable trunk
group 2 and 3
See register TRUNK1_MODE for
port selection and trunk enable
P_DATA[8:0]
I/O - TS with pull up
Bootstrap function - See bootstrap
section
L29, L28, N26, M30, M29,
M28, N30, N29, N28
I/O
Description
J28
P_A[2]
Input
Not used - leave unconnected
H28
P_INT#
Output with internal
weak pullup
Not used - leave unconnected
I2C Interface (0) Note: In unmanaged mode, Use I2C and Serial control interface to configure the system
J27
SCL
Output
I2C Data Clock
M26
SDA
I/O-TS with pull up
I2C Data I/O
Serial Control Interface
J29
PS_STROBE
Input with weak internal
pull up
Serial Strobe Pin
J30
PS_DI
Input with weak internal
pull up
Serial Data Input
L26
PS_DO
(AUTOFD)
Output with pull up
Serial Data Output (AutoFD)
U1, U2, N4, U3,
U4,T1,T2, N5, T3, T4,
M4, R4, R3, R2, R1, M5,
R5, L4, P3, P2, P1,
N3,L5, N2, P5, N1, K4,
M3, M2, M1, K5, L3, J5,
K2, H4, K1, J4, J3, J2,
H5, J1, H3, H2, H1, G3,
G4, G5, G2, G1, F5, F4,
F3, F2, F1, D3, E1,E2,E3,
D2., E4, C3, D1, C1, B2
LA_D[63:0]
I/O-TS with pull up
Frame Bank A- Data Bit [63:0]
AA1, V5, AA2, AA3, Y1,
V4, Y2, Y3, U5, W1, W2,
W3, T5, V1, V2, P4, V3
LA_A[19:3]
Output
Frame Bank A - Address Bit [19:3]
Frame Buffer Interface
142
Zarlink Semiconductor Inc.
MVTX2804
Ball No(s)
Symbol
I/O
Data Sheet
Description
W4
LA_A[20]
Output with pull up
Frame Bank A - Address Bit [20]
C2
LA_CLK
Output
Frame Bank A Clock Input
K3
LA_CS0#
Output with pull up
Frame Bank A Low Portion Chip
Selection
L1
LA_CS1#
Output with pull up
Frame Bank A High Portion Chip
Selection
L2
LA_RW#
Output with pull up
Frame Bank A Read/Write
D18, B18, C18, A17, E17,
B17, C17, E16, D17, B16,
E15, C16, D16, D15, E14,
C15, B15, E13, A15, D14,
C14, D13, B14, A14, C13,
E12, B13, A13, D12, C12,
B12, A12, A11, E10, C10,
B10, E9, A10, D11, D10,
D8, D9, C9, B9, A9, C8,
B8, A8, C7, E7, D7, B7,
E8, A7, D6, C6, E6, B6,
A6, A5, B5, C5, B4,A4
LB_D[63:0]
I/O-TS with pull up
Frame Bank B- Data Bit [63:0]
D22, D20, E20, D21, A21,
D19, B21, C21, A20, B20,
E19, C20, A19, B19, E18,
C19, A18
LB_A[19:3]
Output
Frame Bank B - Address Bit [19:3]
E21
LB_A[20]
Output with pull up
Frame Bank B - Address Bit [20]
D5
LB_CLK
Output
Frame Bank B Clock Input
B11
LB_CS0#
Output with pull up
Frame Bank B Low Portion Chip
Selection
E11
LB_CS1#
Output with pull up
Frame Bank B High Portion Chip
Selection
C11
LB_RW#
Output with pull up
Frame Bank B Read/Write
E24,B27, D27, C27, A27,
A28, B30, D28, E27, C30,
D30, G26, E28, D29,
E26, E29, H26, E30, J26,
F30, F29, F28, F27, H27,
G30, G29, K26, G27,
G28, H30, H29, M27
B_D[31:0]
Output with pull up
Switch Database Domain
- Data Bit [31:0]
C22, B22, A22, E22, C23,
B23, A23, C24, D24, D23,
B24, A24, E23, C25, C26,
B25, A25
B_A[18:2]
Output
Switch Database Address (512K)
- Address Bit [18:2]
C29
B_CLK
Output
Switch Database Clock Input
D25
B_ADSC#
Output with pull up
Switch Database Address Status
Control
B26
B_WE#
Output with pull up
Switch Database Write Chip Select
A26
B_OE#
Output with pull up
Switch Database Read Chip Select
Switch Database Interface
143
Zarlink Semiconductor Inc.
MVTX2804
Ball No(s)
Symbol
I/O
Data Sheet
Description
MII Management Interface
AJ16
M_MDC
Output
MII Management Data Clock (common for all MII Ports [7:0])
AG18
M_MDIO
I/O-TS with pull up
MII Management Data I/O (common for all MII Ports -[7:0]))
2.5Mhz
Ball No(s)
Symbol
I/O
Description
GMII / MII Interface (193) Gigabit Ethernet Access Port
GREF_CLK [7:0]
Input w/ pull up
Gigabit Reference Clock
AK15
CM_CLK
Input w/ pull up
Common Clock shared by port G[7:0]
AF17
IND/CM
Input w/ pull up
1: select GREF_CLK[7:0] as clock
0: select CM_CLK as clock for all ports
MII TX CLK[7:0]
Input w/ pull up
V26, W29, W30, Y28,
W26, Y29, W27, Y30
G7_RXD[7:0]
Input w/ pull up
G[7:0] port - Receive Data Bit [7:0]
AB26, AE27, AE28,
AC27, AE29, AC26,
AE30, AD26
G6_RXD[7:0]
AK27, AH27, AF26, AJ27,
AH26, AK25, AG26, AJ25
G5_RXD[7:0]
AG22, AG21, AG20,
AF22, AK21, AK20,
AF21, AJ20
G4_RXD[7:0]
AG16, AF16, AG15,
AF18, AF15, AH15, AJ15,
AG14
G3_RXD[7:0]
AG11, AJ10, AF11, AF10,
AG9, AF9, AH9, AJ9
G2_RXD[7:0]
AF6, AJ5, AF5, AG6,
AK4, AF4, AK3, AH4
G1_RXD[7:0]
AF1, AC5, AE1, AE2,
AE3, AC4, AE4, AD1
G0_RXD[7:0]
AD29, AK30, AJ22,
AG17, AJ11, AJ6,
AF3,AA4
AA30, AK29, AG25,
AK18, AJ13, AH7, AH3,
AB1
W28, AD30, AK28, AH22,
AH16, AH10, AK5, AD5
G[7:0]_RX_DV
Input w/ pull down
G[7:0]port - Receive Data Valid
V27, AD27, AJ28, AH23,
AF19, AG12, AK6, AF2
G[7:0]_RX_ER
Input w/ pull up
G[7:0]port - Receive Error
144
Zarlink Semiconductor Inc.
MVTX2804
Ball No(s)
Symbol
I/O
AC30, AJ29, AG23,
AK16, AK11, AH6, AG3,
Y4
G[7:0]_CRS/LINK
AA28, AF29, AJ26, AJ21,
AF14, AK10, AJ4, AD3
Data Sheet
Description
Input w/ pull down
G[7:0]port - Carrier Sense
G[7:0]_COL
Input w/ pull up
G[7:0]port - Collision Detected
AA29, AF27, AK26,
AH21, AH14, AG10, AH5,
AC1
G[7:0]_RXCLK
Input w/ pull up
G[7:0]port - Receive Clock
AB28, Y26, AB29, AB30,
AA27, AC28, AC29, AA26
G7_TXD[7:0]
Output
G[7:0]port - Transmit Data Bit [7:0]
AE26, AF28, AG30,
AG28, AG27, AH29,
AH28, AJ30
G6_TXD[7:0]
AK24, AJ24, AG24,
AF24, AH24, AF23,
AK23, AJ23
G5_TXD[7:0]
AJ19, AH19, AJ18, AH18,
AF20, AK17, AG19, AJ17
G4_TXD[7:0]
AK14, AF13, AH13,
AK13, AH12, AJ12, AF12,
AK12
G3_TXD[7:0]
AF8, AJ8, AK8, AG7,
AG8, AJ7, AK7, AF7
G2_TXD[7:0]
AG4, AK1, AJ1, AJ2,
AH2, AH1, AG1, AE5
G1_TXD[7:0]
AA5, AD4, AC2, Y5, AC3,
AB2, W5, AB3
G0_TXD[7:0]
Y27, AG29, AH25, AK19,
AG13, AH8, AK2, AD2
G[7:0]_TX_EN
Output w/ pull up
G[7:0]port - Transmit Data Enable
AB27, AF30, AF25,
AH20, AJ14, AK9, AJ3,
AB5
G[7:0]_TX_ER
Output w/ pull up
G[7:0]port - Transmit Error
AD28, AH30, AK22,
AH17, AH11, AG5, AG2,
AB4
G[7:0]_ TXCLK
Output
G[7:0]port - Gigabit Transmit Clock
PMA Interface (193) Gigabit Ethernet Access Port (PCS)
GREF_CLK [7:0]
Input w/ pull up
Gigabit Reference Clock
AK15
CM_CLK
Input w/ pull up
Common Clock shared by port G[7:0]
AF17
IND/CM
Input w/ pull up
1: select GREF_CLK[7:0] as clock
0: select CM_CLK as clock for all port
AD29, AK30, AJ22,
AG17, AJ11, AJ6,
AF3,AA4
145
Zarlink Semiconductor Inc.
MVTX2804
Ball No(s)
V26, W29, W30, Y28,
W26, Y29, W27, Y30
AB26, AE27, AE28,
AC27, AE29, AC26,
AE30, AD26
Symbol
G7_RXD[7:0]
I/O
Data Sheet
Description
Input w/ pull up
G[7:0]port - PMA Receive Data Bit [7:0]
\
G6_RXD[7:0]
AK27, AH27, AF26, AJ27,
AH26, AK25, AG26, AJ25
G5_RXD[7:0]
AG22, AG21, AG20,
AF22, AK21, AK20,
AF21, AJ20
G4_RXD[7:0]
AG16, AF16, AG15,
AF18, AF15, AH15, AJ15,
AG14
G3_RXD[7:0]
AG11, AJ10, AF11, AF10,
AG9, AF9, AH9, AJ9
G2_RXD[7:0]
AF6, AJ5, AF5, AG6,
AK4, AF4, AK3, AH4
G1_RXD[7:0]
AF1, AC5, AE1, AE2,
AE3, AC4, AE4, AD1
G0_RXD[7:0]
W28, AD30, AK28, AH22,
AH16, AH10, AK5, AD5
G[7:0]_RX_D[8]
Input w/ pull down
G[7:0]port - PMA Receive Data Bit [8]
V27, AD27, AJ28, AH23,
AF19, AG12, AK6, AF2
G[7:0]_RX_D[9]
Input w/ pull up
G[7:0]port - PMA Receive Data Bit [9]
AA28, AF29, AJ26, AJ21,
AF14, AK10, AJ4, AD3
G[7:0]_RXCLK1
Input w/ pull up
G[7:0]port - PMA Receive Clock 1
AA29, AF27, AK26,
AH21, AH14, AG10, AH5,
AC1
G[7:0]_RXCLK0
Input w/ pull up
G[7:0]port - PMA Receive Clock 0
146
Zarlink Semiconductor Inc.
MVTX2804
Ball No(s)
Symbol
AB28, Y26, AB29, AB30,
AA27, AC28, AC29, AA26
G7_TXD[7:0]
AE26, AF28, AG30,
AG28, AG27, AH29,
AH28, AJ30
G6_TXD[7:0]
AK24, AJ24, AG24,
AF24, AH24, AF23,
AK23, AJ23
G5_TXD[7:0]
AJ19, AH19, AJ18, AH18,
AF20, AK17, AG19, AJ17
G4_TXD[7:0]
AK14, AF13, AH13,
AK13, AH12, AJ12, AF12,
AK12
G3_TXD[7:0]
AF8, AJ8, AK8, AG7,
AG8, AJ7, AK7, AF7
G2_TXD[7:0]
AG4, AK1, AJ1, AJ2,
AH2, AH1, AG1, AE5
G1_TXD[7:0]
AA5, AD4, AC2, Y5, AC3,
AB2, W5, AB3
G0_TXD[7:0]
Y27, AG29, AH25, AK19,
AG13, AH8, AK2, AD2
I/O
Data Sheet
Description
Output
G[7:0]port - PMA Transmit Data Bit [7:0]
G[7:0]_TXD[8]
Output w/ pull up
G[7:0]port - PMA Transmit Data Bit [8]
AB27, AF30, AF25,
AH20, AJ14, AK9, AJ3,
AB5
G[7:0]_TX_D[9]
Output w/ pull up
G[7:0]port - PMA Transmit Data Bit [9]
AD28, AH30, AK22,
AH17, AH11, AG5, AG2,
AB4
G[7:0]_ TXCLK
Output
G[7:0]port - PMA Gigabit Transmit Clock
Test Facility (3)
U29
T_MODE0
I/O-TS with pull up
Test - Set upon Reset, and provides
NAND Tree test output during test mode.
Use external Pull up for normal
operation
U28
T_MODE1
I/O-TS with pull up
Test - Set upon Reset, and provides
NAND Tree test output during test mode.
Use external Pull up for normal
operation
A3
SCAN_EN
Input w/ pull down
Enable test mode.
For normal operation leave it open
Output
While resetting, T_D[7,0] are in input
mode and are used as strapping pins.
Internal pullup
LED_PD - Parallel Led data [7:0]
LED Interface (serial and parallel)
R28, T26, R27, T27, U27,
T28, T29, T30
T_D[7:0]/
LED_PD[7:0]
147
Zarlink Semiconductor Inc.
MVTX2804
Data Sheet
Ball No(s)
Symbol
I/O
Description
P26, P30, P29, P28, P27,
R26, R30, R29
T_D[15:8]/
LED_PT[7:0]
Output
While resetting, T_D[15:8] are in input
mode and are used as strapping pins.
Internal pullup
LED_PR[7:0] - Parallel Led port sel [7:0]
V29
LED_CLK0/
LED_PT[8]
Output
LED_CLK0 - LED Serial Interface Output
Clock
LED_PT[8] - Parallel Led port sel [8]
V30
LED_BLINK/
LED_DO/
LED_PT[9]
Output
While resetting, LED-BLINK is in input
mode and is used as strapping pin. 1: No
Blink, 0: Blink. Internal pullup.
LED_DO - LED Serial Data Output
Stream
LED_PT[9] - Parallel Led port sel [9]
V28
LED_PM/
LED_SYNCO#
Output w/ pull up
While resetting, LED_PM is in input
mode and is used as strapping pin.
Internal pull up. 1: Enable parallel
interface, 0: enable serial interface.
LED_SYNCO# - LED Output Data
Stream Envelop
Input
System Clock at 133 MHz
Input - ST
Reset Input
Output
Reset PHY
System Clock, Power, and Ground Pins
A16
S_CLK
U26
S_RST#
U30
RESOUT#
B1
DEV_CFG[0]
Input w/ pull down
Not used
B28
DEV_CFG[1]
Input w/ pull down
Not used
AE7, AE9, F10, F21, F22,
F9, G25, G6, J25, J6,
K25, K6, AA25, AA6,
AB25, AB6, AD25, AE10,
AE21, AE22
VDD
Power core
+2.5 Volt DC Supply
V14, V15, V16, V17, V18,
F16, F24, F25, F6, F7,
N13, N14, N15, N16,
N17, N18, P13, P14, P15,
P16, P17, P18, R13, R14,
R15, R16, R17, R18,
R25, R6, T13, T14, T15,
T16, T17, T18, T25, T6,
U13, U14, U15, U16,
U17, U18, V13, AD6,
AE15, AE16, AE24,
AE25, AE6, F15
VSS
Ground
Ground
A1, C28
AVDD
Power
Analog +2.5 Volt DC Supply
E5, E25
AVSS
Ground
Analog Ground
148
Zarlink Semiconductor Inc.
MVTX2804
Ball No(s)
Symbol
AE12, AE13, AE14,
AE17, AE18, AE19, F12,
F13, F14, F17, F18, F19,
M25, M6, N25, N6, P25,
P6, U25, U6, V25, V6,
W25, W6
VCC
I/O
Power I/O
Data Sheet
Description
+3.3 Volt DC Supply
Bootstrap Pins (Default= pull up, 1= pull up 0= pull down)
AD2,AB5
G0_TX_EN
G0_TX_ER
Default: PCS
Giga0
Mode: G0_TXEN G0_TXER
0
0
MII
0
1
Rsvd
1
0
GMII
1
1
PCS
AK2,AJ3
G1_TX_EN
G1_TXER
Default: PCS
Giga1
Mode: G1_TXEN G1_TXER
0
0
MII
0
1
Rsvd
1
0
GMII
1
1
PCS
AH8,AK9
G2_TX_EN
G2_TX_ER
Default: PCS
Giga2
Mode: G2_TXEN G2_TXER
0
0
MII
0
1
Rsvd
1
0
GMII
1
1
PCS
AG13,AJ14
G3_TX_EN
G3_TX_ER
Default: PCS
Giga3
Mode: G3_TXEN G3_TXER
0
0
MII
0
1
Rsvd
1
0
GMII
1
1
PCS
AK19,AH20
G4_TX_EN
G4_TX_ER
Default: PCS
Giga4
Mode: G4_TXEN G4_TXER
0
0
MII
0
1
Rsvd
1
0
GMII
1
1
PCS
AH25,AF25
G5_TX_EN
G5_TX_ER
Default: PCS
Giga5
Mode: G5_TXEN G5_TXER
0
0
MII
0
1
Rsvd
1
0
GMII
1
1
PCS
AG29,AF30
G6_TX_EN
G6_TX_ER
Default: PCS
Giga6
Mode: G6_TXEN G6_TXER
0
0
0
1
1
0
1
1
149
Zarlink Semiconductor Inc.
MII
Rsvd
GMII
PCS
MVTX2804
Ball No(s)
Y27,AB27
Symbol
G7_TX_EN
G7_TX_ER
Data Sheet
I/O
Default: PCS
Description
Giga7
Mode: G7_TXEN G7_TXER
0
0
0
1
1
0
1
1
MII
Rsvd
GMII
PCS
After reset T_D[15:0] are used by the LED interface
T30
T_D[0]
1
Giga link active status
0 - active low
1 - active high
T29
T_D[1]
1
Power saving
0 - No power saving
1 - Power saving
Stop MAC clock if no MAC activity.
T28
T_D[2]
Must be pulled-down
Reserved - Must be pulled-down
U27
T_D[3]
1
Hot plug port module detection enable
0 - module detection enable
1 - module detection disable
T27
T_D[4]
Must be pulled-down
Reserved - Must be pulled-down
R27
T_D[5]
1
SRAM memory size
0 - 512K SRAM
1 - 256K SRAM
T26
T_D[6]
1
CPU Port mode
0 – 8 bit cpu data bus
1 – 16 bit cpu data bus
R28
T_D[7]
1
FDB memory depth
1- one memory layer
0 - two memory layers
LA_A[20],
LB_A[20]
1
FDB memory size
11 - 2M per bank = 4M total
10 - 1M per bank = 2M total
0x - 512K per bank = 1M total
R29
T_D[8]
1
EEPROM installed
0 - EEPROM is installed
1 - EEPROM is not installed
R30
T_D[9]
1
MCT Aging enable
0 - MCT aging disable
1 - MCT aging enable
R26
T_D[10]
1
FCB handle aging enable
0 - FCB handle aging disable
1 - FCB handle aging enable
P27
T_D[11]
1
Timeout reset enable
0 - timeout reset disable
1 - timeout reset enable
Issue reset if any state machine did not
go back to idle for 5sec.
T_D[13:12]
1
Reserved
W4, E21
P28, P29
150
Zarlink Semiconductor Inc.
MVTX2804
Ball No(s)
Symbol
I/O
Data Sheet
Description
P30
T_D[14]
1
CPU installed
0 - CPU installed
1 - CPU is not installed
P26
T_D[15]
1
External RAM test
0 - Perform the infinite loop of ZBT RAM
BIST. Debug test only
1 - Regular operation.
N30, N29, N28
P_D[2:0]
111
ZBT RAM la_clk turning
3'b000 - control by reg. LCLKCR[2:0]
3'b001 - delay by method # 0
3'b010 - delay by method # 1
3'b011 - delay by method # 2
3'b100 - delay by method # 3
3'b101 - delay by method # 4
3'b110 - delay by method # 5
3'b111 - delay by method # 6 - USE
THIS METHOD
M30, M29, M28
P_D[5:3]1
L29, L28, N26
P_D[8:6]
ZBT RAM lb_clk turning
3'b000 - control by reg. LCLKCR[6:4]
3'b001 - delay by method # 0
3'b010 - delay by method # 1
3'b011 - delay by method # 2
3'b100 - delay by method # 3
3'b101 - delay by method # 4
3'b110 - delay by method # 5
3'b111 - delay by method # 6 - USE
THIS METHOD
111
Notes:
# =
Input =
In-ST =
Output =
Active low signal
Input signal
Input signal with Schmitt-Trigger
Output signal (Tri-State driver)
Out-OD =
I/O-TS =
I/O-OD =
Output signal with Open-Drain driver
Input & Output signal with Tri-State driver
Input & Output signal with Open-Drain driver
SBRAM b_clk turning
3'b000 - control by BCLKCR[2:0]
3'b001 - delay by method # 0
3'b010 - delay by method # 1
3'b011 - delay by method # 2
3'b100 - delay by method # 3
3'b101 - delay by method # 4
3'b110 - delay by method # 5
3'b111 - delay by method # 6- USE
THIS METHOD
151
Zarlink Semiconductor Inc.
MVTX2804
12.3
Ball Signal Name
Ball No.
Signal Name
A1
AVCC
B1
DEV_CFG[0]
B2
LA_D[0]
C2
LA_CLK
C1
LA_D[1]
D1
LA_D[2]
C3
LA_D[3]
E4
LA_D[4]
D2
LA_D[5]
E3
LA_D[6]
E2
LA_D[7]
E1
LA_D[8]
D3
LA_D[9]
F1
LA_D[10]
F2
LA_D[11]
F3
LA_D[12]
F4
LA_D[13]
F5
LA_D[14]
G1
LA_D[15]
G2
LA_D[16]
G5
LA_D[17]
G4
LA_D[18]
G3
LA_D[19]
H1
LA_D[20]
H2
LA_D[21]
H3
LA_D[22]
J1
LA_D[23]
H5
LA_D[24]
J2
LA_D[25]
J3
LA_D[26]
J4
LA_D[27]
K1
LA_D[28]
H4
LA_D[29]
K2
LA_D[30]
M1
LA_D[34]
M2
LA_D[35]
M3
LA_D[36]
K4
LA_D[37]
Ball No.
Signal Name
Data Sheet
Ball No.
Signal Name
N1
LA_D[38]
W4
LA_A[20]
P5
LA_D[39]
Y4
G0_CRS/LNK
N2
LA_D[40]
AA4
GREF_CLK[0]
L5
LA_D[41]
AB4
G0_TXCLK
N3
LA_D[42]
AB3
G0_TXD[0]
P1
LA_D[43]
W5
G0_TXD[1]
P2
LA_D[44]
AB2
G0_TXD[2]
P3
LA_D[45]
AB1
MII_TX_CLK[0]
L4
LA_D[46]
AC3
G0_TXD[3]
R5
LA_D[47]
Y5
G0_TXD[4]
M5
LA_D[48]
AC2
G0_TXD[5]
R1
LA_D[49]
AC1
G0_RXCLK
R2
LA_D[50]
AD3
G0_COL
R3
LA_D[51]
AD4
G0_TXD[6]
R4
LA_D[52]
AA5
G0_TXD[7]
M4
LA_D[53]
AD2
G0_TX_EN
T4
LA_D[54]
AB5
G0_TX_ER
T3
LA_D[55]
AD1
G0_RXD[0]
N5
LA_D[56]
AE4
G0_RXD[1]
T2
LA_D[57]
AC4
G0_RXD[2]
T1
LA_D[58]
AE3
G0_RXD[3]
U4
LA_D[59]
AE2
G0_RXD[4]
U3
LA_D[60]
AE1
G0_RXD[5]
N4
LA_D[61]
AC5
G0_RXD[6]
U2
LA_D[62]
AF1
G0_RXD[7]
U1
LA_D[63]
AD5
G0_RX_DV
V3
LA_A[3]
AF2
G0_RX_ER
P4
LA_A[4]
J5
LA_D[31]
V2
LA_A[5]
K3
LA_CS0#
V1
LA_A[6]
L1
LA_CS1#
Y2
LA_A[13]
L2
LA_RW#
V4
LA_A[14]
L3
LA_D[32]
Y1
LA_A[15]
K5
LA_D[33]
V4
LA_A[14]
AH2
G1_TXD[3]
Y1
LA_A[15]
AJ2
G1_TXD[4]
AA3
LA_A[16]
AJ1
G1_TXD[5]
AA2
LA_A[17]
AK1
G1_TXD[6]
V5
LA_A[18]
AG4
G1_TXD[7]
AA1
LA_A[19]
AK2
G1_TX_EN
152
Zarlink Semiconductor Inc.
MVTX2804
Ball No.
Signal Name
Ball No.
Signal Name
Data Sheet
Ball No.
Signal Name
AH3
MII_TX_CLK[1]
AH11
G3_TXCLK
AJ20
G4_RXD[0]
AJ3
G1_TX_ER
AK12
G3_TXD[0]
AF21
G4_RXD[1]
AH4
G1_RXD[0]
AF12
G3_TXD[1]
AK20
G4_RXF[2]
AK3
G1_RXD[1]
AJ12
G3_TXD[2]
AH21
G4_RXCLK
AF4
G1_RXD[2]
AH12
G3_TXD[3]
AJ21
G4_COL
AK4
G1_RXD[3]
AK13
G3_TXD[4]
AK21
G4_RXD[3]
AH5
G1_RXCLK
AJ13
MII_TX_CLK[3]
AF22
Gr_RXD[4]
AJ4
G1_COL
AH13
G3_TXD[5]
AG20
G4_RXD[5]
AG6
G1_RXD[4]
AF13
G3_TXD[6]
AG21
G4_RXD[6]
AF5
G1_RXD[5]
AK14
G3_TXD[7]
AG22
G4_RXD[7]
AJ5
G1_RXD[6]
AG13
G3_TX_EN
AH22
G4_RX_DV
AF6
G1_RXD[7]
AJ14
G3_TX_ER
AJ22
GREF_CLK[5]
AK5
G1_RX_DV
AH14
G3_RXCLK
AK22
G5_TXCLK
AK6
G1_RX_ER
AF14
G3_COL
AH23
G4_RX_ER
AJ6
GREF_CLK[2]
AG14
G3_RXD[0]
AG23
G5_CRS/LINK
AG5
G2_TXCLK
AK15
CM_CLK
AJ23
G5_TXD[0]
AH6
G2_CRS/LKINK
AF17
IND_CM
AK23
G5_TXD[1]
AF7
G2_TXD[0]
AJ15
G3_RXD[1]
AF23
G5_TXD[2]
AK7
G2_TXD[1]
AH15
G3_RXD[2]
AH24
G5_TXD[3]
AJ7
G2_TXD[2]
AF15
G3_RXD[3]
AF24
G5_TXD[4]
AG8
G2_TXD[3]
AF18
G3_RXD[4]
AG24
G5_TXD[5]
AG7
G2_TXD[4]
AG15
G3_RXD[5]
AF8
G2_TXD[7]
AH7
MII_TX_CLK[2]
AF16
G3_RXD[6]
AH8
G2_TX_EN
AK8
G2_TXD[5]
AF3
GREF_CLK[1]
AK9
G2_TX_ER
AJ8
G2_TXD[6]
AG2
G1_TXCLK
AJ9
G2_RXD[0]
T5
LA_A[7]
AG3
G1_CRS/LINK
AH9
G2_RXD[1]
W3
LA_A[8]
AE5
G1_TXD[0]
AF9
G2_RXD[2]
W2
LA_A[9]
AG1
G1_TXD[1]
AG9
G2_RXD[3]
W1
LA_A[10]
AH1
G1_TXD[2]
AF10
G2_RXD[4]
U5
LA_A[11]
AG19
G4_TXD[1]
AF11
G2_RXD[5]
Y3
LA_A[12]
AK17
G4_TXD[2]
AJ26
G5_COL
AG10
G2_RXCLK
AF20
G4_TXD[3]
AH26
G5_RXD[3]
AK10
G2_COL
AH18
G4_TXD[4]
AJ27
G5_RXD[4]
AJ10
G2_RXD[6]
AJ18
G4_TXD[5]
AF26
G5_RXD[5]
AG11
G2_RXD[7]
AK18
MII_TX_CLK[4]
AH27
G5_RXD[6]
AH10
G2_RX_DV
AH19
G4_TXD[6]
AK27
G5_RXD[7]
AG12
G2_RX_ER
AJ19
G4_TXD[7]
AK28
G5_RX_DV
AK11
G3_CRS/LINK
AK19
G4_TX_EN
AJ28
G5_RX_ER
AJ11
GREF_CLK[3]
AH20
G4_TX_ER
AJ29
G6_CRS/LINK
153
Zarlink Semiconductor Inc.
MVTX2804
Ball No.
Signal Name
Ball No.
Signal Name
Data Sheet
Ball No.
Signal Name
AK29
MII_TX_CLK[6]
W27
G7_RXD[1]
N27
P_D[9]
AK30
GREF_CLK[6]
Y29
G7_RXD{2]
L30
P_D[10]
AH28
G6_TXD[1]
W26
G7_RXD{3]
K28
P_D[11]
AH29
G6_TXD[2]
Y28
G7_RXD{4]
K29
P_D[12]
AG27
G6_TXD[3]
W30
G7_RXD{5]
K30
P_D[13]
AG28
G6_TXD[4]
W29
G7_RXD{6]
L27
P_D[14]
AH30
G6_TXCLK
V26
G7_RXD{7]
K27
P_D[15]
AG30
G6_TXD[5]
W28
G7_RX_DV
M26
P_A[0]
AF28
G6_TXD[6]
V27
G7_RX_ER
J27
P_A[1]
AE26
G6_TXD[7]
V30
LED_DO
J28
P_A[2]
AG29
G6_TX-EN
V29
LED_CLK0
J29
P_WE#
AF27
G6_RXCLK
V28
LED_SYNCO#
J30
P_RD#
AF29
G6_COL
U26
S_RST#
L26
P_CS#
AF30
G6_TX_ER
U30
RESOUT#
H28
P_INT#
AD26
G6_RXD[0]
U29
T_MODE{0}
M27
B_D[0]
AE30
G6_RXD[1]
U28
T_MODE{1]
H29
B_D[1]
AC26
G6_RXD[2]
T30
T_D[0]
H30
B_D[2]
AE29
G6_RXD[3]
T29
T_D[1]
AE28
G6_RXD[5]
AC27
G6_RXD[4]
AJ24
G5_TXD[6]
AE27
G6_RXD[6]
AG16
G3_RXD[7]
AK24
G5_TXD[7]
AB26
G6_RXD[7]
AH16
G3_RX_DV
AG25
MII_TX_CLK[5]
AD30
G6_RX_DV
AF19
G3_RX_ER
AH25
G5_TX_EN
AD29
GREF_CLK[7]
AJ16
M_MDC
AF25
G5_TX_ER
AD27
G6_RX_ER
AG18
M_MDIO
AJ25
G5_RXD[0]]
AD28
G7_TXCLK
AK16
G4_CRS/LINK
AG26
G5_RXD[1]
AC30
G7_CRS/LINK
AG17
GREF_CLK[4]
AK25
G5_RXD[2]
AA26
G7_TXD[0]
AH17
G4_TXCLK
AK26
G5_RXCLK
AC29
G7_TXD[1]
AJ17
G4_TXD[0]
P29
T_D[13]
AC28
G7_TXD[2]
AA27
G7_TXD[3]
P30
T_D[14]
E30
B_D[14]
AB30
G7_TXD[4]
P26
T_D[15]
H26
B_D[15]
AB29
G7_TXD[5]
N28
P_D[0]
E29
B_D[16]
Y26
G7_TXD[6]
N29
P_D[1]
E26
B_D[17]
AB28
G7_TXD[7]
N30
P_D[2]
D29
B_D[18]
Y27
G7_TX_EN
M28
P_D[3]
E28
B_D[19]
AB27
G7_TX_ER
M29
P_D[4]
G26
B_D[20]
AA30
MII_TX_CLK[7]
M30
P_D[5]
D30
B_D[21]
AA29
G7_RXCLK
N26
P_D[6]
C30
B_D[22]
AA29
C7_COL
L28
P_D[7]
E27
B_D[23]
Y30
G7_RXD[0]
L29
P_D[8]
C29
B_CLK
154
Zarlink Semiconductor Inc.
MVTX2804
Ball No.
Signal Name
Ball No.
Signal Name
Data Sheet
Ball No.
Signal Name
D28
B_D[24]
D19
LB_A[14]
C12
LB_D[34]
B30
B_D[25]
B21
LB_A[13]
B12
LB_D[33]
F26
NC1
C21
LB_A[12]
A12
LB_D[32]
D26
NC2
A20
LB_A[11]
C11
LB_RW#
A30
NC3
B20
LB_A[10]
E11
LB_CS1#
A29
NC4
E19
LB_A[9]
B11
LB_CS0#
B29
NC5
C20
LB_A[8]
A11
LB_D[31]
E25
AGND
A19
LB_A[7]
E10
LB_D[30]
B28
DEV_CFG[1]
B19
LB_A[6]
C10
LB_D[29]
C28
AVDD
E18
LB_A[5]
B10
LB_D[28]
A28
B_D[26]
C19
LB_A[4]
E9
LB_D[27]
A27
B_D[27]
A18
LB_A[3]
E24
B_D[31]
C27
B_D[28]
D18
LB_D[63]
D25
B_ADSC#
D27
B_D[29]
G28
B_D[3]
B26
B_WE#
B27
B_D[30]
G27
B_D[4]
A26
B_OE#
T28
T_D[2]
K26
B_D[5]
A25
B_A[2]
U27
T_D[3]
G29
B_D[6]
B25
B_A[3]
T27
T_D[4]
G30
B_D[7]
C26
B_A[4]
R27
T_D[5]
H27
B_D[8]
C25
B_A[5]
T26
T_D[6]
F27
B_D[9]
E23
B_A[6]
R28
T_D[7]
F28
B_D[10]
A24
B_A[7]
R29
T_D[8]
F29
B_D[11]
B24
B_A[8]
R30
T_D[9]
F30
B_D[12]
D23
B_A[9]
R26
T_D[10]
J26
B_D[13]
D24
B_A[10]
P27
T_D[11]
E14
LB_D[49]
C24
B_A[11]
P28
T_D[12]
C15
LB_D[48]
B7
LB_D[12]
A23
B_A[12]
B15
LB_D[47]
E8
LB_D[11]
B23
B_A[13]
E13
LB_D[46]
A7
LB_D[10]
C23
B_A[14]
A15
LB_D[45]
D6
LB_D[9]
E22
B_A[15]
D14
LB_D[44]
C6
LB_D[8]
A22
B_A[16]
C14
LB_D[43]
E6
LB_D[7]
B22
B_A[17]
D13
LB_D[42]
B6
LB_D[6]
C22
B_A[18]
B14
LB_D[41]
A6
LB_D[5]
E21
LB_A[20]
A14
LB_D[40]
A5
LB_D[4]
D22
LB_A[19]
C13
LB_D[39]
B5
LB_D[3]
D20
LB_A[18]
E12
LB_D[38]
C5
LB_D[2]
E20
LB_A[17]
B13
LB_D[37]
B4
LB_D[1]
D21
LB_A[16]
A13
LB_D[36]
D5
LB_CLK
A21
LB_A[15]
D12
LB_D[35]
A4
LB_D[0]
155
Zarlink Semiconductor Inc.
MVTX2804
Ball No.
Signal Name
Ball No.
Signal Name
Data Sheet
Ball No.
Signal Name
A3
SCAN_EN
T16
VSS
AE18
VCC
E5
AGND
T17
VSS
AE19
VCC
C4
NC6
T18
VSS
F12
VCC
B3
NC7
T25
VSS
F13
VCC
D4
NC8
T6
VSS
F14
VCC
A2
NC9
U13
VSS
F17
VCC
AD6
VSS
U14
VSS
F18
VCC
AE15
VSS
U15
VSS
F19
VCC
AE16
VSS
U16
VSS
AE25
VSS
AE24
VSS
A10
LB_D[26]
AE6
VSS
B18
LB_D[62]
D11
LB_D[25]
F15
VSS
C18
LB_D[61]
D10
LB_D[24]
F16
VSS
A17
LB_D[60]
D8
LB_D[23]
F24
VSS
E17
LB_D[59]
D9
LB_D[22]
F25
VSS
B17
LB_D[58]
C9
LB_D[21]
F6
VSS
C17
LB_D[57]
B9
LB_D[20]
F7
VSS
E16
LB_D[56]
A9
LB_D[19]
N13
VSS
D17
LB_D[55]
C8
LB_D[18]
N14
VSS
A16
S_CLK
B8
LB_D[17]
N15
VSS
B16
LB_D[54]
A8
LB_D[16]
N16
VSS
E15
LB_D[53]
C7
LB_D[15]
N17
VSS
C16
LB_D[52]
E7
LB_D[14]
N18
VSS
D16
LB_D[51]
D7
LB_D[13]
P13
VSS
D15
LB_D[50]
AE7
VDD
P14
VSS
P15
VSS
AE9
VDD
U17
VSS
P16
VSS
F10
VDD
U18
VSS
P17
VSS
F21
VDD
V13
VSS
P18
VSS
F22
VDD
V14
VSS
R13
VSS
F9
VDD
V15
VSS
R14
VSS
G25
VDD
V16
VSS
R15
VSS
G6
VDD
V17
VSS
R16
VSS
J25
VDD
V18
VSS
R17
VSS
J6
VDD
AA25
VDD
R18
VSS
K25
VDD
AA6
VDD
R25
VSS
K6
VDD
AB25
VDD
R26
VSS
AE12
VCC
AB6
VDD
T13
VSS
AE13
VCC
AD25
VDD
T14
VSS
AE14
VCC
AE10
VDD
T15
VSS
AE17
VCC
AE21
VDD
156
Zarlink Semiconductor Inc.
MVTX2804
Ball No.
Signal Name
AE22
VDD
M25
VCC
M6
VCC
N25
VCC
N6
VCC
P25
VCC
U25
VCC
U6
VCC
V6
VCC
W25
VCC
W6
VCC
157
Zarlink Semiconductor Inc.
Data Sheet
MVTX2804
12.4
12.4.1
Data Sheet
Characteristics and Timing
Absolute Maximum Ratings
Storage Temperature
-65C to +150C
Operating Temperature
-40°C to +85°C
Maximum Junction Temperature
+125°C
Supply Voltage VCC with Respect to VSS
+3.0 V to +3.6 V
Supply Voltage VDD with Respect to VSS
+2.38 V to +2.75 V
Voltage on Input Pins
-0.5 V to (VCC + 3.3 V)
Caution: Stress above those listed may damage the device. Exposure to the Absolute Maximum Ratings for
extended periods may affect device reliability. Functionality at or above these limits is not implied.
12.4.2
DC Electrical Characteristics
VCC = 3.0 V to 3.6 V (3.3v +/- 10%)TAMBIENT = -40°C to +85°C
VDD = 2.5V +10% -5%
158
Zarlink Semiconductor Inc.
MVTX2804
12.4.3
Data Sheet
Recommended Operating Conditions
Symbol
Parameter Description
Min
Type
Max
Unit
fosc
Frequency of Operation
ICC
Supply Current – @ 133 MHz (3.3 V supply)
720
930
mA
IDD
Supply Current – @ 133 MHz (2.5 V supply)
1400
1700
mA
VOH
Output High Voltage (CMOS)
VOL
Output Low Voltage (CMOS)
133
MHz
2.4
V
0.4
V
VCC + 2.0
V
VIH-TTL
Input High Voltage (TTL 5V tolerant)
VIL-TTL
Input Low Voltage (TTL 5V tolerant)
0.8
V
IIL
Input Leakage Current (0.1 V < VIN < VCC)
(all pins except those with internal
pull-up/pull-down resistors)
10
µA
IOL
Output Leakage Current (0.1 V < VOUT < VCC)
10
µA
CIN
Input Capacitance
5
pF
Output Capacitance
5
pF
I/O Capacitance
7
pF
COUT
CI/O
2.0
θja
Thermal resistance with 0 air flow
11.2
C/W
θja
Thermal resistance with 1 m/s air flow
9.9
C/W
θja
Thermal resistance with 2 m/s air flow
8.7
C/W
θjc
Thermal resistance between junction and case
3.3
C/W
159
Zarlink Semiconductor Inc.
MVTX2804
12.5
Data Sheet
AC Characteristics and Timing
12.5.1
Typical Reset & Bootstrap Timing Diagram
S_RST#
RESOUT#
Tri-Stated
R1
R3
Bootstrap Pins
Outputs
Inputs
Outputs
R2
Figure 8 - Typical Reset & Bootstrap Timing Diagram
Symbol
Parameter
Min
R1
Delay until RESOUT# is tri-stated
R2
Bootstrap stabilization
R3
RESOUT# assertion
1µs
Typ
Note:
10ns
RESOUT# state is then determined by the
external pull-up/down resistor
10µs
Bootstrap pins sampled on rising edge of
S_RST#1
2ms
Table 5 - Reset & Bootstrap Timing
1. The T_D[15:0] pins will switch over to the LED interface functionality in 3 SCLK cycles after S_RST# goes high
160
Zarlink Semiconductor Inc.
MVTX2804
12.5.2
Data Sheet
Typical CPU Timing Diagram for a CPU Write Cycle
Description
Write Cycle
(SCLK=133Mhz)
Symbol
Min (ns)
Write Set up Time
TWS
10
Write Active Time
TWA
15
Write Hold Time
TWH
2
Write Recovery time
TWR
22.5
Data Set Up time
TDS
10
Data Hold time
TDH
2
Max (ns)
At least 2 SCLK
At least 3 SCLK
Table 6 - CPU Write Cycle
P_ADDR
ADDR1
ADDR0
P_CS#
TWA
at least
2 SCLKs
TWS
P_WE#
TDH
TWA
at least
2 SCLKs
TWS
TWH
TWR
Recovery Time
TDH
DATA 0
DATA to VTX2600
TWH
DATA 1
TDS
TDS
Hold time
Set up time
Figure 9 - Typical CPU Timing Diagram for a CPU Write Cycle
161
Zarlink Semiconductor Inc.
MVTX2804
12.5.3
Data Sheet
Typical CPU Timing Diagram for a CPU Read Cycle
P_ADDR
ADDR1
ADDR0
P_CS#
TRS
P_RD#
TRA
at least
2 SCLKs
DATA to CPU
TRH
TRS
TRR
Recovery Time
at least 3 SCLKs
TRA
at least
2 SCLKs
DATA 0
TDV
TRH
DATA 1
TDI
2ns
Valid time
TDV
TDI
Inactive time
Figure 10 - Typical CPU Timing Diagram for a CPU Read Cycle
Description
Read Cycle
(SCLK=133Mhz)
Symbol
Min (ns)
Max (ns)
Read Set up Time
TRS
10
Read Active Time
TRA
15
Read Hold Time
TRH
2
Read Recovery time
TRR
22.5
Data Valid time
TDS
10
Data Inactive time
TDI
2
At least 2 SCLK
At least 3 SCLK
Table 7 - CPU Read Cycle
162
Zarlink Semiconductor Inc.
MVTX2804
12.5.4
Data Sheet
Local Frame Buffer ZBT SRAM Memory Interface
12.5.4.1
Local ZBT SRAM Memory Interface A
LA_CLK
L1
L2
LA_D[63:0]
Figure 11 - Local Memory Interface – Input setup and hold timing
LA_CLK
L3-max
L3-min
LA_D[63:0]
L4-max
L4-min
LA_A[20:3]
L6-max
L6-min
LA_CS[1,0]#
L9-max
L9-min
LA_RW#
Figure 12 - Local Memory Interface - Output valid delay timing
(SCLK= 133MHz)
Symbol
Parameter
Min (ns)
Max (ns)
Note:
L1
LA_D[63:0] input set-up time
2.5
L2
LA_D[63:0] input hold time
L3
LA_D[63:0] output valid delay
3.0
5
2CL = 25pf
L4
LA_A[20:3] output valid delay
3.0
5
3CL = 30pf
L6
LA_CS[1:0]# output valid delay
3.0
5
4CL = 30pf
L9
LA_WE# output valid delay
3.0
5
5CL = 25pf
1
1
Table 8 - AC Characteristics – Local frame buffer ZBT-SRAM Memory Interface A
163
Zarlink Semiconductor Inc.
MVTX2804
12.5.4.2
Data Sheet
Local ZBT SRAM Memory Interface B
LB_CLK
L1
L2
LB_D[63:0]
Figure 13 - Local Memory Interface – Input setup and hold timing
LB_CLK
L3-max
L3-min
LB_D[63:0]
L4-max
L4-min
LB_A[20:3]
L6-max
L6-min
LB_CS[1,0]#
L9-max
L9-min
LB_RW#
Figure 14 - Local Memory Interface - Output valid delay timing
(SCLK= 133MHz)
Symbol
Parameter
Min (ns)
Max (ns)
Note:
L1
LB_D[63:0] input set-up time
2.5
L2
LB_D[63:0] input hold time
L3
LB_D[63:0] output valid delay
3.0
5
CL = 25pf
L4
LB_A[20:3] output valid delay
3.0
5
CL = 30pf
L6
LB_CS[1:0]# output valid delay
3.0
5
CL = 30pf
L9
LB_WE# output valid delay
3.0
5
CL = 25pf
1
Table 9 - AC Characteristics – Local frame buffer ZBT-SRAM Memory Interface B
164
Zarlink Semiconductor Inc.
MVTX2804
12.5.5
Data Sheet
Local Switch Database SBRAM Memory Interface
12.5.5.1
Local SBRAM Memory Interface
B_CLK
L1
L2
B_D[31:0]
Figure 15 - Local Memory Interface – Input setup and hold timing
B_CLK
L3-max
L3-min
B_D[31:0]
L4-max
L4-min
B_A[18:2]
L6-max
L6-min
B_ADSC#
L10-max
L10-min
B_WE#
L11-max
L11-min
B_OE#
Figure 16 - Local Memory Interface - Output valid delay timing
(SCLK= 133MHz)
Symbol
Parameter
Min (ns)
Max (ns)
Note:
L1
B_D[31:0] input set-up time
2.5
L2
B_D[31:0] input hold time
L3
B_D[31:0] output valid delay
3.0
5
CL = 25pf
L4
B_A[18:2] output valid delay
3.0
5
CL = 30pf
L6
B_ADSC# output valid delay
3.0
5
CL = 30pf
L10
B_WE# output valid delay
3.0
5
CL = 25pf
L11
B_OE# output valid delay
3.0
4
CL = 25pf
1
Table 10 - AC Characteristics – Local Switch Database SBRAM Memory Interface
165
Zarlink Semiconductor Inc.
MVTX2804
12.5.6
Data Sheet
Media Independent Interface
MII_TXCLK[7:0]
M6-max
M6-min
G[7:0]_TXEN
M7-max
M7-min
G[7:0] _TXD[3:0]
Figure 17 - AC Characteristics – Media Independent Interface
G[7:0]_RXCLK
M2
G[7:0]_RXD[3:0]
M3
M4
G[7:0]_CRS_DV
M5
Figure 18 - AC Characteristics – Media Independent Interface
(MII_TXCLK &
G_RXCLK = 25MHz)
Symbol
Parameter
Min (ns)
Max (ns)
Note:
M2
G[7:0]_RXD[3:0] Input Setup Time
4
M3
G[7:0]_RXD[3:0] Input Hold Time
1
M4
G[7:0]_CRS_DV Input Setup Time
4
M5
G[7:0]_CRS_DV Input Hold Time
1
M6
G[7:0]_TXEN Output Delay Time
3
11
CL = 20 pF
M7
G[7:0]_TXD[3:0] Output Delay Time
3
11
CL = 20 pF
Table 11 - AC Characteristics – Media Independent Interface
166
Zarlink Semiconductor Inc.
MVTX2804
12.5.7
Data Sheet
Gigabit Media Independent Interface
G[7:0]_TXCLK
G12-max
G12-min
G[7:0]_TXD[7:0]
[15:0]
G13-max
G13-min
G[7:0]_TX_EN
G14-max
G14-min
G[7:0]_TX_ER
Figure 19 - AC Characteristics - GMII
G[7:0]_RXCLK
G1
G2
G[7:0]_RXD[7:0]
G3
G4
G[7:0}_RX_DV
G5
G6
G[7:0]_RX_ER
G7
G8
G[7:0]_RX_CRS
Figure 20 - AC Characteristics – Gigabit Media Independent Interface
(G_RCLK &
G_REFCLK = 125MHz)
Symbol
Min (ns)
Parameter
G1
G[7:0]_RXD[7:0] Input Setup Times
2
G2
G[7:0]_RXD[7:0] Input Hold Times
1
G3
G[7:0]_RX_DV Input Setup Times
2
G4
G[7:0]_RX_DV Input Hold Times
1
G5
G[7:0]_RX_ER Input Setup Times
2
G6
G[7:0]_RX_ER Input Hold Times
1
G7
G[7:0]_CRS Input Setup Times
2
G8
G[7:0]_CRS Input Hold Times
1
Max (ns)
Table 12 - AC Characteristics – Gigabit Media Independent Interface
167
Zarlink Semiconductor Inc.
Note:
MVTX2804
Data Sheet
(G_RCLK &
G_REFCLK = 125MHz)
Symbol
Parameter
Min (ns)
Max (ns)
Note:
1.5
5
CL = 20pf
G12
G[7:0]_TXD[7:0] Output Delay Times
G13
G[7:0]_TX_EN Output Delay Times
2
5
CL = 20pf
G14
G[7:0]_TX_ER Output Delay Times
1
5
CL = 20pf
Table 12 - AC Characteristics – Gigabit Media Independent Interface (continued)
12.5.8
PCS Interface
G[7:0]_TXCLK
G30-max
G30-min
G[7:0]_TXD[9:0]
[15:0]
Figure 21 - AC Characteristics – PCS Interface
Figure 22 - AC Characteristics – PCS Interface
(G_RCLK &
G_REFCLK =
125MHz)
Symbol
Min (ns)
Parameter
G21
G[7:0]_RXD[9:0] Input Setup Times ref to G_RXCLK
2
G22
G[7:0]_RXD[9:0] Input Hold Times ref to G_RXCLK
1
Table 13 - AC Characteristics – PCS Interface
168
Zarlink Semiconductor Inc.
Max (ns)
Note:
MVTX2804
Data Sheet
(G_RCLK &
G_REFCLK =
125MHz)
Symbol
Parameter
Min (ns)
G23
G[7:0]_RXD[9:0] Input Setup Times ref to G_RXCLK1
2
G24
G[7:0]_RXD[9:0] Input Hold Times ref to G_RXCLK1
1
G25
G[7:0]_CRS Input Setup Times
2
G26
G[7:0]_CRS Input Hold Times
1
G30
G[7:0]_TXD[9:0] Output Delay Times
1
Max (ns)
5
Note:
CL = 20pf
Table 13 - AC Characteristics – PCS Interface (continued)
12.5.9
LED Interface
LED_CLK
LE5-max
LE5-min
LED_SYN
LE6-max
LE6-min
LED_BIT
Figure 23 - AC Characteristics – LED Interface
Variable FREQ.
Symbol
Parameter
Min (ns)
Max (ns)
Note:
LE5
LED_SYN Output Valid Delay
1
7
CL = 30pf
LE6
LED_BIT Output Valid Delay
1
7
CL = 30pf
Table 14 - AC Characteristics – LED Interface
169
Zarlink Semiconductor Inc.
MVTX2804
12.5.10
Data Sheet
MDIO Input Setup and Hold Timing
MDC
D1
D2
MDIO
Figure 24 - MDIO Input Setup and Hold Timing
MDC
D3-max
D3-min
MDIO
Figure 25 - MDIO Output Delay Timing
1MHz
Symbol
Parameter
Min (ns)
D1
MDIO input setup time
10
D2
MDIO input hold time
2
D3
MDIO output delay time
1
Table 15 - MDIO Timing
170
Zarlink Semiconductor Inc.
Max (ns)
20
Note:
CL = 50pf
MVTX2804
12.5.11
Data Sheet
I2C Input Setup Timing
SCL
S1
S2
SDA
Figure 26 - I2C Input Setup Timing
SCL
S3-max
S3-min
SDA
Figure 27 - I2C Output Delay Timing
500KHz
Symbol
Parameter
Min (ns)
S1
SDA input setup time
20
S2
SDA input hold time
1
S3*
SDA output delay time
1
Max (ns)
20
* Open Drain Output. Low to High transistor is controlled by external pullup resistor.
Table 16 - I2C Timing
171
Zarlink Semiconductor Inc.
Note:
CL = 30pf
MVTX2804
12.5.12
Data Sheet
Serial Interface Setup Timing
STROBE
D4
D5
D1
D1
D2
PS_DI
D2
Figure 28 - Serial Interface Setup Timing
STROBE
D3-max
D3-min
PS_DO
Figure 29 - Serial Interface Output Delay Timing
(SCLK =133 MHz)
Symbol
Parameter
Min (ns)
D1
PS_DI setup time
20
D2
PS_DI hold time
10
D3
PS_DO output delay time
1
D4
Strobe low time
5µ s
D5
Strobe high time
5µs
Table 17 - Serial Interface Timing
172
Zarlink Semiconductor Inc.
Max (ns)
50
Note:
CL = 100pf
E1
MIN
MAX
A
2.20
2.46
A1
0.50
0.70
A2
1.17 REF
40.20
D
39.80
D1
34.50 REF
E
40.20
39.80
E1
34.50 REF
b
0.60
0.90
e
1.27
596
Conforms to JEDEC MS - 034
E
e
D
D1
A2
NOTE:
b
A1 A
1. CONTROLLING DIMENSIONS ARE IN MM
2. DIMENSION "b" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER
3. SEATING PLANE IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS.
4. N IS THE NUMBER OF SOLDER BALLS
5. NOT TO SCALE.
6. SUBSTRATE THICKNESS IS 0.56 MM
Package Code
ISSUE
ACN
DATE
APPRD.
Previous package codes:
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