SP5768 SP5768 3.0 GHz Low Phase Noise Frequency Synthesiser November 2004 Features • • Ordering Information • Complete 3.0GHz single chip system Optimised for low phase noise, with comparison frequencies up to 4 MHz No RF prescaler • Selectable reference division ratio • Reference frequency output • Selectable charge pump current • Integrated loop amplifier • Four switching ports • Low power replacement for SP5658 and 5668 • Downwards software compatible with SP5658 • ESD protection, (Normal ESD handling procedures should be observed) SP5768/KG/MP1S (Tubes) SP5768/KG/MP1T (Tape and Reel) Description The SP5768 is a single chip frequency synthesiser designed for tuning systems up to 3.0GHz and is optimized for low phase noise with comparison frequencies up to 4 MHz. The RF programmable divider contains a front end dual modulus 16/17 functioning over the full operating range and allows for coarse tuning in the upconverter application and fine tuning in the downconverter. Comparison frequencies are obtained either from a crystal controlled on-chip oscillator or from an external source. A buffered reference frequency output is also available to drive a second SP5768. Applications • TV, VCR and Cable tuning systems • Communications systems The device also contains 4 switching ports. REF 13 BIT COUNT RF INPUT CRYSTAL CAP REFERENCE DIVIDER CRYSTAL 16/17 4 BIT COUNT CHARGE PUMP DRIVE 17 BIT LATCH DATA CLOCK DATA INTERFACE 6 BIT LATCH 5 BIT LATCH & PORT/ TEST MODE INTERFACE ENABLE PORT P0/OP PORT P1/OC PORT P2 PORT P3 Figure 1 - SP5768 block diagram Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2001-2004, Zarlink Semiconductor Inc. All Rights Reserved. 1 SP5768 16 SPOT REF. CHARGE PUMP CRYSTAL CAP CRYSTAL ENABLE DATA CLOCK PORT P1/OC PORT P2 DRIVE V EE RF INPUT RF INPUT V CC REF PORT P0/OP PORT P3 MP16 QP16 Figure 2 - Pin Connections Diagram Electrical Characteristics These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. TAMB = -40°C to 80°C, VCC = +4·5V to +5·5V Characteristic Pin Value Min Supply current 2 12 Units Typ Max 18 25 mA MHz Conditions RF input frequency range 13,14 100 3000 RF input voltage 13,14 100 300 mV rms 100 - 200MHz 13, 14 30 300 mVrms RF input impedance 13,14 Data, clock & enable input high voltage input low voltage input current hysterysis Clock rate 5,6,4 Bus timing data set up data hold enable set up enable hold clock to enable 5,6,4 See Figure 6 See Figure 3 3 0 -10 Vcc 0.7 10 6 V V µA V 500 300 600 300 600 300 ns ns ns ns ns 0.8 All input conditions kHz SP5768 Electrical Characteristics (continued) These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. Tamb = -40°C to 80°C, Vcc = +4·5V to +5·5V Characteristic Pin Min Value Typ Units Conditions Max Charge pump output current 1 See Table 1 Vpin1 = 2V Charge pump output leakage 1 Charge pump drive output current 16 0.5 Crystal frequency 2,3 2 20 MHz See Figure 5 for application External reference input frequency 3 2 20 MHz Sinewave coupled through 10F blocking capacitor External reference drive level 3 0.2 0.5 Vpp Sinewave coupled through 10nF blocking capacitor Buffered reference 11 ±3 ±10 0.35 250 4 Equivalent phase noise at phase detector -148 RF division ratio 240 131071 2 320 Output ports P0-P3 sink current leakage current 1 2 Vpin1=2V, Vcc = +5.0V, Tamb = 25°C mA Vpin 16=0.7V AC coupled, See note 1 frequency output output amplitude output impedance Comparison frequency Reference division ratio nA Vpp Ω MHz dBc/Hz 10 At 10 kHz, SSB, with 2 MHz comparison from 4 MHz crystal reference See Table 2 7,8,9,10 2 2-20MHz mA See Note 2 Vport = 0.7V µA Vport = Vcc Reference output disabled by connecting to Vcc if not required Output ports high impedance on power up, with data, clock and enable at logic 0 3 SP5768 Absolute Maximum Ratings All voltages are referred to Vee at 0V Characteristic Pin Min Supply voltage, Vcc 12 -0.3 Typ Max Units 7 V 2.5 RF input voltage 13,14 RF input DC offset 13,14 -0.3 V cc+0.3 Vp-p V 7,8,9,10 -0.3 V cc+0.3 V Charge pump DC offset 1 -0.3 V cc+0.3 V Varactor drive DC offset 16 -0.3 V cc+0.3 V Crystal DC offset 2,3 -0.3 V cc+0.3 V Buffered ref output 11 -0.3 V cc+0.3 V 5,6,4 -0.3 V cc+0.3 V -55 +125 °C +150 °C 80 20 °C/W °C/W 138 mW Port voltage Data, clock & enable DC offset Storage temperature Junction temperature MP16 thermal resistance, chip to ambient chip to case Power consumption at Vcc=5.5V ESD protection 2 kV Conditions Differential All ports off Mil-std 883B latest revision method 3015 cat.1. Functional description The SP5768 contains all the elements necessary, with the exception of a frequency reference, loop filter and external high voltage transistor, to control a varicap tuned local oscillator, so forming a complete PLL frequency synthesised source. The device allows for operation with a high comparison frequency and is fabricated in high speed logic, which enables the generation of a loop with excellent phase noise performance, even with high comparison frequencies. The package and pin allocation is shown in Figure 1 and the block diagram in Figure 2. The SP5768 is controlled by a standard 3-wire bus comprising data, clock and enable inputs. The programming word contains 28 bits, four of which are used for port selection, 17 to set the programmable divider ratio, four bits to select the reference division ratio, bits RD & R0-R2, see Table 2, two bits to set charge pump current, bit C0 and C1, see Table 1, and the remaining bit to access test modes, bit T0, see Table 3. The programming format is shown in Figure 4. The clock input is disabled by an enable low signal, data is therefore only loaded into the internal shift registers during an enable high and is clocked into the controlling buffers by an enable high to low transition. This load is also synchronised with the programmable divider so giving smooth fine tuning. 4 The RF signal is fed to an internal preamplifier, which provides gain and reverse isolation from the divider signals. The output of the preamplifier is fed to the 17 bit fully programmable counter, which is of MN+A architecture. The M counter is 13 bit and the A counter 4 The output of the programmable counter is fed to the phase comparator where it is compared in both phase and frequency domain with the comparison frequency. This frequency is derived either from the on board crystal controlled oscillator or from an external reference source. In both cases the reference frequency is divided down to the comparison frequency by the reference divider which is programmable into1 of 16 ratios as descried in Table 2. The output of the phase detector feeds the charge pump and loop amplifier section, which when used with an external high voltage transistor and loop filter integrates the current pulses into the varactor line voltage. The charge pump current setting is described in Table 1, A buffered crystal reference frequency suitable for driving further synthesisers is available from Pin 11. If not required this output can be disabled by connecting to Vcc The programmable divider output divided by 2, Fpd/2 and comparison frequency, Fcomp can be switched to ports P0 and P1 respectively by switching the device into test mode. The test modes are described in Table 3. SP5768 +j1 +j2 +j0.5 +j0.2 +j5 0 1 2 -j0.2 S11 : Zo = 50Ω 4 Normalised to 50Ω -j0.5 -j5 3 Frequency Markers at 500MHz, 1GHz, 1.5GHz and 2.4GHz -j2 -j1 Figure 3 - RF input impedance CLOCK ENABLE DATA 227 226 225 224 223 222 P3 P2 P1 P0 T0 C1 221 220 C0 R2 219 R1 218 217 R0 RD 216 20 MSB LSB Frequency data 2^16 to 2^0 : Programmable divider ratio control bits R2,R1,R0 : Reference divider control bits RD : Reference divider mode select P3, P2, P1,P0 : Port control bits C1,C0 : Charge pump current select T0 : Test mode enable Figure 4 - Data format Current (in µA) C1 C0 0 0 230 0 1 1000 1 0 115 1 1 500 Table 1 - Charge pump current 5 SP5768 2 18pF 39pF SP5768 3 Figure 5 - Crystal oscillator application RD 0 0 0 0 0 0 0 0 R2 0 0 0 0 1 1 1 1 R1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 RATIO 2 4 8 16 32 64 128 256 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 3 5 10 20 40 80 160 320 Table 2 - Reference division ratio P1 X 0 0 1 1 P0 X 0 1 0 1 T0 0 1 1 1 1 FUNCTIONAL DESCRIPTION Normal operation Charge pump sink Charge pump source Charge pump disable Port P1 = Fcomp, P0 = Fpd/2 X = don't care Table 3 - Test modes 6 SP5768 300 VIN (mV RMS INTO 50Ω) OPERATING WINDOW 100 30 10 100 200 3000 1000 FREQUENCY (MHz) Figure 6 - Typical input sensitivity 1.6GHz 50 - 900MHz 38.9MHz 1650-2700MHz 1650 -2400MHz 2 SP5768 SP5748 SP5768 SP5748 3 3 VCO VCO 10 11 10nF Figure 7 - Example of double conversion from VHF/UHF frequencies to TV IF 18pF +30V 2 39pF 68pF 3 2n2 +5V 22k 4MHz 1k 13k3 BCW31 Optional application utilising on–board crystal controlled oscillator ENABLE DATA 2 15 3 14 4 5 CLOCK SP5768 CONTROL MICRO OR 4n7 16 1 REFERENCE +12V TUNER 1n 1n OSCILLATOR OUTPUT 13 12 10n 6 11 P1 7 10 P0 P2 8 9 P3 Figure 8 - Typical application SP5768 7 SP5768 Application Notes Loop Bandwidth A generic set of application notes AN168 for designing withsynthesisers such as the SP5768 has been written. This covers aspects such as loop filter design and decoupling. This application note is also featured in the Media Data Book, or refer to the Zarlink Semiconductor Internet Site http://www.zarlink.com. The majority of applications for which the SP5768 is intended require a loop filter bandwidth of between 2kHz and10kHz. Typically the VCO phase noise will be specified at both 1kHz and10kHz offset. It is common practice to arrange the loop filter bandwidth such that the 1kHz figure lies within the loop bandwidth. Thus the phase noise depends on the synthesiser comparator noise floor, rather than the VCO. Reference Source The SP5768 offers optimal LO phase noise performance when operated with a large step size. This is due to the fact that the LO phase noise within the loop bandwidth is: phase comparator LO frequency noise floor + 20 log 10 phase comparator frequency ( Assuming the phase comparator noise floor is flat irrespective of sampling frequency, this means that the best performance will be achieved when the overall LO to phase comparator division ratio is a minimum. There are two ways of achieving a higher phase comparator sampling frequency:– A) Reduce the division ratio between the reference source and the phase comparator B) use a higher reference source frequency. Approach B) may be preferred for best performance since it is possible that the noise floor of the reference oscillator may degrade the phase comparator performance if the reference division ratio is very small. 8 ) The 10kHz offset figure should depend on the VCO providing the loop is designed correctly, and is not underdamped. SP5768 VREF 500 VCC 500 CHARGE PUMP RF INPUTS 200 DRIVE Loop amplifier RF inputs PORT VCC 25K BIAS INPUT Disable, Enable, Data and Clock inputs Output Ports VCC VCC CRYSTAL REF 1.2mA CRYSTAL CAP Reference oscillator Reference output Figure 9 - Input/Output interface circuits 9 For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. 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