ZXFV401 SYNC SEPARATOR WITH VARIABLE FILTER DEVICE DESCRIPTION FEATURES AND BENEFITS The ZXFV401 provides the ability to separate out video synchronisation signals for a wide variety of TV and CRT display systems, standard and non-standard. • PAL, NTSC, SECAM, other TV systems • Super accurate synch slice • Variable filter for outputs: composite, horizontal, Vertical, back porch, odd / even Flexibility arises from the use of just three external resistors to adapt to each application. One resistor controls a fully integrated internal colour carrier filter with variable bandwidth. This filter aviods disturbance from the colour carrier, permitting accurate threshold slicing for timing extraction. • No-signal detector • On chip sample / hold capacitors • +5V single supply • 4.5 mA supply current • Default vertical output where there are no A second resistor controls the voltage threshold for loss of signal detection after a time-out interval. The third resistor controls the timing functions. serration pulses • Pin compatible with industry standard part SO16N surface mount package DC restoration for displays is facilitated by the Back Porch synch output, which can be used to drive an external curcuit to clamp the blanking voltage to a fixed level. APPLICATIONS • Digital image capture • Video input systems requiring separation of ORDERING INFORMATION Part Number Container ZXFV401N16TA Reel 7″ ZXFV401N16TC Reel 13″ picture timing Increment • Video distribution 500 • CCTV surveillance 2500 • Digital multimedia • Timing for black level clamp CONNECTION DIAGRAM +5V COMPOSITE SYNC ZXFV401N16 RFILT RNOSIG VIDEO INPUT 1 RFILT 2 RNOSIG 3 CSYNC 4 FILTIN 5 VSYNC 6 0VD 7 FILTOUT 8 FVIDIN 0VA 16 HSYNC 15 V+ 14 ODDFLD 13 RSET 12 BKPCH 11 BACK PORCH NOSIG 10 NO SIGNAL VLEV 9 SYNC TIP VOLTAGE HORIZONTAL SYNC C1 ODD FIELD RSET 0.1uF 75R C2 0.1uF VERTICAL SYNC PROVISIONAL ISSUE A - FEBRUARY 2002 1 ZXFV401 ABSOLUTE MAXIMUM RATINGS Supply voltage VCC Inputs to ground* -0.5V to +7V -0.5V to VCC +0.5V Operating Temperature Range -40⬚C to 85⬚C Storage -65⬚C to +150⬚C Operating Ambient Junction temperature TJMAX150⬚C** **The thermal resistance from the semiconductor die to ambient is typically 120⬚C/W when the SO16 package is mounted on a PCB in free air. The power dissipation of the device when loaded must be designed to keep the device junction temperature below TJMAX. *During power-up and power-down, these voltage ratings require that signals be applied only when the power supply is connected. ELECTRICAL CHARACTERISTICS VCC = 4.75 TO 5.25, RSET = 681k, RFILT = 22k, RNOSIG = 82k, Tamb = 25⬚C unless otherwise stated. PARAMETER CONDITIONS TEST MIN TYP 1.3 1.35 MAX UNIT DC Characteristics Supply current P 4.5 mA Clamp voltage Pin 4 unloaded P 1.8 Discharge current at FILTIN Pin 4, Vin = 2V pk-pk C Discharge current at FILTIN Pin 4, no signal P 3 6 12 A Clamp charge current at FILTIN Pin 4, Vin = 1V pk-pk P 2 3 4 mA Clamp voltage at FVIDIN Pin 8 unloaded P 1.3 1.35 1.8 Discharge current at FVIDIN Pin 8, Vin = 2V pk-pk C Discharge current at FVIDIN Pin 8, no signal P Clamp charge current at FVIDIN Pin 8, Vin = 1V pk-pk 6 V 〈 1 3 V A 1 12 〈 P 2 3 4 mA R SET voltage, pin 12 P 1.5 1.75 2 V R FILT voltage, pin 1 P 0.35 0.5 0.65 V P 1.5 2.5 3.5 A 0.35 0.8 RNOSIG current, pin 2 Logic output Low voltage, V OL I OL = 1.6mA P Logic output High voltage, V OH I OH = 1.6mA P 2.4 4 V V TEST - P = production tested, C = characterised PROVISIONAL ISSUE A - FEBRUARY 2002 2 ZXFV401 ELECTRICAL CHARACTERISTICS (CONT) VCC = 4.75 TO 5.25, RSET = 681k, RFILT = 22k, Tamb = 25 C unless otherwise stated. PARAMETER CONDITIONS TEST MIN TYP MAX UNIT AC Characteristics FILTIN function input voltage range PAL/NTSC P Filter voltage gain FILTIN to FILOUT P 6 dB Filter attenuation 4.4MHz for PAL, C 12 dB 3.6MHz for NTSC Slice level Vin = 1V pk-pk P CSYNC prop. Delay, t CS Relative to pin 4 input 0.4 40 2 50 P 250 VSYNC delay P 250 VSYNC pulse width, t VSYNC (PAL) P VSYNC pulse width, t VSYNC (NTSC) P VSYNC default delay, t VSD P HSYNC delay P HSYNC pulse width, t HSYNC P BKPCH delay, t BD BKPCH pulse width, t B VLEV output Relative to pin 4 input Input 1 Vpk-pk, pin 4 NOSIG time-out delay after loss of signal PROVISIONAL ISSUE A - FEBRUARY 2002 3 % 400 ns ns s s 195 45 s 5 6.2 s 36 250 3.8 P ns 250 400 ns P 2.7 3.7 4.7 s P 500 600 700 mV P TEST - P = production tested, C = characterised 60 165 27 V pk-pk 600 s ZXFV401 CONNECTIONS PIN No. PIN NAME TYPE FUNCTION 1 RFILT Resistor control Controls the input colour carrier filter characteristic. An external resistor R FILT connected from this pin to 0V sets the bandwidth. Smaller R FILT gives increased bandwidth. See the detailed operating description below. 2 RNOSIG Resistor control Controls the no-signal detector level. An external resistor R NOSIG connected from this pin to 0V sets the threshold voltage level, according to the equation V PMIN = 0.75 R NOSIG / R SET where V PMIN is the minimum detected sync pulse amplitude at pin 4 and R SET is the resistor value at pin 12. Composite sync logic output. Includes all sync pulses derived from the input video. Input to colour carrier filter. This is the main analog (unfiltered) Analog in composite video input used when colour carrier filtering is required. A voltage clamp circuit and adaptive current source are also included at this node. See the detailed operating description. Vertical sync output. This is an active low pulse commencing on the first Logic out vertical sync pulse trailing (rising) edge and ending near the second next equalising pulse. See timing diagram. 3 CSYNC Logic out 4 FILTIN 5 VAYNC 6 OVD 7 FILTOUT Analog out Analog output signal from colour carrier filter. The filter voltage gain is nominally 2. This output is normally capacitor-coupled to pin 8. 8 FVIDIN Input for filtered analog video signal input. This is the direct input to the sample/hold and sync slicing comparator providing the logic timing Analog in edges. This input is normally coupled via an external capacitor from FILTOUT, pin 7. It may be used as the signal input where the colour carrier filter is not required. Includes a clamp similar that of pin 4. 9 VLEV Analog out Analog output, a positive voltage typically equal to twice the (negative) peak sync pulse amplitude if the filter is used. 10 NOSIG Ground Logic out 11 BKPCH Logic out 12 RSET Resistor control 13 ODDFLD Logic out 14 V+ Power in 15 HSYNC Logic out 16 OVA Ground Provides ground return path for internal logic output buffer circuits. Normally connected externally to a common PCB ground plane. Logic output, which goes high after a time-out delay when no signal is present. The threshold level is controlled at pin 2. Burst or Back Porch logic output, an active low monostable pulse triggered from rising composite sync pulse edges. The width is set by R SET to overlap most of the steady part of the back porch, assuming the colour carrier burst has been attenuated sufficiently by filtering. This pulse is then suitable for controlling an external black level clamping circuit. See the timing diagram. Controls the timing interval of the sample/hold circuit and the monostable interval for the sync outputs according to the application. An external resistor, R SET connected from this pin to 0V establishes the timing parameter, to which these times are scaled together. See the detailed operating description. Odd field logic output. High during an odd numbered field, low during even. This output is timed with the start of the VSYNC pulse. Power supply input, +5V. Horizontal sync logic output. Monostable output derived from CSYNC falling edges, it achieves a steady stream of 5µs pulses. The half line events during the field blanking interval are eliminated. See timing diagram. Analog ground. Normally connected externally to a common PCB ground plane. PROVISIONAL ISSUE A - FEBRUARY 2002 4 ZXFV401 DETAIL DESCRIPTION The vertical sync output VSYNC is derived from the Field pulse group. Where there are short equalisation pulses in the standard systems, these short pulses are ignored. Essentially, a pulse width discriminator circuit senses the first of the Field pulses, as they are wider than those of the rest of the sequence. The trailing edge of the first negative-going Frame Pulse (i.e. the rising edge of the first “serration” pulse) triggers the VSYNC output. In systems with a frame interval with no serration pulses, a vertical sync output is provided after a default delay as in Figure 4. Also provided is an ODDFLD logic output, which is high during an odd-numbered field and low during an even one. Introduction This device includes all the functions required to separate out the critical timing points of most types of video signal. A sample-and-hold process is used to establish accurately the 50% point of the sync pulse. The input is also filtered to avoid the effect of the colour carrier. The filter is coupled externally. The following paragraphs give a simplified description of the signal processing. Colour Carrier Filter This is a low-pass filter providing adjustable attenuation of the colour carrier with low distortion of the remaining sync pulses so as to ensure accurate timing of the extracted logic outputs. The control is via an external resistor RFILT connected from pin 1 to ground. A graph shows how the bandwidth varies with the resistor value (Graph to be provide in future issue). The horizontal sync HSYNC is a monostable output derived from the leading edge of the composite sync. The pulse width is about 5 µs. Also, during the Field blanking sequence, the additional half-line pulses are removed by a timing circuit with a pulse interval discrimination function controlled by RSET. Clamping Circuits Clamping circuits are use to limit the signal swing excursion after AC coupling at both the input to the filter, FILTIN and the timing extractor input, FVIDIN. In each case, the sync tip level is maintained at a value of nominally 1.35V. The Back Porch monostable output BKPCH is initiated from the trailing edge of the composite.sync. The pulse is active low and the width is set according to RSET. Sync Timing Extraction Circuits Loss-of-Signal Detector The waveforms are depicted in Timing Diagrams, Figure 1 for PAL (625 lines) and Figure 2 for NTSC (525 lines). Sample-and-hold circuits are used to obtain time-delayed voltage values of the sync tip and the back porch. The sample gates are controlled by a comparator sensing the video input relative to a threshold at a fixed offset above the sync tip clamp level. The sampled voltages are combined in a potential divider to derive the mean voltage (50% amplitude), which is used as the sync pulse threshold. A second comparator then provides CSYNC, the logic version of the composite sync signal. This is delayed slightly as shown in Figure 3. The time delay comprises that of the input filter and also the smaller delay of the comparator and logic. The timing of the sample hold and other time parameters are all controlled together in unison by the external resistor RSET. A 1% resistor tolerance is recommended. The sync tip voltage level from the sample-and-hold is buffered and provided as an analog output, VLEV. Loss of signal is indicated by a logic high level at the output NOSIG. The decision threshold is set by an external resistor RNOSIG connected from pin 2 to ground. The table of connections above gives the equation used to determine a suitable resistor value. A waiting time of nominally 600 µs occurs before the loss of signal is flagged. PROVISIONAL ISSUE A - FEBRUARY 2002 5 ZXFV401 FRAME 1 FIELD BLANKING VIDEO INPUT 621 620 622 623 624 625 1 2 3 4 5 6 7 23 8 CSYNC OUTPUT VSYNC OUTPUT HSYNC OUTPUT BACK PORCH OUTPUT, BKPCH SEE FIGURE 3 FOR DETAIL Figure 1: PAL 625 TIMING DIAGRAM VIDEO INPUT 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 CSYNC OUTPUT VSYNC OUTPUT HSYNC OUTPUT BACK PORCH OUTPUT, BKPCH Figure 2: NTSC TIMING DIAGRAM PROVISIONAL ISSUE A - FEBRUARY 2002 6 ZXFV401 FVIDIN VIDEO INPUT 50% tCS CSYNC OUTPUT tBD BKPCH OUTPUT tB Figure 3: SYNC SLICING & OUTPUT DETAIL Line period FVIDIN VIDEO INPUT tVSD VSYNC OUTPUT Figure 4: VERTICAL SYNC DEFAULT PROVISIONAL ISSUE A - FEBRUARY 2002 7 ZXFV401 PACKAGE DIMENSIONS Millimetres Inches DIM A MIN MAX MIN MAX 4.80 4.98 0.189 0.196 B 0.635 0.025 NOM C 0.23 REF 0.009 REF D 0.20 0.30 0.008 0.012 E 3.81 3.99 0.15 0.157 F 1.35 1.75 0.053 0.069 G 0.10 0.25 0.004 0.01 J 5.79 6.20 0.228 0.244 K 0° 8° 0° 8° © Zetex plc 2001 Zetex plc Fields New Road Chadderton Oldham, OL9 8NP United Kingdom Telephone (44) 161 622 4422 Fax: (44) 161 622 4420 Zetex GmbH Streitfeldstraße 19 D-81673 München Zetex Inc 700 Veterans Memorial Hwy Hauppauge, NY11788 Germany Telefon: (49) 89 45 49 49 0 Fax: (49) 89 45 49 49 49 USA Telephone: (631) 360 2222 Fax: (631) 360 8222 Zetex (Asia) Ltd 3701-04 Metroplaza, Tower 1 Hing Fong Road Kwai Fong Hong Kong Telephone: (852) 26100 611 Fax: (852) 24250 494 These offices are supported by agents and distributors in major countries world-wide. This publication is issued to provide outline information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose or form part of any order or contract or be regarded as a representation relating to the products or services concerned. The Company reserves the right to alter without notice the specification, design, price or conditions of supply of any product or service. For the latest product information, log on to www.zetex.com PROVISIONAL ISSUE A - FEBRUARY 2002 8