CUSTOMER PROCUREMENT SPECIFICATION Z86127 LOW-COST DIGITAL TELEVISION CONTROLLER (LDTC) GENERAL DESCRIPTION The Z86127 Low-Cost Digital Television Controller (LDTC) introduces a new level of sophistication to single-chip architecture. The Z86127 is a member of the Z8® singlechip microcontroller family with 8 Kbytes of ROM and 236 bytes of RAM. The device is housed in a 64-pin DIP package, in which only 52 are active, and are CMOS compatible. The LDTC offers mask programmed ROM which enables the Z8 microcontroller to be used in a high volume production application device embedded with a custom program (customer supplied program). Zilog’s LDTC offers fast execution, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, and easy hardware/software system expansion along with low cost and low power consumption. The device provides an ideal performance and reliability solution for consumer and industrial television applications. The Z86127 architecture is characterized by utilizing Zilog’s advanced Superintegration™ design methodology. The device has an 8-bit internal data path controlled by a Z8 microcontroller and On Screen Display (OSD) logic circuits/ Pulse Width Modulators (PWM). On-chip peripherals include two register mapped I/O ports (Ports 2 and Port 3), interrupt control logic (one software, two external and three internal interrupts) and a standby mode recovery input port (Port 3, pin P30). The OSD control circuits support 8 rows by 20 columns of characters. The character color is specified by row. One of the eight rows is assigned to show two kinds of colors for bar type displays such as volume control. The OSD is capable of displaying either low resolution (5x7 dot pattern) or high resolution (11x15 dot pattern) characters. The Z86C97 currently supports high resolution characters only. DC-4063-00 (10-16-91) A 14-bit PWM port provides enough voltage resolution for a voltage synthesizer tuning system. Three 6-bit PWM ports are used for controlling audio signal levels. Five 8-bit PWM ports are used to vary picture levels. The LDTC applications demand powerful I/O capabilities. The Z86127 fulfills this with 27 I/O pins dedicated to input and output. These lines are grouped into four ports, and are configurable under software control to provide timing, status signals, parallel I/O and an address/data bus for interfacing to external memory. There are three basic address spaces available to support this wide range of configurations: Program Memory, Video RAM, and Register File. The Register File is composed of 236 bytes of general purpose registers, two I/O Port registers, 15 control and status registers and three reserved registers. To unburden the program from coping with the real-time problems such as counting/timing and data communication, the LDTC offers two on-chip counter/timers with a large number of user selectable modes (Functional Block Diagram). Notes: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Circuit Device Power Ground VCC GND VSS VDD 1 GENERAL DESCRIPTION (Continued) XTAL1 XTAL2 /RESET RESET Oscillator WDT Counter Timer Counter Timer P30 P31 P34 P35 P36 P50( P00 ) P51( P01 ) P52( P02 ) P53( P03 ) P54( P04 ) P55( P05 ) P56( P06 ) P57( P07 ) P60( /AS ) P61( /DS ) P62( R//W ) P63( SCLK ) P64( P66 )* P65( P67 )* AFCIN 8 KByte Program ROM Port 2 Z8 CPU Core Port 3/ Interrupt PWM 1 14 -bit 256 Byte Register File Port 5 (Port 0) Port 0 PWM 6 to PWM 8 6-bit Port 1 A8:15 AD0:7 PWM 9 to PWM 13 8-bit Port 6 (Control) 160 Byte Character RAM 4 KByte Character ROM Functional Block Diagram 2 P27 P26 P25 P24 P23 P22 P21 P20 On Screen Display PWM 1 PWM 6 PWM 7 PWM 8 PWM 9 PWM 10 PWM 11 PWM 12 PWM 13 OSCIN OSCOUT HSYNC VSYNC VRED VGREEN VBLUE VBLANK PIN CONFIGURATION N/C 1 64 PWM6 N/C 2 3 63 62 PWM7 PWM8 4 61 PWM9 5 6 60 59 PWM10 PWM11 P36 P34 7 8 58 57 PWM12 PWM13 P31 9 56 P27 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 P26 P25 P24 P23 N/C N/C PWM1 P35 P30 XTAL1 XTAL2 /RESET P60 GND P61 P62 VCC P63 P64 P65 AFCIN P50 P51 P52 P53 P54 P55 P56 P57 OSCIN OSCOUT 32 Z86127 (LDTC) GND P22 P21 VCC P20 38 37 36 35 34 N/C N/C N/C N/C N/C N/C N/C N/C VBLANK VBLUE VGREEN VRED VSYNC 33 HSYNC 64-Pin Mask-ROM Plastic DIP 3 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Symbol Parameters Min Max Units Notes VCC VI VI VO IOH Power Supply Voltage* Input Voltage Input Voltage Output Voltage Output Current High -0.3 -0.3 -0.3 -0.3 +7 VCC+0.3 VCC+0.3 VCC+8.0 -10 V V V V mA [1] [2] 1 pin IOH IOL IOL IOL TA TSTG Output Current High Output Current Low Output Current Low Output Current Low Operating Temperature Storage Temperature -100 20 40 200 mA mA mA mA All total 1 pin [3] (1 pin) All total +150 C † -65 Notes: [1] Port 2 open drain [2] PWM open-drain outputs [3] Port 5 * Voltage on all pins with respect to GND. † See Ordering Information STANDARD TEST CONDITIONS VDD The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Test Load Diagram). RLL From Output Under Test 150 pF Test Load Diagram CAPACITANCE TA=25°C; VCC=GND=0V; Freq=1.0 MHz; unmeasured pins to GND. Parameter Input capacitance Output capacitance I/O capacitance AFCIN input capacitance 4 Max Units 10 20 25 10 pF pF pF pF RLH DC CHARACTERISTICS TA=0°C to +70°C; VCC=+4.5V to +5.5V; FOSC=4 MHz Sym Parameter TA=0°C to +70°C Min Max VIL VILC VIH Input Voltage Low Input XTAL/Osc In Low Input Voltage XTAL/Osc In High VIHC VHY VPU Input XTAL/Osc in High Schmitt Hysteresis Maximum Pull-up Voltage VOL Output Voltage Low V00-01 V01-11 VOH AFC Level 01 In AFC Level 11 In Output Voltage High 0.5 VCC VCC-0.4 IIR IIL IOL Reset Input Current Input Leakage Tri-State Leakage -3.0 -3.0 ICC ICC1 ICC2 Supply Current 0 0.7 VCC 0.8 VCC 0.1 VCC Typical Units @ 25°C Conditions 0.2 VCC 0.07 VCC VCC 1.48 0.98 3.2 V V V VCC 3.0 0.8 V V V External Clock Generator Driven 12 External Clock Generator Driven External Clock Generator Driven [2] 0.4 0.4 0.4 1.5 0.16 0.19 0.19 1.00 V V V V IOL=1.00mA IOL=3.2mA, [1] IOL=0.75mA [2] IOL=10mA [1] 0.45 VCC 0.75 VCC 1.9 3.12 4.75 V V V IOH=-0.75mA -80 3.0 3.0 -46 0.01 0.02 µA µA µA VRL=0V 0V,VCC 0V,VCC 20 6 10 13.2 3.2 0 mA mA µA All inputs at rail All inputs at rail All inputs at rail Notes: [1] Port 5 [2] PWM open drain 5 AC CHARACTERISTICS Timing Diagrams 1 3 XTAL1 3 2 2 External Clock 7 5 Tin 4 6 Counter Timer IRQn 8 Interrupt Request 6 9 Vcc 10 11 Internal /RESET 12 External /RESET Power On Reset HSYNC 13 14 OSC2 On Screen Display 7 AC CHARACTERISTICS TA=0° C to +70° C; VCC=+4.5V to +5.5V; FOSC=4 MHz, No Symbol Parameter Min Max Unit 1 2 3 4 TpC TrC,TfC TwC TwTinL Input Clock Period Clock Input Rise and Fall Input Clock Width Timer Input Low Width 250 1000 15 ns ns ns ns 5 6 7 8a TwTinH TpTin TrTin,TfTin TwIL Timer Input High Width Timer Input Period Timer Input Rise and Fall Int Req Input Low 3TpC 8TpC 100 ns ns 8b 9 10 11 TwIL TwIH TdPOR TdLVIRES 100 ms ns 12 13 14 15 TwRES TdHsOI TdHsOh TdWDT Int Request Input High Power On Reset Delay Low Voltage Detect to Internal RESET Condition Reset Minimum Width Hsync Start to Vosc Stop Hsync End to Vosc Start WDT Refresh Time 70 70 70 3TpC 3TpC 25 200 5TpC 2TpV 3TpV 1TpV 12 ms Note: Refer to DC Characteristics for details on switching levels. © 1991 by Zilog, Inc. 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