Z86233/243 CP96DZ81201 CUSTOMER P ROCUREMENT S PECIFICA TION Z86233/243 CMOS Z8® 8K ROM CONSUMER CONTROLLER PROCESSOR FEATURES Part ROM RAM Kbytes bytes Z86233 8 Z86243 8 237 236 Package Information I/O 24 32 28-pinDIP,SOIC,PLCC 40-pin DIP, 44-pin PLCC, 44-pin QFP ■ 32 Input/Output Lines (Three with Comparator Inputs) (Z86243 Only) ■ Vectored, Prioritized Interrupts with Programmable Polarity ■ Two Comparators ■ Two Programmable 8-Bit Counter/Timers, Each with a 6-Bit Programmable Prescaler ■ 3.0-to 5.5-Volt Operating Range ■ Low-Power Consumption: 40 mW (Typical @5.0V) ■ Watch-Dog Timer (WDT)/Power-On Reset (POR) ■ 0°C to +70°C Temperature Range (–40°C to +105°C Temperature Range Available) ■ On-Chip Oscillator that Accepts a Crystal, Ceramic Resonator, LC, RC, or External Clock Drive ■ Three Expanded Register File Control Registers ■ RAM and ROM Protect ■ Z86C33/C43 Pin and Package Compatible Version (With Addition of 4K ROM) ■ Clock Free Watch-Dog Timer (WDT) Reset GENERAL DESCRIPTION The Z86233/243 Consumer Controller Processor is a member of Zilog's Z8® single-chip microcontroller family featuring enhanced wake-up circuitry, programmable Watch-Dog timers and low-EMI options. The parts provide flexible and efficient growth paths for designers currently using the 4K ROM versions of the consumer controller devices (Z86C30/C40/C33/C43). Four address spaces, the Program Memory, Register File, Data Memory and Expanded Register File (ERF), support a wide range of memory configurations. Through the ERF, the designer has access to two additional control registers which provide extra peripheral devices, I/O ports, and register addresses. With ROM/ROMless selectivity, the Z86243 provides both external memory and pre-programmed ROM, which enables this Z8 microcontroller to be used in high-volume applications, or where code flexibility is required. Note: All Signals with a preceding front slash, "/", are active Low, e.g., B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Circuit Device Power Ground VCC GND VDD VSS For applications demanding powerful I/O capabilities, the Z86243 provides 32 pins dedicated to input and output. The Z86233 provides 24 pins dedicated to input and output. These lines are grouped into four ports with eight lines each, and are configurable under software control to provide timing, status signals, or parallel I/O. CP96DZ81201 (8/96) 1 Z86233/243 CP96DZ81201 GENERAL DESCRIPTION (Continued) Output Input Vcc GND * * * * XTAL /AS /DS R//W /RESET Machine Timing & Instruction Control Port 3 Counter/ Timers (2) RESET WDT, POR ALU FLAGS Prg. Memory 8192 Bytes Interrupt Control Two Analog Comparators R//RL† Register Pointer Register File Program Counter ERF Port 2 Port 0 4 I/O (Bit Programmable) Port 1 * 4 8 Address/Data or I/O (Byte Programmable) Address or I/O (Nibble Programmable) * Not available on Z86233. † Available on Z86243 44-Pin QFP and PLCC versions only. Functional Block Diagram 2 CP96DZ81201 (8/96) Z86233/243 CP96DZ81201 PIN DESCRIPTION P25 1 28 P24 P26 2 27 P23 P27 3 26 P22 P04 4 25 P21 P05 5 24 P20 P06 6 P03 P07 7 23 Z86233 22 VCC 8 21 P02 XTAL2 9 20 P01 XTAL1 10 19 P00 P31 11 18 P30 P32 12 17 P36 P33 13 16 P37 P34 14 15 P35 28-Pin DIP/SOIC/PLCC Pin Identification GND Pin # Symbol Function Direction 1-3 4-7 8 9 P25-P27 P07-P04 VCC XTAL2 Port 2, Pins 5,6,7 Port 0, Pins 4,5,6,7 Power Supply Crystal Oscillator In/Output In/Output 10 11-13 14-15 16 17 XTAL1 P33-P31 P35-P34 P37 P36 Crystal Oscillator Port 3, Pins 1,2,3 Port 3, Pins 4,5 Port 3, Pin 7 Port 3, Pin 6 Input Fixed Input Fixed Output Fixed Output Fixed Output 18 19-21 22 23 24-28 P30 P02-P00 GND P03 P24-P20 Port 3, Pin 0 Fixed Input Port 0, Pins 0,1,2 In/Output Ground Port 0, Pins 3 In/Output Port 2, Pins 0,1,2,3,4 In/Output Output Z86233 28-Pin SOIC Pin Configuration CP96DZ81201 (8/96) P24 P23 P22 P21 P20 P03 GND P02 P01 P00 P30 P36 P37 P35 P05 XXX XXX P06 XXX P07 XXX VCC XXX XT2 XXX XT1 XXX P31 P25 P24 P23 P22 28 27 26 25 24 23 22 21 20 19 18 17 16 15 4 1 5 26 25 Z86233 11 12 19 18 P21 XXX XXX P20 XXX P03 XXX GND XXX P02 XXX P01 XXX P00 P35 P37 P36 P30 1 2 3 4 5 6 7 8 9 10 11 12 13 14 P32 P33 P34 P25 P26 P27 P04 P05 P06 P07 VCC XTAL2 XTAL1 P31 P32 P33 P34 P04 P27 P26 28-Pin DIP Pin Configuration 28-Pin PLCC Pin Configuration 3 Z86233/243 CP96DZ81201 PIN DESCRIPTION (Continued) R//W 1 40 /DS P25 2 39 P24 P26 3 38 P23 P27 4 37 P22 P04 5 36 P21 P05 6 35 P20 P06 7 34 P03 P14 8 33 P13 P15 9 32 P12 P07 10 31 GND VCC 11 30 P02 P16 12 29 P11 P17 13 28 P10 XTAL2 14 27 P01 XTAL1 15 26 P00 P31 16 25 P30 P32 17 24 P36 P33 18 23 P37 P34 19 22 P35 /AS 20 21 /RESET Z86243 DIP 40-Pin DIP Pin Configuration 40-Pin DIP Pin Configuaration Pin # Symbol Function Direction Pin # Symbol Function Direction 1 2-4 5-7 R//W P25-P27 P04-P06 Read/Write Port 2, Pins 5, 6, 7 Port 0, Pins 4, 5, 6 Output In/Output In/Output 22 23 24 P35 P37 P36 Port 3, Pin 5 Port 3, Pin 7 Port 3, Pin 6 Output Output Output 8-9 10 11 P14-P15 P07 VCC Port 1, Pins 4, 5 Port 0, Pin 7 Power Supply In/Output In/Output 25 26-27 28-29 P30 P00-P01 P10-P11 Port 3, Pin 0 Port 0, Pins 0,1 Port 1, Pins 0,1 Input In/Output In/Output 12-13 14 15 P16-P17 XTAL2 XTAL1 Port 1, Pins 6, 7 Crystal Oscillator Crystal Oscillator In/Output Output Input 30 31 32-33 P02 GND P12-P13 Port 0, Pin 2 Ground Port 1, Pins 2, 3 In/Output 16-18 19 20 21 P31-P33 P34 /AS /RESET Port 3, Pins 1, 2, 3 Port 3, Pin 4 Address Strobe Reset Input Output Output Input 34 35-39 40 P03 P20-P24 /DS Port 0, Pin 3 Port 2, Pins 0,1,2,3,4 Data Strobe In/Output In/Output Output 4 In/Output CP96DZ81201 (8/96) GND GND P02 3 2 1 44 43 42 41 40 P00 P12 4 P01 P13 5 P10 P03 6 P11 P20 Z86233/243 CP96DZ81201 P21 7 39 P30 P22 8 38 P36 P23 9 37 P37 P24 10 36 P35 /DS 11 35 /RESET NC 12 34 R//RL R//W 13 33 /AS P25 14 32 P34 P26 15 31 P33 P27 16 30 P32 P04 17 29 P31 Z86243 PLCC XTAL1 XTAL2 P17 P16 VCC VCC P07 P15 P14 P06 P05 18 19 20 21 22 23 24 25 26 27 28 44-Pin PLCC Pin Configuration 44-Pin PLCC Pin Identification Pin # Symbol Function Direction Pin # Symbol Function Direction 1 2 3-4 5 6-10 GND GND P12-P13 P03 P20-P24 Ground Ground Port 1, Pins 2,3 In/Output Port 0, Pin 3 In/Output Port 2, Pins 0,1,2,3,4 In/Output 27 28 29-31 32 33 XTAL2 XTAL1 P31-P33 P34 /AS Crystal Oscillator Crystal Oscillator Port 3, Pins 1,2,3 Port 3, Pin 4 Address Strobe Output Input Input Output Output 11 12 13 14-16 17-19 /DS N/C R//W P25-P27 P04-P06 Data Strobe Not Connected Read/Write Port 2, Pins 5,6,7 Port 0, Pins 4,5,6 34 35 36 37 38 R//RL /RESET P35 P37 P36 ROM/ROMless select Reset Port 3, Pin 5 Port 3, Pin 7 Port 3, Pin 6 Input Input Output Output Output 20-21 22 23 24 25-26 P14-P15 P07 VCC VCC P16-P17 Port 1, Pins 4,5 Port 0, Pin 7 Power Supply Power Supply Port 1, Pins 6,7 39 40-41 42-43 44 P30 P00-P01 P10-P11 P02 Port 3, Pin 0 Port 0, Pins 0,1 Port 1, Pins 0,1 Port 0, Pin 2 Input In/Output In/Output In/Output CP96DZ81201 (8/96) Output Output In/Output In/Output In/Output In/Output In/Output 5 Z86233/243 CP96DZ81201 P00 P01 P10 P11 P02 GND GND P12 P13 P03 P20 PIN DESCRIPTION (Continued) 33 32 31 30 29 28 27 26 25 24 23 P21 34 22 P30 P22 35 21 P36 P23 36 20 P37 P24 37 19 P35 /DS 38 18 /RESET NC 39 17 R//RL R//W 40 16 /AS P25 41 15 P34 P26 42 14 P33 P27 43 13 P32 P04 44 12 P31 P15 P07 VCC 7 8 9 10 11 XTAL1 6 XTAL2 5 P17 4 P16 3 VCC 2 P14 P05 1 P06 Z86243 QFP 44-Pin QFP Pin Configuration 44-Pin QFP Pin Identification Pin # Symbol Function Direction Pin # Symbol Function Direction 1-2 3-4 5 6-7 8-9 10 11 P05-P06 P14-P05 P07 VCC P16-P17 XTAL2 XTAL1 Port 0, Pins 5,6 Port 1, Pins 4,5 Port 0, Pin 7 Power Supply Port 1, Pins 6,7 Crystal Oscillator Crystal Oscillator In/Output In/Output In/Output P31-P33 P34 /AS R//RL /RESET P35 P37 Port 3, Pins 1,2,3 Port 3, Pin 4 Address Strobe ROM/ROMless select Reset Port 3, Pin 5 Port 3, Pin 7 Input Output Output Input Input Output Output P36 P30 P00-P01 P10-P11 P02 GND GND P12-P13 Port 3, Pin 6 Port 3, Pin 0 Port 0, Pin 0,1 Port 1, Pins 0,1 Port 0, Pin 2 Ground Ground Port 1, Pins 2,3 Output Input In/Output In/Output In/Output 12-14 15 16 17 18 19 20 21 22 23-24 25-26 27 28 29 30-31 32 33-37 38 39 40 41-43 44 P03 P20-24 /DS N/C R//W P25-P27 P04 Port 0, Pin 3 Port 2, Pins 0,1,2,3,4 Data Strobe Not Connected Read/Write Port 2, Pins 5,6,7 Port 0, Pin 4 In/Output In/Output Output 6 In/Output Output Input In/Output Output In/Output In/Output CP96DZ81201 (8/96) Z86233/243 CP96DZ81201 ABSOLUTE MAXIMUM RATINGS Parameter Min Max Units Ambient Temperature under Bias Storage Temperature Voltage on any Pin with Respect to VSS [Note 1] Voltage on VDD Pin with Respect to VSS Voltage on XTAL1 and /RESET Pins with Respect to VSS [Note 2] Total Power Dissipation Maximum Allowable Current out of VSS Maximum Allowable Current into VDD Maximum Allowable Current into an Input Pin [Note 3] Maximum Allowable Current into an Open-Drain Pin [Note 4] Maximum Allowable Output Current Sinked by Any I/O Pin Maximum Allowable Output Current Sourced by Any I/O Pin –40 –65 –0.6 –0.3 –0.6 +105 +150 +7 +7 VDD+1 1.21 220 180 +600 +600 25 25 C C V V V W mA mA µA µA mA mA –600 –600 Notes: [1] This applies to all pins except XTAL pins and where otherwise noted. [2] There is no input protection diode from pin to VDD. [3] This excludes XTAL pins. [4] Device pin is not at an output Low state. Notice: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. Total power dissipation should not exceed 1.21 W for the package. Power dissipation is calculated as follows: Total Power Dissipation = VDD x [ IDD – (sum of IOH) ] + sum of [ (VDD – VOH) x IOH ] + sum of (V0L x I0L) STANDARD TEST CONDITIONS The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to Ground. Positive current flows into the referenced pin (Test Load). From Output Under Test 150 pF Test Load Diagram CAPACITANCE TA = 25°C, VCC = GND = 0V, f = 1.0 MHz; unmeasured pins returned to GND. Parameter Input capacitance Output capacitance I/O capacitance CP96DZ81201 (8/96) Min Max 0 0 0 12 pF 12 pF 12 pF 7 Z86233/243 CP96DZ81201 DC ELECTRICAL CHARACTERISTICS Sym Parameter VCC Note [3] VCH Clock Input High Voltage 3.0V 5.5V VCL Clock Input Low Voltage VIH Input High Voltage VIL Input Low Voltage VOH1 Output High Voltage VOL1 Output Low Voltage VOL2 Output Low Voltage VRH Reset Input High Voltage 3.0V 5.5V Reset Input Low Voltage 3.0V 5.5V Reset Output Low Voltage 3.0V 5.5V VRl VOLR TA = –40°C to +105°C Typical [1] Min Max @ 25°C Units Conditions Notes 0.7 VCC 0.7 VCC VCC+0.3 VCC+0.3 0.7 VCC 0.7 VCC VCC+0.3 VCC+0.3 1.8 2.6 V V Driven by External Clock Generator Driven by External Clock Generator 3.0V 5.5V 3.0V 5.5V GND-0.3 GND-0.3 0.7 VCC 0.7 VCC 0.2 VCC 0.2 VCC VCC+0.3 VCC+0.3 GND-0.3 GND-0.3 0.7 VCC 0.7 VCC 0.2 VCC 0.2 VCC VCC+0.3 VCC+0.3 1.2 2.1 1.8 2.6 V V V V Driven by External Clock Generator Driven by External Clock Generator 3.0V 5.5V 3.0V 5.5V GND-0.3 0.2 VCC GND-0.3 0.2 VCC VCC-0.4 VCC-0.4 GND-0.3 0.2 VCC GND-0.3 0.2 VCC VCC-0.4 VCC-0.4 1.1 1.6 3.1 4.8 V V V V IOH = -2.0 mA IOH = -2.0 mA [8] [8] 0.2 0.1 0.3 0.4 V V V V IOL = +4.0 mA IOL = +4.0 mA IOL = +6 mA IOL = +12 mA [8] [8] [8] [8] 1.8 2.6 1.1 1.6 0.3 0.2 V V V V V V IOL = +1.0 mA IOL = +1.0 mA [13] [13] [13] [13] [13] [13] 10 10 0.004 0.004 mV mV µA µA 3.0V 5.5V 3.0V 5.5V VOFFSET Comparator Input Offset Voltage IIL Input Leakage 3.0V 5.5V 3.0V 5.5V IOL Output Leakage IIR Reset Input Current 3.0V 5.5V 3.0V 5.5V ICC Supply Current 3.0V 5.5V 3.0V 5.5V ICC1 Standby Current (Halt Mode) ICC2 Standby Current (Stop Mode) 8 TA = 0° C to +70°C Min Max 0.6 0.4 1.2 1.2 .8 VCC VCC .8 VCC VCC GND-0.3 0.2 VCC GND-0.3 0.2 VCC 0.6 0.6 0.6 0.4 1.2 1.2 .8 VCC VCC .8 VCC VCC GND-0.3 0.2 VCC GND-0.3 0.2 VCC 0.6 0.6 -1 -1 25 25 1 1 -1 -1 25 25 2 2 [10] [10] -1 -1 -20 -20 1 1 -130 -180 -1 -1 -18 -18 2 2 -130 -180 0.004 0.004 -60 -85 µA µA µA µA VIN = OV, VCC VIN = OV, VCC 20 25 15 20 20 25 15 20 7 20 5 15 mA mA mA mA @ 16 MHz @ 16 MHz @ 12 MHz @ 12 MHz [4] [4] [4] [4] 3.0V 5.5V 3.0V 5.5V 4.5 8 3.4 7.0 4.5 8 3.4 7.0 2.0 3.7 1.5 2.9 mA mA mA mA VIN = OV, VCC @ 16 MHz VIN = OV, VCC @ 16 MHz Clock Divide-by-16 @ 16 MHz Clock Divide-by-16 @ 16 MHz [4] [4] [4] [4] 3.0V 5.5V 3.0V 5.5V 8 10 500 800 8 10 600 1000 2 4 310 600 µA µA µA µA VIN = OV, VCC WDT is not Running [6,11] VIN = OV, VCC WDT is not Running [6,11] VIN = OV, VCC WDT is Running [6,11,14] VIN = OV, VCC WDT is Running [6,11,14] VIN = OV, VCC VIN = OV, VCC CP96DZ81201 (8/96) Z86233/243 CP96DZ81201 DC ELECTRICAL CHARACTERISTICS (Continued) Sym Parameter VCC Note [3] VICR Input Common Mode Voltage Range 3.0 5.5 IALL Auto Latch Low Current IALH Auto Latch High Current 3.0V 5.5V 3.0V 5.5V VLV VCC Low Voltage Protection Voltage TA = 0° C to +70°C Min Max TA = –40°C to +105°C Min Max GND-0.3 VCC-1.0V GND-0.3 VCC-1.5V GND-0.3 VCC-1.0V GND-0.3 VCC-1.5V 8 15 -5 -8 2.1 2.4 VOH Output High Voltage (Low EMI Mode) 3.3V 5.0V VOL Output Low Voltage (Low EMI Mode) 3.3V 5.0V Typical [1] @ 25°C Units µA µA µA µA OV < VIN < VCC OV < VIN < VCC OV < VIN < VCC OV < VIN < VCC 3.3 2.8 2.8 V 4 MHz max Int. CLK Freq. 6 MHz max Int. CLK Freq. 3.1 4.8 V V IOH = -0.5 mA IOH = -0.5 mA 0.2 0.1 V V IOL = 1.0 mA IOL = 1.0 mA 0.6 0.4 Notes [10] [10] 3 5 -3 -6 VCC-0.4 VCC-0.4 0.6 0.4 V V 10 20 -7 -10 3.1 VCC-0.4 VCC-0.4 Conditions [9] [9] [9] [9] [7,15] [7,14] Notes: [1] Typicals are at VCC = 5.0V and 3.3V. [2] GND = 0V. [3] The VDD voltage specification of 3.0V guarantees 3.3V ±0.3V, and the VDD voltage specification of 5.5V guarantees 5.0V ± 0.5V. [4] All outputs unloaded, I/O pins floating, inputs at rail. [5] CL1 = CL2 = 100 pF. [6] Same as note [4] except inputs at VCC. [7] The VLV increases as the temperature decreases. [8] Standard Mode (not Low EMI). [9] Auto Latch (Mask Option) selected. [10] For analog comparator, inputs when analog comparators are enabled. [11] Clock must be forced Low, when XTAL 1 is clock-driven and XTAL2 is floating. [12] Excludes clock pins. [13] Z86243 Only. [14] 0˚C to 70˚C (standard temperature). [14] –40˚C to 105˚C (extended temperature). CP96DZ81201 (8/96) 9 Z86233/243 CP96DZ81201 AC CHARACTERISTICS External I/O or Memory Read and Write Timing Diagram 10 CP96DZ81201 (8/96) Z86233/243 CP96DZ81201 AC CHARACTERISTICS External I/O or Memory Read and Write Timing Table (SCLK/TCLK = XTAL/2) No Symbol Parameter 1 TdA(AS) Address Valid to /AS Rise Delay 2 TdAS(A) /AS Rise to Address Float Delay 3 TdAS(DR) /AS Rise to Read Data Req’d Valid 4 TwAS /AS Low Width 5 Td Address Float to /DS Fall 6 TwDSR /DS (Read) Low Width 7 TwDSW /DS (Write) Low Width 8 TdDSR(DR) /DS Fall to Read Data Req’d Valid 9 ThDR(DS) Read Data to /DS Rise Hold Time TA = 0°C to +70°C Note [3] 12 MHz 16 MHz VCC Min Max Min Max 3.0 5.5 3.0 5.5 35 35 45 45 25 25 35 35 35 35 45 45 ns ns [2] [1,2] 40 40 55 55 40 40 3.0 5.5 3.0 5.5 0 0 200 200 0 0 135 135 0 0 200 200 0 0 135 135 ns ns ns ns 3.0 5.5 3.0 5.5 110 110 80 80 110 110 80 80 ns ns ns ns 3.0 5.5 3.0 5.5 0 0 45 55 0 0 50 50 0 0 45 55 0 0 50 50 ns ns ns ns 3.0 5.5 3.0 5.5 30 45 45 45 35 35 25 25 30 45 45 45 35 55 25 25 ns ns ns ns [2] 3.0 5.5 14 TdDW(DSW) Write Data Valid to /DS Fall (Write) Delay 3.0 5.5 45 45 55 55 35 35 25 25 45 45 55 55 35 35 25 25 ns ns ns ns [2] 15 TdDS(DW) /DS Rise to Write Data Not Valid Delay 45 55 35 35 45 55 35 35 Address Valid to Read Data Req’d Valid ns ns ns ns [2] 16 TdA(DR) 3.0 5.5 3.0 5.5 17 TdAS(DS) /AS Rise to /DS Fall Delay 18 TdDI(DS) Data Input Setup to /DS Rise 3.0 5.5 3.0 5.5 65 65 115 75 45 45 60 60 65 65 115 75 45 45 60 60 ns ns ns ns 19 TdDM(AS) /DM Valid to /AS Rise Delay 3.0 5.5 35 35 30 30 35 35 30 30 ns ns 11 TdDS(AS) /DS Rise to /AS Fall Delay 12 TdR/W(AS) R//W Valid to /AS Rise Delay 13 TdDS(R/W) /DS Rise to R//W Not Valid Notes: [1] When using extended memory timing add 2 TpC. [2] Timing numbers given are for minimum TpC. [3] The VDD voltage specification of 3.0V guarantees 3.3V ± 0.3V, and the VDD voltage specification of 5.5V guarantees 5.0V ±0.5V. CP96DZ81201 (8/96) 75 75 310 310 180 180 [2] 55 55 150 150 250 250 ns ns ns ns ns /DS Rise to Address Active Delay 180 180 25 25 35 35 Units Notes 3.0 5.5 3.0 5.5 10 TdDS(A) 250 250 TA = –40°C to +105°C 12 MHz 16 MHz Min Max Min Max 150 150 230 230 75 75 310 310 230 230 [2] [1,2] [1,2] [1,2] [2] [2] [2] [2] [1,2] [2] [1,2] [2] Standard Test Load All timing references use 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 11 Z86233/243 CP96DZ81201 AC ELECTRICAL CHARACTERISTICS Additional Timing Diagram 3 1 Clock 2 7 2 3 7 TIN 4 5 6 IRQN 8 9 Clock Setup 11 Stop-Mode Recovery Source 10 Additional Timing 12 CP96DZ81201 (8/96) Z86233/243 CP96DZ81201 AC ELECTRICAL CHARACTERISTICS Additional Timing Table (SCLK/TCLK = XTAL/2) No Symbol Parameter 1 TpC 2 TrC,TfC Clock Input Rise & Fall Times 3 TwC Input Clock Width 4 TwTinL Timer Input Low Width 5 TwTinH Timer Input High Width 6 TpTin 7 Input Clock Period Timer Input Period TrTin, TfTin 8A TwIL Timer Input Rise & Fall Timer 8B TwIL Int. Request Low Time 9 Int. Request Input High Time TwIH 10 Twsm 11 Tost 12 Twdt 13 TPOR Int. Request Low Time VCC Note[6] Power On Reset Delay DC DC 15 15 62.5 62.5 83 83 3.0V 5.5V 3.0V 5.5V 41 41 100 70 31 31 100 70 41 41 100 70 31 31 100 70 3.0V 5.5V 3.0V 5.5V 5TpC 5TpC 8TpC 8TpC 5TpC 5TpC 8TpC 8TpC 5TpC 5TpC 8TpC 8TpC 5TpC 5TpC 8TpC 8TpC 100 100 DC DC 15 15 TA = –40°C to +105°C 12 MHz 16 MHz Min Max Min Max Units 3.0V 5.5V 3.0V 5.5V 83 83 100 100 DC DC 15 15 62.5 62.5 3.0V 5.5V 3.0V 5.5V 100 70 100 70 100 70 100 70 3.0V 5.5V 3.0V 5.5V 5TpC 5TpC 5TpC 5TpC 5TpC 5TpC 5TpC 5TpC 5TpC 5TpC 5TpC 5TpC 5TpC 5TpC 5TpC 5TpC 12 12 12 12 12 12 12 12 STOP-Mode Recovery Width Spec 3.0V 5.5V Oscillator Startup Time 3.0V 5.5V Watch-Dog Timer Delay Time Before Time-Out TA = 0°C to +70°C 12 MHz 16 MHz Min Max Min Max 5TpC 5TpC 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 10 5 20 10 40 20 160 80 3.0V 5.5V 7 3 5TpC 5TpC 10 5 20 10 40 20 160 80 24 13 100 100 7 3 24 13 7 3 [1] [1] [1] [1] ns ns ns ns [1] [1] [1] [1] ns ns ns ns ns ns 5TpC 5TpC 7 3 [1] [1] [1,2] [1,2] [1,3] [1,3] [1,2] [1,2] 10 5 20 10 40 20 160 80 25 14 ns ns ns ns [1] [1] [1] [1] 100 100 5TpC 5TpC 10 5 20 10 40 20 160 80 DC DC 15 15 Notes [4] [4] ms ms ms ms ms ms ms ms 25 14 D1 0 0 0 0 1 1 1 1 D0 0 [5] 0 [5] 1 [5] 1 [5] 0 [5] 0 [5] 1 [5] 1 [5] ms ms Notes: [1] Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. [2] Interrupt request via Port 3 (P31-P33). [3] Interrupt request via Port 3 (P30). [4] SMR-D5 = 0. [5] Reg. WDTMR, internal RC used. [6] The VDD voltage specification of 3.0V guarantees 3.3V ± 0.3V, and the VDD voltage specification of 5.5V guarantees 5.0V ± 0.5V. CP96DZ81201 (8/96) 13 Z86233/243 CP96DZ81201 AC ELECTRICAL CHARACTERISTICS Additional Timing Table (Divide-By-One Mode, SCLK/TCLK = XTAL) No Symbol Parameter 1 TpC Input Clock Period 2 TrC,TfC Clock Input Rise & Fall Times 3 TwC Input Clock Width 4 TwTinL Timer Input Low Width 5 TwTinH Timer Input High Width 6 TpTin Timer Input Period 7 Timer Input Rise & Fall Timer 8A TrTin, TfTin TwIL 8B TwIL Int. Request Low Time 9 TwIH Int. Request Input High Time 10 Twsm STOP-Mode Recovery Width Spec 11 Tost Oscillator Startup Time Int. Request Low Time Vcc Note [6] TA = 0°C to +70°C 4 MHz Min Max DC DC 25 25 TA = –40°C to +105°C 4 MHz Min Max Units 3.0V 5.5V 3.0V 5.5V 250 250 250 250 3.0V 5.5V 3.0V 5.5V 125 125 100 70 125 125 100 70 3.0V 5.5V 3.0V 5.5V 3TpC 3TpC 4TpC 4TpC 3TpC 3TpC 4TpC 4TpC 3.0V 5.5V 3.0V 5.5V 100 100 100 70 100 70 3.0V 5.5V 3.0V 5.5V 3TpC 3TpC 3TpC 3TpC 3TpC 3TpC 3TpC 2TpC 3.0V 5.5V 3.0V 5.5V 12 12 12 12 5TpC 5TpC DC DC 25 25 Notes ns ns ns ns [1,7,8] [1,7,8] [1,7,8] [1,7,8] ns ns ns ns [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] 100 100 ns ns ns ns [1,7,8] [1,7,8] [1,2,7,8] [1,2,7,8] [1,3,7,8] [1,3,7,8] [1,2,7,8] [1,2,7,8] ns ns 5TpC 5TpC [4,8] [4,8] [4,8,9] [4,8,9] Notes: [1] Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. [2] Interrupt request via Port 3 (P33-P31). [3] Interrupt request via Port 3 (P30). [4] SMR-D5 = 1, POR STOP mode delay is on. [5] Reg. WDTMR. [6] The VDD voltage specification of 3.0V guarantees 3.3V ± 0.3V, and the VDD voltage specification of 5.5V guarantees 5.5V ± 0.5V. [7] SMR D1 = 0. [8] Maximum frequency for internal system clock is 4 MHz when using XTAL divide-by-one mode. [9] For RC and LC oscillator, and for oscillator driven by clock driver. 14 CP96DZ81201 (8/96) Z86233/243 CP96DZ81201 AC ELECTRICAL CHARACTERISTICS Handshake Timing Diagrams Data In Data In Valid 1 Next Data In Valid 2 3 /DAV (Input) Delayed DAV 4 5 RDY (Output) 6 Delayed RDY Input Handshake Timing Data Out Valid Data Out Next Data Out Valid 7 /DAV (Output) Delayed DAV 8 9 11 10 RDY (Input) Delayed RDY Output Handshake Timing CP96DZ81201 (8/96) 15 Z86233/243 CP96DZ81201 AC ELECTRICAL CHARACTERISTICS Handshake Timing Table No Symbol Parameter 1 TsDI(DAV) Data In Setup Time 2 ThDI(DAV) Data In Hold Time 3 TwDAV Data Available Width 4 TdDAVI(RDY) DAV Fall to RDY Fall Delay 5 TdDAVId(RDY) DAV Rise to RDY Rise Delay 6 TdRDY0(DAV) RDY Rise to DAV Fall Delay 7 TdD0(DAV) Data Out to DAV Fall Delay 8 TdDAV0(RDY) DAV Fall to RDY Fall Delay 9 TdRDY0(DAV) RDY Fall to DAV Rise Delay 10 TwRDY RDY Width 11 TdRDY0d(DAV) RDY Rise to DAV Fall Delay TA = 0°C to +70°C 12 MHz 16 MHz Min Max Min Max TA = –40°C to +105°C 12 MHz 16 MHz Min Max Min Max 3.0V 5.5V 3.0V 5.5V 0 0 160 115 0 0 160 115 0 0 160 115 0 0 160 115 IN IN IN IN 3.0V 5.5V 3.0V 5.5V 155 110 155 110 155 110 155 110 IN IN IN IN VCC Note[1,2] 160 115 160 115 160 115 160 115 120 80 120 80 120 80 120 80 Data Direction 3.0V 5.5V 3.0V 5.5V 0 0 0 0 0 0 0 0 IN IN IN IN 3.0V 5.5V 3.0V 5.5V 42 42 0 0 31 31 0 0 42 42 0 0 31 31 0 0 OUT OUT OUT OUT 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 160 115 110 80 160 115 110 80 110 80 160 115 110 80 110 80 160 115 110 80 110 80 110 80 OUT OUT OUT OUT OUT OUT Notes: [1] Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. [2] The VDD voltage specification of 3.0V guarantees 3.3V ± 0.3V and the VDD voltage specification of 5.5V guarantees 5.0V ±0.5V. 16 CP96DZ81201 (8/96) Z86233/243 CP96DZ81201 PRECAUTIONS (1) When in ROM Protect Mode, and executing out of External Program Memory , instructions LDC, LDCI, LDE, and LDEI cannot read Internal Program Memory. When in ROM Protect Mode, and executing out of Internal Program Memory , instructions LDC, LDCI, LDE, and LDEI can read Internal Program Memory. (2) The device has an oscillator-free reset for the device pins. When the device is reset from a WDT timeout, POR, or VBO, the reset will force the device pins to their reset default state even if the oscillator is not running. (3) The Port 3 outputs are reset to High State after Reset, except after Stop-Mode Recovery, at which the outputs remain in the last state. (4) Extended timing is operable. (5) P0/P1/P2/P3 is Low-EMI software programmable. (6) P0/P1/P2 is software programmable for open-drain. (7) Expanded register PCON is Write Only. (8) WDTMR is writeable only within the first 60 internal system clocks after Reset. Afterward, the WDTMR is write protected. (9) Device functions down to the VLV threshold. At temperatures less than 25°C, the VLV threshold will rise to a maximum VDD of 3.6V. (10) Low EMI is 25 percent of standard pull-down output driver and 25 percent of standard pull-up output driver. (11) There is no clock filter on Reset pin. (12) Registers FE Hex (SPH) and FF Hex (SPL) are set to 00Hex after any reset. (13) When Low EMI OSC is selscted (PCONReg Bit D7=0), the output drive of /DS, /AS, and R//W will also be in low emi mode. (14) P01M Reg Bit D4,D3 must be set to 00Hex for Z86233. CP96DZ81201 (8/96) 17 Z86233/243 CP96DZ81201 © 1996 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. 18 Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX 408 370-8056 Internet: http://www.zilog.com CP96DZ81201 (8/96)