Z86C93 CPS DC-4020-12 CUSTOMER PROCUREMENT SPECIFICATION Z86C93 CMOS Z8® MULT/DIV MICROCONTROLLER GENERAL DESCRIPTION The Z86C93 is a CMOS ROMless Z8 microcontroller enhanced with a hardwired 16-bit x 16-bit multiplier, 32-bit/16-bit divider, and three 16-bit counter timers (see Functional Block Diagram). A capture register and a fast decrement mode are also provided. It is offered in 40-pin PDIP, 44-pin PLCC, 44-pin QFP, and 48-pin VQFP packages. The Z86C93 is functionally compatible with the Z86C91, yet it offers a more powerful mathematical capability. In the PDIP package, the Z86C93 is fully pin compatible with the Z86C91. In the PLCC package, the Z86C93 is also pin compatible to the Z86C91, with the addition of four signals (SCLK, /IACK, /SYNC, and /WAIT). The /WAIT signal is only available on the 25 MHz and 33 MHz devices. The Z86C93 provides up to 16 output address lines permitting an address space of up to 64 Kbytes of data and program memory each. Eight address outputs (AD7-AD0) are provided by a multiplexed, 8-bit, Address/Data bus. The remaining 8 bits can be provided by the software configuration of Port 0 to output address bits A15-A8. DC-4020-12 (2-16-94) There are 256 registers located on chip and organized as 236 general-purpose registers, 16 control and status registers, one reserved register, and up to three I/O port registers. The register file can be divided into 16 groups of 16 working registers each. Configuration of the registers in this manner allows the use of short format instructions; in addition, any of the individual registers can be accessed directly. There are an additional 17 registers implemented in the Expanded Register File in Banks D and E. Two of the registers may be used as general-purpose registers, while 15 registers supply the data and control functions for the Multiply/Divide Unit and additional Counter/Timer blocks. Notes: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Circuit Device Power Ground VCC GND VSS VDD 1 Z86C93 CPS DC-4020-12 UART ALU Three 16-Bit Counter/Timers FLAGS 32 ÷ 16 Divider Register Pointer Register File 256 x 8-Bit Program Counter Interrupt Control Port 2 Port 0 4 I/O (Bit Programmable) Port 1 4 Address or I/O (Nibble Programmable) Functional Block Diagram 2 8 Address/Data /SYNC IACK SCLK /RESET R//W Machine Timing, Emulation and Instruction Control Port 3 16 x 16 Multiplier /DS VCC GND /WAIT (25 MHz & 33 MHz Devices Only.) Output Input /AS XTAL GENERAL DESCRIPTION (Continued) Z86C93 CPS DC-4020-12 4 P30 5 36 P25 /RESET 6 35 P24 R//W 7 34 P23 /DS 8 33 P22 /AS 9 32 P21 P35 Z86C93 10 DIP 31 P20 11 30 P33 GND /RESET R//W /DS /AS P26 37 P32 12 29 P34 P00 13 28 P17 P01 14 27 P16 P02 15 26 P15 P03 16 25 P14 P04 17 24 P13 P05 18 23 P12 P06 19 22 P11 P07 20 21 P10 5 4 3 2 1 P26 P25 44 43 42 41 40 7 39 8 38 9 37 10 36 35 NC P24 P23 P22 P21 P20 P33 P34 P35 GND 11 P32 P00 13 33 14 32 P01 P02 15 31 16 30 P17 P16 IACK 17 29 P15 Z86C93 MCU 12 34 18 19 20 21 22 23 24 25 26 27 28 P03 P37 6 P27 P27 P14 /SYNC 38 P31 3 P12 P13 XTAL1 +5V P36 P31 P10 P11 P36 39 XTAL1 XTAL2 40 2 P05 P06 P07 1 P04 VCC XTAL2 SCLK P30 P37 PIN CONFIGURATION 44-Pin PLCC Package (20 MHz) 6 7 8 9 10 11 P01 P02 IACK 3 4 5 P00 1 2 44-Pin QFP Package (20 MHz) P03 42 +5V XTAL2 XTAL1 P37 P30 SCLK NC P15 Z86C93 MCU 43 44 45 46 47 48 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 /SYNC P14 P13 P12 P11 P10 P07 NC P06 P05 P04 P03 P02 IACK 44 P05 P04 NC 24 23 22 21 20 19 18 P00 P01 14 13 12 37 38 39 40 41 P32 41 42 43 P11 P10 P07 P06 P25 P26 P27 P31 P36 /DS /AS P35 GND 17 16 15 /SYNC P14 P13 P12 NC /RESET R//W 19 18 Z86C93 MCU P32 P37 P30 SCLK 36 37 38 39 40 /DS /AS P35 GND XTAL2 XTAL1 22 21 20 /RESET R//W P31 P36 +5V 34 35 P17 P16 36 35 34 33 32 31 30 29 28 27 26 25 33 32 31 30 29 28 27 26 25 24 23 P25 P26 P27 P22 P21 P20 P33 P34 NC P24 P23 P17 P16 P15 P23 P22 P21 P20 P33 P34 NC P24 40-Pin DIP Package (20 MHz) 48-Pin VQFP Package (20 MHz) 3 Z86C93 CPS DC-4020-12 40 P36 2 39 P31 XTAL1 3 38 P27 P37 4 37 P26 P30 5 36 P25 /RESET 6 35 P24 R//W 7 34 P23 /DS 8 33 P22 /AS 9 32 P21 P35 10 31 P20 GND 11 30 P32 12 P00 /RESET R//W /DS /AS 6 1 5 4 3 2 P27 P26 P25 1 +5V P36 P31 VCC XTAL2 SCLK P30 P37 XTAL1 XTAL2 PIN CONFIGURATIONS (Continued) 44 43 42 41 40 7 39 8 38 9 37 10 36 35 /WAIT P24 P23 P22 P21 P20 P33 P34 P35 GND 11 P32 P00 13 33 14 32 P01 P02 15 31 P33 16 30 P17 P16 29 P34 IACK 17 29 P15 13 28 P17 P01 14 27 P16 P02 15 26 P15 P03 16 25 P14 P04 17 24 P13 P05 18 23 P12 P06 19 22 P11 P07 20 21 P10 12 34 P14 /SYNC P10 P11 P12 P13 18 19 20 21 22 23 24 25 26 27 28 P03 P04 P05 P06 P07 Z86C93 DIP Z86C93 MCU 44-Pin PLCC Package (25 MHz and 33 MHz) P17 P16 P15 NC /WAIT P24 P23 P22 P21 P20 P33 P34 P15 P17 P16 P34 /WAIT P24 P23 P22 P21 P20 P33 40-Pin DIP Package (25 MHz and 33 MHz) 36 35 34 33 32 31 30 29 28 27 26 25 44-Pin QFP Package (25 MHz and 33 MHz) 4 P05 P04 P03 XTAL1 P37 P30 SCLK 40 41 42 43 44 45 46 47 48 Z86C93 MCU 1 2 3 4 5 6 7 8 9 10 11 12 P00 P01 P02 IACK P01 P02 IACK 6 7 8 9 10 11 P00 3 4 5 P32 1 2 /SYNC P14 P13 P12 P11 P10 P07 P06 37 38 39 P32 22 21 20 19 18 17 16 15 14 13 12 Z86C93 MCU /DS /AS P35 GND P37 P30 SCLK 34 35 36 37 38 39 40 41 42 43 44 /RESET R//W P25 P26 P27 P31 P36 +5V XTAL2 XTAL1 P25 P26 P27 P31 P36 NC +5V XTAL2 NC /RESET R//W /DS /AS P35 GND 33 32 31 30 29 28 27 26 25 24 23 48-Pin VQFP Package (25 MHz and 33 MHz) 24 23 22 21 20 19 18 17 /SYNC P14 P13 P12 P11 P10 P07 NC 16 15 14 13 P06 P05 P04 P03 Z86C93 CPS DC-4020-12 ABSOLUTE MAXIMUM RATINGS Symbol Description Min Max Units VCC TSTG TA –0.3 –65 † +7.0 +150 † V C C Supply Voltage* Storage Temp Oper Ambient Temp * Voltages on all pins with respect to GND. † See Ordering Information Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. STANDARD TEST CONDITIONS The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Test Load Diagram). I OL DUT Device Under Test V Commutation 50 pf I OH Test Load Diagram 5 Z86C93 CPS DC-4020-12 DC ELECTRICAL CHARACTERISTICS VCC = 3.3V ± 10% TA = 0°C to +70°C Min Max Sym Parameter VCH VCL VIH VIL Max Input Voltage Clock Input High Voltage Clock Input Low Voltage Input High Voltage Input Low Voltage VOH VOH VOL VRH VRl Output High Voltge 1.8 Output High Voltage VCC –100mV Output Low Voltage Reset Input High Voltage 0.8xVCC Reset Input Low Voltage -0.03 IIL IOL IIR ICC Input Leakage Output Leakage Reset Input Current Supply Current ICC1 ICC2 IAL Standby Current (HALT Mode) Standby Current (HALT Mode) Auto Latch Current –10 0.8 VCC –0.03 0.7xVCC –0.3 –2 –2 Units Conditions 7 VCC 0.1xVCC VCC 0.1xVCC V V V V V IIN 250 µA Driven by External Clock Generator Driven by External Clock Generator 0.4 VCC 0.1xVCC V V V V V IOH= –1.0 mA IOH = –100 µA IOL = +1.0 mA 2 2 –180 30 20 µA µA µA mA Test at 0V, VCC Test at 0V, VCC VRL = 0V @ 25 MHz [1] 12 8 10 8 1 5 mA µA µA HALT Mode VIN = OV, VCC @ 25 MHz [1] STOP Mode VIN = OV, VCC [1] Note: [1] All inputs driven to 0V, or Vcc and outputs floating. 6 Typical at 25°C Z86C93 CPS DC-4020-12 DC ELECTRICAL CHARACTERISTICS VCC = 5.0V ± 10% TA = 0°C to +70°C Min Max Sym Parameter VCH VCL VIH VIH VIL Max Input Voltage Clock Input High Voltage 3.8 Clock Input Low Voltage –0.03 Input High Voltage (P0,P1,P2) 2.0 Input High Voltage (P3) 2.2 Input Low Voltage –0.3 VOH VOH VOL VRH VRl Output High Voltge 2.4 Output High Voltage VCC –100mV Output Low Voltage Reset Input High Voltage 3.8 Reset Input Low Voltage –0.03 IIL IOL IIR ICC Input Leakage Output Leakage Reset Input Current Supply Current ICC1 Standby Current (HALT Mode) ICC2 IAL Standby Current Auto Latch Current –2 –2 –16 Typical at 25°C Units Conditions 7 VCC 0.8 VCC VCC 0.8 V V V V V V IIN 250 µA Driven by External Clock Generator Driven by External Clock Generator 0.4 VCC 0.8 V V V V V IOH= –2.0 mA IOH = –100 µA IOL = +5 mA 2 2 –180 55 40 30 35 25 20 µA µA µA mA mA mA Test at 0V, VCC Test at 0V, VCC VRL = 0V @ 33 MHz [1] @ 25 MHz [1] @ 20 MHz [1] 20 15 12 10 16 15 9 7 1 5 mA mA mA µA µA HALT Mode VIN = OV, VCC @ 33 MHz [1] HALT Mode VIN = OV, VCC @ 25 MHz [1] HALT Mode VIN = OV, VCC @ 20 MHz [1] STOP Mode VIN = OV, VCC [1] Note: [1] All inputs driven to 0V, or Vcc and outputs floating. 7 Z86C93 CPS DC-4020-12 AC CHARACTERISTICS External Memory Read/Write Timing Diagram R/W, /DM 19 20 12 13 Port 0 A8 - A15 21 16 Port 1 D0 - D7 IN A0 - A7 A0 - A7 9 2 3 10 /AS 8 11 4 5 /DS (Read) Port1 1 6 17 D0 - D7 OUT A0 - A7 14 15 7 /DS (Write) External Memory Read/Write Timing 8 A0-A7 Z86C93 CPS DC-4020-12 AC CHARACTERISTICS External I/O or Memory Read and Write; DSR/DSW; WAIT Timing Table 33 MHz Min Max TA = 0°C to +70°C 25 MHz 20 MHz Min Max Min Max No Sym Parameter 1 2 3 4 TdA(AS) ThAS(A) TdAS(DI) TwAS Address Valid To /AS Rise Delay /AS Rise To Address Hold Time /AS Rise To Data In Req’d Valid Delay /AS Low Width 5 6 7 8 TdAZ(DSR) TwDSR TwDSW TdDSR(DI) Address Float To /DS Fall (Read) 0 /DS (Read) Low Width 65 /DS (Write) Low Width 40 /DS Fall (Read) To Data in Req'd Valid Delay 9 10 11 12 ThDSR(DI) TdDS(A) TdDS(AS) TdR/W(AS) /DS Rise (Read) to Data In Hold Time /DS Rise To Address Active Delay /DS Rise To /AS Delay R/W Valid To /AS Rise Delay 0 25 16 12 0 40 30 26 0 48 36 32 ns ns ns ns 13 14 15 16 TdDS(R/W) TdDO(DSW) ThDSW(DO) TdA(DI) /DS Rise To R/W Not Valid Delay 12 Data Out To /DS Fall (Write) Delay 12 /DS Rise (Write) To Data Out Hold Time 12 Address Valid To Data In Req’d Valid Delay 30 34 34 36 40 40 ns ns ns ns 17 19 20 TdAS(DSR) TdDM(AS) TdDS(DM) /AS Rise To /DS Fall (Read) Delay /DM Valid To /AS Rise Delay /DS Rise To /DM Valid Delay 21 22 23 24 ThDS(A) TdXT(SCR) TdXT(SCF) TdXT(DSRF) /DS Rise To Address Valid Hold Time XTAL Falling to SCLK Rising** XTAL Falling to SCLK Falling** XTAL Falling to/DS Read Falling** 35 35 45 35 ns ns ns ns 25 26 27 28 29 30 TdXT(DSRR) TdXT(DSWF) TdXT(DSWF) TsW(XT) ThW(XT) TwW XTAL Falling to /DS Read Rising** XTAL Falling to /DS Write Falling** XTAL Falling to /DS Write Rising** Wait Set-up Time Wait Hold Time Wait Width (One Wait Time) 35 45 35 ns ns ns ns ns ns 15 20 96 15 5 15 20 22 25 130 28 26 28 160 36 ns ns ns ns 0 100 65 0 130 75 ns ns ns ns 55 85 115 30 15 15 Units 100 160 40 22 34* 10* 15* 25* 200 48 26 ns ns ns Notes: When using extended memory timing add 2 TpC. Timing numbers given are for minimum TpC. * Typical value to be characterized (25 MHz). ** External clock drive. 9 Z86C93 CPS DC-4020-12 XTAL1 (External Clock Drive) 22 23 SCLK 25 24 /DS DSR (READ) 27 26 /DS DSW (Write) XTAL/SCLK To DSR and DSW Timing T1 T2 TW TW TW XTAL1 SCLK /AS /DS 32 /WAIT 30 31 XTAL/SCLK To WAIT Timing (25 MHz and 33 MHz Devices Only) 10 T3 T1 Z86C93 CPS DC-4020-12 AC CHARACTERISTICS Additional Timing Diagram 3 1 Clock 2 7 2 3 7 T IN 4 5 6 IRQ N 8 9 Additional Timing AC CHARACTERISTICS Additional Timing Table No Symbol Parameter 1 2 3 4 TpC TrC,TfC TwC TwTinL Input Clock Period Clock Imput Rise & Fall Times Input Clock Width Timer Input Low Width 5 6 7 8A TwTinH TpTin TrTin,TfTin TwIL 8B 9 TwIL TwIH 33 MHz Min Max 30 10 75 1000 5 TA = 0°C to +70°C 25 MHz 20 MHz Min Max Min Max 42 1000 10 50 11 75 15 75 Timer Input High Width 3 TpC Timer Input Period 8 TpC Timer Input Rise & Fall Times 100 Interrupt Request Input Low Times 70 3 TpC 8 TpC 100 70 3 TpC 8 TpC 100 70 Interrupt Request Input Low Times 5 TpC Interrupt Request Input High Times 3 TpC 5 TpC 3 TpC 5 TpC 3 TpC 1000 10 Units Notes ns ns ns ns [1] [1] [1] [2] ns ns [2] [2] [2] [2,4] [2,5] [2,3] Notes: [1] [2] [3] [4] [5] Clock timing references use 3.8V for a logic 1 and 0.8V for a logic 0. Timing references use 2.0V for a logic 1 and 0.8V for a logic 0. Interrupt references request through Port 3. Interrupt request via Port 3 (P33-P31)`. Interrupt request via Port 30. 11 Z86C93 CPS DC-4020-12 AC CHARACTERISTICS Handshake Timing Diagrams Data In Data In Valid 1 Next Data In Valid 3 2 /DAV (Input) Delayed DAV 4 5 RDY (Output) 6 Delayed RDY Input Handshake Timing Data Out Data Out Valid Next Data Out Valid 7 /DAV (Output) Delayed DAV 8 9 11 10 RDY (Input) Delayed Output Handshake Timing 12 RDY Z86C93 CPS DC-4020-12 AC CHARACTERISTICS Handshake Timing Table No Symbol Parameter 1 2 3 4 TsDI(DAV) ThDI(DAV) TwDAV TdDAVIf(RDYf) Data In Setup Time to /DAV RDY to Data In Hold Time /DAV Width /DAV to RDY Delay 5 6 7 8 TdDAVIr(RDYr) TdRDYOr(DAVIf) TdD0(DAV) TdDAV0f(RDYIf) DAV Rise to RDY Wait Time RDY Rise to DAV Delay Data Out to DAV Delay /DAV to RDY Delay 9 10 11 TdRDYIf(DAVOr) TwRDY TdRDYIr(DAVOf) RDY to /DAV Rise Delay RDY Width RDY Rise to DAV Wait Time © 1994 by Zilog, Inc. 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TA = 0°C to +70°C Min Max 0 0 40 70 40 0 TpC 0 70 40 40 Units Data Direction ns ns ns ns In In In In ns ns ns ns In In Out Out ns ns ns Out Out Out Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056 13