ZILOG Z86U18

PRELIMINARY PRODUCT SPECIFICATION
1
Z86U18
1
USB DEVICE CONTROLLER WITH
CMOS Z86K15 MCU
FEATURES
Device
ROM
(KB)
RAM
(Bytes)
I/O
Lines
Speed
(MHz)
Z86U18
4
188
32
6
■
Intergrated USB Transceiver @ 1.5 Mb/sec
■
For Use In A Variety of Applications Including Keyboards
and Game Controllers
■
USB Serial Interface Engine, Transceiver, and MCU
Intergrated for USB Function Controller
■
Programmable 8-Bit Counter/Timer,
Programmable Prescaler
■
+4.0V to +5.5V Operating Range
■
Five Vectored, Priority Interrupts from Five Different
Sources
■
Low Power Consumption: 60 mW @ 6 MHz
■
■
Digital Inputs CMOS Levels with Internal Pull-Up
Resistors
On-Chip Oscillator, Which Accepts A Crystal, Ceramic
Resonator, LC or External Clock Drive (all clock speeds
@ 6 MHz)
■
Four Direct Connect LED Drive Ports
■
Low System EMI Emission
■
Power-On Reset (POR), Hardware Watch-Dog Timer
(WDT)
■
HALT/STOP Modes
with
6-Bit
GENERAL DESCRIPTION
The Z86U18 USB Controller is a member of the Z8¨ MCU
family. The Z86U18 is characterized by a flexible I/O
scheme, an efficient register architecture, and a number of
ancillary features. It contains a dedicated USB interface
(transceiver and SIE).
For applications demanding powerful I/O capabilities, the
Z86U18 (40- and 44-pin versions) provides 32 pins dedicated to application input and output. These lines are
grouped into four ports, each port consists of eight lines
and are configurable under software control to provide timing, status signals, and serial or parallel I/O ports. It also
has 2 pins to connect directly to the USB cable.
The Z86U18 achieves low EMI by means of several circuit
implementations in the output drivers and clock circuitry of
the device.
With fast execution, efficient use of memory, sophisticated
interrupt, input/output bit-manipulation capabilities, and
easy hardware/software system expansion, along with low
cost and low power consumption, the Z86U18 meets the
needs of a variety of sophisticated applications (Figure 1:
Functional Block Diagram)
Notes: All signals with a preceding front slash, "/", are active Low. For example, B//W (WORD is active Low); /B/W
(BYTE is active Low, only).
To unburden the system from coping with real-time tasks,
such as counting/timing and I/O data communications, the
Z86U18 offers an on-chip counter/timer with a large number of user-selectable modes.
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1
Z86U18
USB Device Controller with CMOS Z86K15 MCU
Zilog
GENERAL DESCRIPTION (Continued)
Power connections follow conventional descriptions below:
Connection
Circuit
Device
Power
VCC
VDD
Ground
GND
VSS
2. Watch-Dog Timer (WDT): WDT is also driven by the
system clock and subject to same tolerance. The
WDT can be programmed for time out value of:
WDT = POR/2
This device is based on the Z86K15 device with the following changes or modifications:
1. Power-On Reset (POR): POR timing is a function of
the system clock.
POR = (32 * 216)/f = .098
3. EMI, 801-2 and 801-4 Compliance: When used with
good engineering practice, this device should meet
Class B FCC with at least 10 dB of margin and comply
with the 801-2 group 4 air discharge. It shall meet 8014 EFT requirements in a system.
4. XTAL: Drive to 3-pin ceramic resonator (@ 6 MHz).
5. XTAL In: From ceramic resonator or crystal.
VCC
Output
GND
VCC
4
4
3.3 V
VR
VUSB
Input
XTAL2
XTAL1
POR is in seconds and frequency in Hz. It may need
a programmable timer for warm reset (USB reset).
Machine
Timing & Inst.
Control
Port 3
WDT
D+
D-
USB SIE
and Trans
ALU
POR
Flags
Program
Memory
4 KB ROM
Counter/
Timers
Register
Pointer
Interrupt
Control
Port 2
4
Input
I/O
(Bit Programmable)
Program
Counter
Register File
208 x 8-Bytes
Port 0
Port 1
8
8
Open-Drain
Output
Open-Drain
Output
Figure 1. Z86U18 Functional Block Diagram
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Z86U18
USB Device Controller with CMOS Z86K15 MCU
Zilog
USB FUNCTIONAL BLOCK DESCRIPTION
The USB portion of the chip is divided into two areas, the
transceiver and the Serial Interface Engine (SIE). The
transceiver handles incoming differential signals and "single ended zero" (SE0). It also converts output data in digital form to differential drive at the proper levels.
The SIE does all other processing on incoming and out going data. This includes signal recovery timing, bit stuffing,
validity checking, data sequencing, and handshaking to
Preamble
sent at full speed
SYNC
PID
Hub enables low
speed port outputs
Hub Setup
the host. Data flow into and out of the MCU portions is processed through eight registers mapped into Expanded
Register File Memory at locations 010 to 017.
The USB SIE handles two endpoints (control at Endpoint
0 and data into the host from Endpoint 1). All communications are at the 1.5 Mb/sec HID class data rate. Future devices will handle the full 12 Mb/sec data rate.
Hub enables low
speed port outputs
Token sent at low speed
SYNC
ENDP . . .
PID
EOP
Data packet sent at low speed
SYNC
PID
Preamble
sent at full speed
SYNC
PID
DATA
Hub enables low
speed port outputs
Hub Setup
CRC
EOP
Handshake sent at low speed
SYNC
PID
Hub enables low
speed port outputs
EOP
Figure 2. Data To/From K86U18
USB SUSPEND/RESUME FUNCTIONALITY
Suspend is intitiated by the host only, when it stops sending start of frame signaling or start of frame keep alive
pulse.
When SIE detects the absence of start of frame signaling
from the host for more than 3 miliseconds, it sets the Suspend bit in Reg7 and the Supspend Interrupt bit in Reg6
which interrupts the microcontroller. There is also an internal Suspend node that reflects the state of the Suspend bit
in Reg7. This Suspend node is used to put the tranceiver
in Suspend mode. When the microcontroller gets the Suspend Interrupt, it stops all the clocks.
Resume can be initiated by host or by UC. Host initiates
Resume by sending J to K transition on D+ and D- pins.
Upon detecting J to K transition, the GFI makes Resumeout signal active, which is used to wake the UC. Once the
UC is up, it clears the suspend bit in Reg7. UC can initiate
Resume by writing 1 to Send Resume bit in Reg7 for longer than 10mSec. This makes GFI to send J to K transition
on D+ and D- pins which indicates to the host the Resume
state. After 10 msec UC also clears the Suspend bit in
Reg7.
U18 EMULATIONS AND CODE DEVELOPMENT
An existing ICEBOXª Emulator has been modified by the
addition of an adaptor board. This board includes a FPGA
with the logic of the SIE, a commercial USB transceiver,
and a voltage regulator. These three functions adapt our
Z86C15/K15 to the USB world allowing the customer to
develop code to be placed into the ROM of U18s.
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The ICEBOX has complete functional equivalence to the
final part including pin out to the application board. This
begins with the 40-pin DIP and covers the other pin configurations. Once code has been verified, it can be released
to Zilog and placed into the ROM of the Z86U18.
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Z86U18
USB Device Controller with CMOS Z86K15 MCU
Zilog
PIN IDENTIFICATION
P36
P17
P16
P15
P14
P13
P12
P11
P10
P35
GND
P00
P01
P02
P03
P04
P05
P06
P07
P34
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Z86UXX
DIP
P23
P22
P21
P20
P37
P24
Test
XTALI
XTAL0
GND
P25
P26
VUSB
VCC
(IN)
(OUT)
D+
DP30
P31
P32
P33
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
Figure 3. 40-Pin DIP Pin ConÞguration
6
7
8
9
10
11
12
13
14
15
16
17
18
4
42
1
Z86U18
PLCC/QFP
20
22
24
26
40
39
38
37
36
35
34
33
32
31
30
29
28
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
Pin assignments to be determined.
Figure 4. 44-Pin PLCC and QFP Pin Assignments
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Z86U18
USB Device Controller with CMOS Z86K15 MCU
Zilog
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
1
28
Z86U18
SOIC
14
15
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
1
Pin assignments to be determined.
Figure 5. 28-pin SOIC Assignments
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
1
28
Z86U18
PDIP
14
15
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
Pin assignments to be determined.
Figure 6. 28-pin PDIP Assignments
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Z86U18
USB Device Controller with CMOS Z86K15 MCU
Zilog
ABSOLUTE MAXIMUM RATINGS
Symbol
Description
Min
Max
Units
VCC
Supply Voltage*
Ð0.3
+7.0
V
TSTG
Storage Temp
Ð65
+150
°C
TA
Oper Ambient Temp
0
+105
°C
Note: * Voltage on all pins with respect to GND.
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at
any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
STANDARD TEST CONDITIONS
The characteristics listed here apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Figure 7).
From Output
Under Test
150 pF
Figure 7. Test Load Diagram
CAPACITANCE
TA = 25°C; VCC = GND = 0V; f = 1.0 MHz; unmeasured pins returned to GND.
Parameter
Input Capacitance
Output Capacitance
I/O Capacitance
Max
12 pF
12 pF
12 pF
Note: Frequency tolerance ±10%
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Z86U18
USB Device Controller with CMOS Z86K15 MCU
Zilog
DC CHARACTERISTICS
VCC = 4.0V to 5.5V @ 0°C to +70°C
Sym
Parameter
VCH
1
Min
Max
Clock Input High Voltage
0.7 VCC
VCC + 0.3V
V
Driven by External Clock Generator
VCL
Clock Input Low Voltage
GND Ð0.3
0.2 VCC
V
Driven by External Clock Generator
VIH
Input High Voltage
0.7 VCC
VCC + 0.3
V
VIL
Input Low Voltage
GND Ð0.3
0.2 VCC
V
VOH
Output High Voltage
VCC Ð0.4
V
IOH = Ð2.0 mA
VOH
Output High Voltage
VCC Ð0.6
V
IOH = Ð2.0 mA (see note 1 below.)
VOL
Output Low Voltage
.4
V
IOL= 4 mA
VOL
Output Low Voltage
.8
V
IOL= 4 mA (see note 1 below.)
IOL
Output Low
10
20
mA
VOL= VCC Ð2.2 V (see note 1 below.)
IOL
Output Leakage
Ð1
1
mA
VIN = 0V, 5.25V
ICC
VCC Supply Current
12
mA
@ 6.0 MHz
ICC1
Halt Mode Current
TBD
mA
@ 6.0 MHz
ICC2
Stop Mode Current
10
mA
Rp
Pull Up Resistor
14.04
K ohm
Rp
Pull Up Resistor (P26-P25)
1.8
3
K ohm
3.0
D- > D+
3.6
D+ > D-
V
mV
VUSB Voltage Regulator Output
D+,D- Differential Signaling
6.76
Unit Condition
@ > 200mV Difference (see note 2
below)
Notes:
1. Ports P37-P34. These may be used for LEDs or as general-purpose outputs requiring high sink current.
2. Except for SE0 for EOP and RESET (See 7.1.4 of USB Specification).
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Z86U18
USB Device Controller with CMOS Z86K15 MCU
Zilog
AC ELECTRICAL CHARACTERISTICS
Additional Timing Diagram
1
3
Clock
2
7
2
3
7
TIN
4
5
6
IRQN
8
9
Clock
Setup
11
Stop
Mode
Recovery
Source
10
Figure 8. Additional Timing
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Z86U18
USB Device Controller with CMOS Z86K15 MCU
Zilog
AC ELECTRICAL CHARACTERISTICS
Additional Timing Table
TA=0°C to +70°C
5.0V, 6 MHz
Min
Max
No
Symbol
Parameter
1
2
3
4
5
6
7
8
9
10
11
12
13
TpC
TrC,TfC
TwC
TwTinL
TwTinH
TpTin
TrTin
TwIL
TwIH
Twsm
Tost
Twdt
D+, D-
Input Clock Period
Clock Input Rise & Fall Times
Input Clock Width
Timer Input Low Width
Timer Input High Width
Timer Input Period
Timer Input Rise & Fall Timer
Int. Request Low Time
Int. Request Input High Time
Stop-Mode Recovery Width Spec
Oscillator Start-up Time
Watch-Dog Timer
Differential Rise and Fall Times
150
Units
Notes
250
25
ns
ns
ns
ns
100
ns
ns
1
1
1
1
1
1
1
1,2
1,2
37
70
2.5TpC
4TpC
70
3TpC
5TpC
5TpC
3,0
70
1
300
ns
ns
ms
nS
3
Notes:
1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0.
2. Interrupt request through Port 3 (P33-P31)
3. See USB Specification 7.1.1.2
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Z86U18
USB Device Controller with CMOS Z86K15 MCU
Zilog
PIN FUNCTIONS
XTAL 1,2 for ceramic resonator operation (6 MHz).
Z86UXX
Port 0 (P07-P00) and Port 1 (P17-P10). Port 0 and Port
1 are 8-bit open drain output (Figure 9).
8
(Open-Drain
Output)
Port 0 and Port 1
Pad
Output
Figure 9. Port 0 and Port 1 ConÞguration
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Z86U18
USB Device Controller with CMOS Z86K15 MCU
Zilog
Port 2 (P27-P20). Port 2 is an 8-bit CMOS-compatible
Port with 4-bit input, 4-bit programmable I/O (Figure 10).
P20-P24 have 10.4 K (±35 percent) pull-up resistors. P25
and P26 have 2.4 K (±25 percent) pull-up resistor.
1
Input
4
Z86UXX
I/O
VCC
(a) Ports P20-P23
Input
10.4 K
Pad
VCC
10.4 kOhm
OEN
Open-Drain
(b) Port P24
Pad
OUT
Input
IN
VCC
2.4K
OEN
Open-Drain
(c) Ports P25-P26
Pad
OUT
Input
IN
Figure 10. Port 2 ConÞguration
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Z86U18
USB Device Controller with CMOS Z86K15 MCU
Zilog
PIN FUNCTIONS (Continued)
Port 3 (P37-P30). Port 3 is an 8-bit, CMOS-compatible
four-fixed-input (P33-P30) and four-fixed-output (P37P34) I/O port. Port 3 inputs have 10.4 Kohm pull-up resistors and outputs are capable of directly driving LED.
Port 3 is configured under software control to provide the
following control functions: three external interrupt request
signals (IRQ0-IRQ2)..
Port 3
Z86U18
(a) Port 3 P34-P37
Output
Pad
(b) Port 3 P30-P33
10.4 Kohms
Input
Pad
Figure 11. Port 3 ConÞguration
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Z86U18
USB Device Controller with CMOS Z86K15 MCU
Zilog
FUNCTIONAL DESCRIPTION
Program Memory. The 16-bit program counter addresses
4 KB of program memory space at internal locations (Figure 12).
D7 D6 D5 D4 D3 D2 D1 D0
The first 12 bytes of program memory are reserved for the
interrupt vectors. These locations have five 16-bit vectors
that correspond to the six available interrupts.
Byte 12 to byte 4095 consists of on-chip, mask programmed ROM. Addresses 4096 and greater are reserved. The 4 KB program memory is mask programmable.
65535
Reserved
4096
4095
On-Chip
ROM
Location of
First Byte of
Instruction
Executed 12
After RESET
11
Reserved
10
Reserved
9
(T0)
8
Interrupt
Vector
(Lower Byte)
Interrupt
Vector
(Upper Byte)
7
(USB)
1
R253 RP
Bank Pointer
Default setting after RESET = 00000000
Working Register
Group
Figure 13. Register Pointer Register
Register File. The register file consists of four I/O port registers, 188 general-purpose registers and 11 control and
status registers (R3-R0, R4-191, and R255-R240, respectively). The instructions can access registers directly or indirectly through an 8-bit address field. This allows short, 4bit register addressing using the Register Pointer (Figure
13). In the 4-bit mode, the register file is divided into12
working-register groups, each occupying 16 continuous locations. The Register Pointer addresses the starting location of the active working register group.
Note: To use the Bank Pointer: The instruction SRP 01
must be used to access the USB registers in the Expanded
Register File Space. These 8 registers (as defined on pp.
21-24) are available along with those registers from 10h to
BFh. Setting SRP 0 will allow access to the register locations 0 to BFh, including the I/O port registers at 0-3.
6
5
P31
4
(IRQ2)
3
P33
2
(IRQ1)
1
P32
0
(IRQ0)
Figure 12. Program Memory Map
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Z86U18
USB Device Controller with CMOS Z86K15 MCU
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Z8 STANDARD CONTROL REGISTERS
REGISTER POINTER
7
6
5
4
3
2
Working Register
Group Pointer
1
REGISTER
0
Bank Pointer
*
*
Z8 Reg. File
%FF
%FO
Not
available
%BF
% FF
SPL
% FE
Reserved
% FD
RP
% FC
FLAGS
% FB
IMR
% FA
IRQ
% F9
IPR
% F8
Reserved
% F7
P3M
% F6
P2M
% F5
PRE0
% F4
T0
% F3
Reserved
% F2
Reserved
% F1
TMR
% F0
Reserved
Usb Register
Bank 1
%0F
%00
REG. GROUP (0)
PORT REGISTERS
Note:
* Will not be reset with a
STOP Mode Recovery
% (0) 03
P3
% (0) 02
P2
% (0) 01
P1
% (0) 00
P0
Figure 14. Register File Architecture
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Z86U18
USB Device Controller with CMOS Z86K15 MCU
Zilog
Counter/Timers. There is an 8-bit programmable
counter/timer (T0) driven by its own 6-bit programmable
prescaler (Figure 15).
The 6-bit prescalers can divide the input frequency of the
clock source by any integer number from 1 to 64. The prescaler drives the counter, which decrements the counter
value (1 to 256) on the prescaler overflow. When both the
counter and prescaler reach the end of count, a timer interrupt request, IRQ4, is generated.
The counter can be programmed to start, stop, restart to
continue, or restart from the initial value. The counter can
also be programmed to stop upon reaching zero (single
pass mode) or to automatically reload the initial value and
continue counting (modulo-n continuous mode) The
counter, but not the prescaler, is read at any time without
disturbing its value or count mode.
Internal Data Bus
Write
OSC
¸4
Write
Read
PRE0
Initial Value
Register
T0
Initial Value
Register
6-Bit
Down
Counter
8-bit
Down
Counter
T0
Current Value
Register
IRQ4
Figure 15. Counter/Timers Block Diagram
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Z86U18
USB Device Controller with CMOS Z86K15 MCU
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Watch-Dog Timer. The Watch-Dog Timer is activated automatically by power-on
Watch-Dog Timer Mode Register (WDTMR). The WDTMR is: WDT (ms) » 50 ms.
WDT Hot bit. Bit 7 of the Interrupt Request register (IRQ
register FAH) determines whether a hot start or cold start
occurred. A cold start is defined as reset occurring from
the power-up of the Z86U18 (the default upon power-up is
0). A hot start occurs when a WDT time-out has occurred
(bit 7 is set to 1). Bit 7 of the IRQ register is read-only and
is automatically reset to 0 when accessed.
WDT During HALT (D5-R250). This bit determines whether or not the WDT is active during HALT Mode. The default
is 1, and a 1 indicates active during HALT.
VCC
18 Tpc
Internal
Reset
Reset
Delay
POR
* Reset Delay = POR 98.57 ms at 6 MHz.
Figure 16. WDT Turn-On Timing After Reset
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Z86U18
USB Device Controller with CMOS Z86K15 MCU
Zilog
Interrupts. The Z86U18 has five different interrupts from
three different groups. These interrupts are maskable and
prioritized (Figure 17). The five sources are divided as follows: three sources are claimed by Port 3 lines P33-P31,
one is claimed by the counter/timer, and the other is
claimed by the USB interface. The Interrupt Masked Register globally or individually enables or disables the six interrupts requests.
To accommodate polled interrupt systems, interrupt inputs
are masked and the interrupt request register is polled to
determine which of the interrupt request needs service.
EMI. Lower EMI on the Z86U18 is achieved through circuit
modifications. The internal divide-by-two circuit has been
removed to further reduce EMI.
The Z86U18 also accepts external clock from Pin 33 (40Pin DIP).
IRQ0-IRQ4
5
IRQ
XTAL1 (in)
XTAL2 (out)
IMR
5
Global
Interrupt
Enable
IPR
XTAL1
Priority
Logic
External Clock
Vector Select
Figure 18. Oscillator ConÞguration
Figure 17. Interrupt Block Diagram
When more than one interrupt is pending, priorities are resolved by a programmable priority encoder that is controlled by the Interrupt Priority register. All interrupts are
vectored through locations in the program memory. When
an interrupt machine cycle is activated an interrupt request
is granted. Thus, this disables all of the subsequent interrupts, saves the Program Counter and status flags, and
then branches to the program memory vector location reserved for that interrupt. This memory location and the
next byte contain the 16-bit address of the interrupt service
routine for that particular interrupt request.
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Z86U18
USB Device Controller with CMOS Z86K15 MCU
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Power-On-Reset (POR). A timer circuit is triggered by the
system oscillator and is used for the Power-On Reset
(POR) timer function. The POR time allows VCC and the oscillator circuit to stabilize before instruction execution begins. POR period is defined as:
POR (ms) = 98 ms
The POR timer circuit is a one-shot timer triggered by lower fail to Power OK status. The POR time is a nominal 100
ms at 6 MHz. The POR time is bypassed after Stop-Mode
Recovery.
HALT. HALT turns off the internal CPU clock, but not the
oscillator. The counter/timer and external interrupts IRQ0,
IRQ1, IRQ2, and IRQ3 remain active. The Z86U18 recovers by interrupts, either externally or internally.
USB Reset. Detection by the SIE of a reset from the Host
will cause the chip to reset. The reset will be remembered
so that the program can decide the source of the reset.
The USB Reset will act even if the chip is in the STOP
mode.
18
STOP. This instruction turns off the internal clock and external crystal oscillation. It reduces the standby current to
less than 10 mA. The STOP Mode is terminated by an interrupt. An interrupt from any of the active (enabled) interrupts will remove the chip from the STOP Mode ( Ports 3133 and the USB reset). The timer can not do this as the
clock is stopped. This causes the processor to restart the
application program at the address or the vector of the interrupt and continue the program at the end of the interrupt
service routine. In order to enter STOP (or HALT) Mode, it
is necessary to first flush the instruction pipeline to avoid
suspending execution in mid-instruction. To do this, the
user must execute a NOP (opcode=FFH) immediately before the appropriate sleep instruction, such as:
FF
6F
NOP
STOP
FF
7F
NOP
HALT
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; clear the pipeline
; enter STOP Mode
or
; clear the pipeline
; enter HALT Mode
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Z86U18
USB Device Controller with CMOS Z86K15 MCU
Zilog
Z8 CONTROL REGISTER DIAGRAMS
R241 TMR
1
R247 P3M
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2
D1
D0
0 = No Function
1 = Load T0
0
1
0 = Disable T0 Count
1 = Enable T0 Count
Reserved (Must be 0)
Port 2 Open-Drain
Port 2 Push-Pull
Reserved (Must be 0)
Figure 23. Port 2 Open Drain Register
(F7H: Write Only)
Figure 19. Timer Mode Register
(F1H: Read/Write)
R249 IPR
R244 T0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3
D2 D1 D0
Interrupt Group Priority
Reserved = 000
C > A > B = 001
A > B > C = 010
A > C > B = 011
B > C > A = 100
C > B > A = 101
B > A > C = 110
Reserved = 111
T0 Initial Value
(When Written)
(Range 1-256 Decimal
01-00 HEX)
T0 Current Value
(When READ)
IRQ1, IRQ4 Priority (Group C)
0 = IRQ1 > IRQ4
1 = IRQ4 > IRQ1
IRQ0, IRQ2 Priority (Group B)
0 = IRQ2 > IRQ0
1 = IRQ0 > IRQ2
Figure 20. Counter/Timer 0 Register
(F4H: Read/Write)
R245 PRE0
Reserved (Must be 0)
D7 D6 D5 D4 D3 D2 D1 D0
Figure 24. Interrupt Priority Register
(F9H: Write Only)
Count Mode
0 = T0 Single Pass
1 = T0 Modulo N
Reserved (Must be 0)
Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)
R250 IRQ
D7 D6 D5 D4 D3 D2
IRQ0 = P32 Input
IRQ1 = P33 Input
IRQ2 = P31 Input
IRQ3 = USB
IRQ4 = T0
Figure 21. Prescaler 0 Register
(F5H: Write Only)
WDT During HALT
0 OFF *
1 ON
R246 P2M
D7 D6 D5 D4 D3 D2 D1 D0
Stop Flag
0 POR/WDT*
1 Stop Recovery
Reserved
P24-P27 I/O Definition
0 Defines Bit as OUTPUT
1 Defines Bit as INPUT
Figure 22. Port 2 Mode Register
(F6H: Write Only)
DS97KEY0102
D1 D0
* On RESET
WDT Hot Bit (Read Only)
0 POR*
1 WDT Timeout
Figure 25. Interrupt Request Register
(FAH: Read/Write)
PRELIMINARY
19
Z86U18
USB Device Controller with CMOS Z86K15 MCU
Zilog
Z8 CONTROL REGISTER DIAGRAMS (Continued)
R251 IMR
R255 SPL
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1 Enables IRQ5-IRQ0
(D0 = IRQ0)
Stack Pointer Lower
Byte (SP0-SP7)
Reserved (Must be 0)
1=Global Interrupt Enable
0=Global Interrupt Disable
Figure 29. Stack Pointer
(FFH: Read/Write)
Figure 26. Interrupt Mask Register
(FBH: Read/Write)
R252 Flags
D7 D6 D5 D4 D3 D2 D1 D0
User Flag F1
User Flag F2
Half Carry Flag
Decimal Adjust Flag
Overflow Flag
Sign Flag
Zero Flag
Carry Flag
Figure 27. Flag Register
(FCH: Read/Write)
R253 RP
D7 D6 D5 D4 D3
D2 D1 D0
Bank Pointer
r4
r5
r6
Register
Pointer
r7
Figure 28. Register Pointer
(FDH: Read/Write)
20
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Z86U18
USB Device Controller with CMOS Z86K15 MCU
Zilog
USB REGISTERS
Table 1. Address Offset
Located @ 01 in Expanded Register Space
Register
Function Address
Endpoint 0 CSR
Endpoint 0 Write Count
Endpoint FIFO
IN CSR
IN FIFO
Interrupt Register
Miscellaneous Register
Address
0
1
2
3
4
5
6
7
1
Reset Value
00
00
00
00
40
00
00
00
REGISTER DESCRIPTIONS
000h
D7
D6 D5
D4 D3 D2
D1 D0
Function Address
Not Used
Figure 30. Function Address Register
Bit
mC
SIE
Description
6:0
R/W
R
Upon receiving a SET_Address descriptor, the microcontroller writes this
register with the address received from the host.
DS97KEY0102
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21
Z86U18
USB Device Controller with CMOS Z86K15 MCU
Zilog
REGISTER DESCRIPTIONS (Continued)
001h
D7
D6 D5
D4 D3 D2
D1 D0
Out _pkt _rdy
In _pkt _rdy
Force Stall
Data End
Setup End
Send Stall
Serviced Out Packet Ready
Serviced Setup End
Figure 31. Endpoint 0 CS Register
Bit No
Bit Description
mC
SIE
Description
7
6
W
W
R
R
5
Serviced Setup End
Serviced Outpacket
Ready
Send STALL
W
R
4
Setup End
R
W
3
Data End
W
R
2
Force STALL
R
W
1
In Packet Ready
W
R
0
Out Packet Ready
R
W
The microcontroller writes a 1 to this register to clear setup end bit.
The microcontroller writes a 1 to this register to clear out packet ready
bit.
If the microcontroller decodes an invalid descriptor, it writes a 1 to this
register before clearing out_pkt_rdy bit or when microcontroller decodes
a set feature or clear feature USB command from the host.
If the function receives a new setup transaction before the previous one
is complete (entire length of data is transferred), this bit is set. Upon
seeing this bit set, the microcontroller should abort the current set
operation.
During the data phase of a control transfer after the microcontroller has
received/sent the last data as speciÞed in the setup phase, it sets this
bit.
The SIE writes to this register, when it encounters a protocol violation,
and issues a STALL handshake to the current control transfer.
During the data phase, after the microcontroller has Þlled the data, it sets
this bit. It is cleared by SIE upon successful transmittion of data.
The SIE sets this bit after writing data to the FIFO. The microcontroller
clears this bit by writing it to Serviced Out Packet Ready bit.
002h
D7
D6 D5
D4 D3 D2
D1 D0
Write Count
00000
Figure 32. Endpoint 0 Write Count Register
Bit
mC
SIE
Description
2:0
R
W
The contents indicates the number of bytes in the FIFO.
22
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DS97KEY0102
Z86U18
USB Device Controller with CMOS Z86K15 MCU
Zilog
003h
D7
D6 D5
D4 D3 D2
1
D1 D0
FIFO Data
Figure 33. Endpoint 0 FIFO Register
Bit
mC
SIE
Description
7:0
R/W
R/W
This is the Endpoint 0 FIFO data register.
004h
D7
D6 D5
D4 D3 D2
D1 D0
In_pkt _rdy
Force Stall
IN MAXP
000
Figure 34. IN CS Register
/Bit No Bit Description mC
SIE
Description
4:2
IN MAXP
W
R
1
Force STALL
R/W
W
0
In Packet Ready W
Before setting in_pkt_rdy, the microcontroller writes the maximum packet
size to these bits. The default value = 8 Bytes.
The SIE writes this register, when it encounters a protocol violation, and
issues a STALL handshake to the current transfer. The microcontroller sets
this bit, when it receives a SET_FEATURE (ENDPOINT_STALL), and clears
it, when it receives a CLEAR_FEATURE (ENDPOINT_STALL).
After the microcontroller has Þlled the data, it sets this bit. It is cleared by
SIE upon successful transmission of data.
R
005h
D7
D6 D5
D4 D3 D2
D1 D0
FIFO Data
Figure 35. IN FIFO Register
Bit
mC
SIE
Description
7:0
W
R
The microcontroller writes IN data to this register.
DS97KEY0102
PRELIMINARY
23
Z86U18
USB Device Controller with CMOS Z86K15 MCU
Zilog
REGISTER DESCRIPTIONS (Continued)
006h
D7
D6 D5
D4 D3 D2
D1 D0
Endpoint 0 Interrupt
IN Endpoint Interrupt
Suspend Interrupt
Resume Interrupt
00000
Figure 36. Interrupt Register
Bit No Bit Description
mC
SIE
Description
The ßag is sent on the Host signal to resume operations.
The bit is set when theSuspend signaling is received from the host.
This bit is set upon:
1) clearing in_pkt_ rdy
2) setting Force STALL.
This bit set by SIE upon:
1) setting out_pkt_rdy
2) clearing in_pkt_rdy
3) setting Force STALL
4) clearing data_end
5) setting data_end
3
2
1
Resume Interupt
R
Suspend Interrupt
R
IN Endpoint Interrupt R
W
W
W
0
Endpoint 0 Interrupt
W
R
007h
D7
D6 D5
D4 D3 D2
D1 D0
Suspend
Send Resume
Interrupt Mask Bits
000
Figure 37. Misc. Register
Bit No Bit Description
mC
SIE
Description
4:2
Interrupt Mask Bits
R/W
R
1
Send Resume
W
R
0
Suspend
R/W
W
This has bit correspondence to the interrupt register. A value of 1, implies
that particular interrupt is disabled.
The microcontroller writes a 1 to this bit, while in suspend mode, and
wants to start a resume sequence after the clocks are running. This bit is
set high for a duration of at least 10 ms by microcontroller.
This bit is set by the SIE when, the microcontroller is to enter suspend
mode. The microcontroller clears this bit after Þnishing resume signaling,
or after it receives a resume out interrupt, and the clocks have started.
24
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Zilog
Z86U18
USB Device Controller with CMOS Z86K15 MCU
PACKAGE INFORMATION
1
Figure 38. 44-Pin QFP Package Diagram
Figure 39. 28-Pin SOIC
DS97KEY0102
PRELIMINARY
25
Z86U18
USB Device Controller with CMOS Z86K15 MCU
Zilog
Figure 40. 28-Pin PDIP
Figure 41. 44-Pin PLCC
26
PRELIMINARY
DS97KEY0102
Zilog
Z86U18
USB Device Controller with CMOS Z86K15 MCU
1
Figure 42. 40-Pin DIP
DS97KEY0102
PRELIMINARY
27
Z86U18
USB Device Controller with CMOS Z86K15 MCU
Zilog
ORDERING INFORMATION
6 MHz
6 MHz
6 MHz
6 MHz
6 MHz
40-Pin DIP
44-Pin PLCC
44-PIN QFP
28-Pin DIP
28-Pin SOIC
Z86U18PSC
Z86U18VSC
Z86U18FSC
Z86U18PSC
Z86U18SSC
For fast results, contact your Zilog sales office for assistance in ordering the part desired.
CODES
Package
P = Plastic DIP
V = Plastic Leaded Chip Carrier
F = Quad Flat Pack
Environment
C = Plastic Standard
Temperature
S = 0°C to +70°C
Speed
06 = 6 MHz
Example:
Z
86U18
05 P S C
is a Z86U18, 6 MHz, DIP, 0°C to +70°C, Plastic Standard Flow
Environmental Flow
Temperature
Package
Speed
Product Number
Zilog Prefix
© 1997 by Zilog, Inc. All rights reserved. No part of this
document may be copied or reproduced in any form or by
any means without the prior written consent of Zilog, Inc.
The information in this document is subject to change
without notice. Devices sold by Zilog, Inc. are covered by
warranty and patent indemnification provisions appearing
in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc.
makes no warranty, express, statutory, implied or by
description, regarding the information set forth herein or
regarding the freedom of the described devices from
intellectual property infringement. Zilog, Inc. makes no
warranty of merchantability or fitness for any purpose.
Zilog, Inc. shall not be responsible for any errors that may
appear in this document. Zilog, Inc. makes no commitment
to update or keep current the information contained in this
document.
28
ZilogÕs products are not authorized for use as critical
components in life support devices or systems unless a
specific written agreement pertaining to such intended use
is executed between the customer and Zilog prior to use.
Life support devices or systems are those which are
intended for surgical implantation into the body, or which
sustains life whose failure to perform, when properly used
in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in
significant injury to the user.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
FAX 408 370-8056
Internet: http://www.zilog.com
PRELIMINARY
DS97KEY0102
Zilog
Z86U18
USB Device Controller with CMOS Z86K15 MCU
1
DS97KEY0102
PRELIMINARY
29
Z86U18
USB Device Controller with CMOS Z86K15 MCU
30
PRELIMINARY
Zilog
DS97KEY0102