PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION Z89302/04/06 1 DIGITAL TELEVISION CONTROLLER FEATURES Device ROM (KB) RAM* (Bytes) Speed MHz Z89302 Z89304 Z89306 24 16 12 640 640 640 12 12 12 ■ 0°C to +70°C Temperature Range ■ Fully Customized Character Set ■ Character-Control and Closed-Caption Modes ■ Keypad User Control ■ TV Tuner Serial Interface ■ Direct Video Signals Note: * General-Purpose ■ 40-Pin DIP Packages ■ 4.75- to 5.25-Volt Operating Range GENERAL DESCRIPTION The Z89302/04/06 Digital Television Controllers are designed to provide complete audio and video control of television receivers, video recorders, and advanced onscreen display facilities. The Television Controllers feature a Z89C00 RISC processor core that controls the on-board peripheral functions and registers using the standard processor instruction set. Character attributes can be controlled through two modes: the on-screen display Character-Control Mode and the Closed-Caption Mode. The Character-Control Mode provides access to the full set of attribute controls, allowing the modification of attributes on a character-by-character basis. The insertion of control characters permits direction of other character attributes. The fully customized 512 character set, formatted in two 256 character banks, can be displayed with a host of display attributes that include underlining, italics, blinking, eight foreground/background colors, character position offset delay, and background transparency. CP96TEL1803 (9/96) Serial interfacing with the television tuner is provided through the tuner serial port. Other serial devices, such as digital channel tuning adjustments, may be accessed through the industry-standard I2C port. User control can be monitored through the keypad scanning port, or the 16-bit remote control capture register. Receiver functions such as color and volume can be directly controlled by eight 8-bit pulse width modulated ports. The Z89302/04/06 has two internal 12 MHz VCOs that are referenced to a 32 kHz internal oscillator to provide the system clock. In Sleep Mode, the controller uses the 32 kHz clock for the system clock to reduce power consumption. The processor can be suspended by placing it into STOP Mode when main power is not available for low-power consumption. 1 Z89302/04/06 Digital Television Controller PRELIMINARY GENERAL DESCRIPTION (Continued) PWM Capture IRIN PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 PWM8 PWM9 ADC Port 17 Port 00 ADC0 ADC1 ADC2 ADC3 Port1 Port 0 Port 00 Port 01 Port 02 Port 03 Port 04 Port 05 Port 06 Port 07 Port 08 Port 09 Port 0A Port 0B Port 0C Port 0D Port 0E Port 0F Port 10 Port 11 Port 12 Port 13 Port 14 Port 15 Port 16 Port 17 Port 18 Port 19 Note: Dotted pin functions not available on 40-pin device. I2C Control XTAL1 XTAL2 LPF HSYNC VSYNC /Reset Register Addr/Data Port 01/11 SCD Port 02/12 OSD V1 V2 V3 BLANK HALFBLNK CPU RAM 640 x 16 SCL ROM Addr Data ROM Data ROM 12K x 16 16K x 16 24K x 16 Figure 1. Z8930X Functional Block Diagram 2 Port0F Address Note: Z89306 has 12K words of ROM. Z89304 has 16K. Z89302 has 24K. Z89302/04/06 Digital Television Controller PRELIMINARY PIN DESCRIPTION PWM9 1 40 PWM6 IRIN 2 39 PWM5 Port 18/G<0> 3 38 PWM4 Port 00/ADC2 4 37 PWM3 Port 01/I2SSC 5 36 PWM2 Port 02/I2SSD 6 35 PWM1 Port 03 7 34 CVI/ADC0 Port 04/ADC4 8 33 LPF Port 05/ADC3 9 32 XTAL2 31 GND 30 XTAL1 Port 06/Counter 10 Z89302 Z89304 Z89306 40-Pin DIP Port 07/C Sync 11 Port 08/R<1> 12 29 VCC Port 09 13 28 /Reset Port 10/R<0> 14 27 Port 17/ADC1 Port 11/I2MSC 15 26 VBlank Port 12/I2MSD 16 25 V1 Port 13/G<1> 17 24 V2 Port 14/B<0> 18 23 V3 Port 15/B<1> 19 22 VSync Port 16/SCLK 20 21 HSync 1 Figure 2. 40-Pin DIP Configuration 3 Z89302/04/06 Digital Television Controller PRELIMINARY PIN DESCRIPTIONS Z89302/03/06/07 Pin Name Function VCC GND IRIN ADC[5:0] +5V 0V Infrared Remote Capture Input 4-Bit Analog to Digital Converter Input 14-Bit Pulse Width Modulator Output 8-Bit Pulse Width Modulator Output Bit Programmable Input/Output Ports Bit Programmable Input/Output Ports I2C Clock I/O I2C Data I/O Crystal Oscillator Input Crystam Oscillator Output Loop Filter H_Sync V_Sync Device Reset OSD Video Output (Typically Drive B, G, and R Outputs) OSD Blank Output OSD Half Blank Output R[1:0],G[1:0], and B[1:0] Outputs of the RGB Matrix Internal Processor SCLK PWM9 PWM[8:1] Port0[F:0] Port1[9:0] SCLb SCDc XTAL1 XTAL2 LPF HSYNC VSYNC /RESET V[3:1] Blank Half Blankd RGB Digital Outputse SCLKf Direction Reset Configuration 29,– 31,– 2 –,9,8,4,27,34 I nAI PWR– PWR– I I 1 OD/Oa O –,–,40,39,38 OD/Oa O –,–,–,–,–,–,13,12,11,10,9,8,7,6,5,4 B I –,3,27,20,19,18,17,16,15,14 B I 5 or 15 6 or 16 30 32 33 21 22 28 23,24,25 BOD BOD AI AO AB B B I O I O O I I I O 26 – 19,18,17,14,12,3 O O O 40-Pin, Z89302/04/06 O Notes: a) Port19 is not available on the 40-pin DIP Version, Revision D is Push-Pull. b) SCL I/O pin is shared with Port01 or Port11 c) SCD I/O pin is shared with Port02 or Port12 d) Half Blank output is a function shared with Port0F. Half Blank output is not available on the 40-pin DIP version. e) Digital RGB outputs and the internal SCLK are shared with Port1[5:0]. f) Internal processor SCLK is shared with Port16. 4 O I Z89302/04/06 Digital Television Controller PRELIMINARY ABSOLUTE MAXIMUM RATINGS Symbol Parameter Min Max Units 0 7 V 1 Conditions VCC Power Supply Voltage VID Input Voltage –0.3 VCC +0.3 V Digital Inputs VIA Input Voltage –0.3 VCC +0.3 V Analog Inputs (A/D0-A/D4) VO Output Voltage –0.3 VCC +0.3 V All Push-Pull Digital Output VO Output Voltage –0.3 VCC +0.3 V IOH IOH Output Current High Output Current High –10 –100 mA mA Open-Drain/Push-Pull PWM Outputs (PWM1-PWM8) One Pin All Pins IOL IOL TA Output Current Low Output Current Low Operating Temperature 0 20 200 70 mA mA °C TA Storage Temperature –65 150 °C One Pin All Pins Note: Revision D and later have push-pull PWM outputs. DC CHARACTERISTICS TA = 0°C to + 70°C; VCC = 4.5 V to + 5.5 V; FOSC = 32.768 kHz Symbol Parameter Min Max Typical Units VIL Input Voltage Low 0 0.2 VCC 0.4 V VIH Input Voltage High 0.6 VCC VCC 3.6 V VPU Max. Pull-Up Voltage 5 VOL Output Voltage Low 0.4 VOL VXL Output Voltage High Input Voltage XTAL1 Low VCC–0.9 0.3 VCC VXH Input Voltage XTAL1 High VCC–2.0 VHY IIR IIL Schmitt Hysteresis Reset Input Current Input Leakage ICC ICC1E ICC1 ICC2 IADC IADC Conditions V All Pins 0.16 V @ IOL = 1 mA 4.75 1.0 V V @ IOL = 0.75 mA External Clock 3.5 V Generator Driven 0.75 150 3.0 0.5 90 0.01 V mA mA On XTAL1 Input Pin VRL = 0V @ 0 V and VCC Supply Current Supply Current of the OTP 100 700 60 300 mA mA Sleep Mode @ 32 kHz Supply Current Supply Current Input Current Input Current 300 10 0.5 10 100 5 mA mA mA mA Sleep Mode @ 32 kHz Sleep Mode C Revision D Revision 3.0 –3.0 5 Z89302/04/06 Digital Television Controller PRELIMINARY V1,V2,V3 ANALOG OUTPUT Condition 4.75 V 5.25 V 11 10 3.6 – 4.4 4.0 – 5.0 01 00 VII 79% of VII ± 5% 50% of VII ± 5% 0.0 – 0.8V Notes: Maximum Variance Between V1, V2, V3 is 100 mV Settling Time 70% of DC Level, 10pF Load <50n Sec XTAL1 47 pF 32.768K 10 MOhm XTAL2 27 K 68 pF 32K Oscillator Recomended Circuit Figure 3. 32K Oscillator Recommended Circuit Z893XX 510 W 0.1 mF 10 mF Figure 4. Low Pass Filter 6 Z89302/04/06 Digital Television Controller PRELIMINARY AC CHARACTERISTICS TA = 0°C to + 70°C; VCC = 4.5 V to 5.5 V; FOSC = 32.768 kHz Symbol Parameter TPC Input Clock Period TRC,TFC Clock Input Rise and Fall TDPOR Power-On Reset Delay 1 Min Max Typical Units 16 100 32 ms 12 ms 1.2 s Typical Units 0.8 AC CHARACTERISTICS TA = 0°C to + 70°C; VCC = 4.5 V to 5.5 V; FOSC = 32.768 kHz Symbol TWRES TDHS TDVS TDES Parameter Power-On Reset Min. Width H_Sync Incoming Signal Width V_Sync Incoming Signal Width Time Delay Between Leading Edge of V_Sync and H_Sync on Even Field Time Delay Between Leading Edge of H_Sync in Odd Field H_Sync/V_Sync Edge Width TDOS TWHVS Min. Max. 5.5 0.15 –12 5TPC 12.5 1.5 +12 11 1.0 0 ms ms ms ms 20 44 32 ms 2.0 0.5 ms 2 2 Note: All timing of the I C bus interface is defined by related specifications of the I C bus interface. ANALOG INPUT ADC0 ADC1 Step Min. Max Step Min. Max 1 15 1.45 Step 1 + 0.468 1.55 Step 1 + 0.532 1 15 0.2 Step_1 + 4.95 0.4 Step_1 + 5.15 Note: VCC = 5V 7 Z89302/04/06 Digital Television Controller PRELIMINARY Development Projects: Customer is cautioned that while reasonable efforts will be employed to meet performance objectives and milestone dates, development is subject to unanticipated problems Pre-Characterization Product: The product represented by this CPS is newly introduced and Zilog has not completed the full characterization of the product. The CPS states what Zilog knows about this product at this time, but additional features or nonconformance with some aspects of the CPS may be found, © 1996 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. 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