ZILOG Z89390 CPS DC-9030-01 P R E L I M I N A R Y PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION Z89390 16-BIT DIGITAL SIGNAL PROCESSOR GENERAL DESCRIPTION The Z89390 is a CMOS Digital Signal Processor (DSP). Single-cycle instruction execution and a Harvard bus structure promotes efficient algorithm execution. The processor contains 512 word data RAM and 64K word of external program address space is accessible. Six register pointers provide circular buffering capabilities and dual operand fetching. Three vectored interrupts are complemented by a six level stack. The CODEC interface enables high-speed transfer rates to accommodate digital audio and voice data. A dedicated Counter/Timer provides the necessary timing signals for the CODEC interface. An additional 13-bit timer is available for general-purpose use. Development tools for the IBM PC include a relocatable assembler, a linker loader debugger. Notes: All Signals with a preceding front slash, "/", are active Low, e.g., B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Circuit Device Power Ground VCC GND VSS VDD The Z89390 is optimized to accommodate intricate signal processing algorithms. The 20-MIP operating performance and efficient architecture provides real-time execution. Compression, filtering, frequency detection, audio, voice detection/synthesis and other available algorithms can all be accommodated. The on-board peripherals provide additional cost advantages. DC 9030-00 1 Z89390 CPS DC-9030-01 P R E L I M I N A R Y ZILOG GENERAL DESCRIPTION (Continued) External Program ROM PD15-PD0 PA15-PA0 16 16 PA PD 16 Register Pointer 0-2 256 Word RAM 0 256 Word RAM 1 16 PC Register Pointer 4-6 Instruction Register 16 EXT0-15 D Bus 16-Bit Bus 16-bit I/O Port Switch S-Bus X Y Stack Switch Ready WAIT, RD/WR, /OS 3 EA0-2 16 x16 Multiplier EXT5-1 EXT5-2 24-bit P 24-Bit Bus MUX P Bus EXT7-1 EXT7-2 A CODEC Interface EXT4 Shifter B RXD TXD SCLK FS0 FS1 EXT6-1 EXT6-2 24 Status (5) ALU 13-Bit Timer Interrupt 3 /INTO-2 /RESET ACC 2 User Port UI0-1 2 UO0-1 Note: EXT5, EXT6, and INTERRUPT1 are used for the CODEC Interface. EXT4 and INTERRUPT2 are used for the 13-bit timer. Z89391 Functional Block Diagram 2 DC 9030-00 Z89390 CPS DC-9030-01 P R E L I M I N A R Y ZILOG VCC PA0 VSS EXT0 PA1 EXT1 PA2 84 EXT2 1 PA3 VSS 11 VSS RXD EXT12 PA4 EXT13 PA5 EXT14 PA6 VSS PA7 EXT15 N/C PIN DESCRIPTION 75 74 12 VSS PD15 EXT3 FS1 PA8 EXT4 PD14 PA9 UO1 VSSP PD13 EXT5 UO0 PA10 PD12 EXT6 INT0 FS0 PA11 Z89390 84-Pin PLCC EXT7 HALT TXD PD11 PA12 CLK EXT8 /D5 PA13 PD10 EXT9 VDDP VSS PD9 PA14 EA2 EXT10 PD8 PA15 EA1 54 53 EA0 PD7 PD6 /RESET PD5 PD4 WAIT VDD RD//WR SCLK UI1 PD3 INT1 PD2 PD1 INT2 PD0 42 43 EXT11 VSS 33 VDD VCC 32 UI0 VCC 84-Pin PLCC Pin Assignments DC 9030-00 3 Z89390 CPS DC-9030-01 P R E L I M I N A R Y ZILOG ABSOLUTE MAXIMUM RATINGS Symbol Description Min. Max. Units VCC TSTG TA Supply Voltage (*) Storage Temp Oper Ambient Temp –0.3 –65° +7.0 +150° † V C C Notes: * Voltage on all pins with respect to GND. † See Ordering Information. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended period may affect device reliability. STANDARD TEST CONDITIONS +5V The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to ground. Positive current flows into the referenced pin (Test Load). 2.1 K Ω From Output Under Test 9.1 K Ω 30 pF . Test Load Diagram DC ELECTRICAL CHARACTERISTICS (VDD= 5V ± 10%, TA = 0°C to +70°C unless otherwise specified) Symbol Parameter Condition IDD Supply Current IDC DC Power Consumption VDD = 5.25V fclock = 20 MHz VDD = 5.25V VIH VIL IL Input High Level Input Low Level Input Leakage VOH VOL IFL Output High Voltage Output Low Voltage Output Floating Leakage Current 4 Min. Max. Typical Units 80 70 mA 5 mA 2.5 IOH = –100 µA IOL = 2.0 mA 0.8 10 V V µA 0.5 5 V V µA VDD– 0.2 DC 9030-00 Z89390 CPS DC-9030-01 P R E L I M I N A R Y ZILOG AC ELECTRICAL CHARACTERISTICS (VDD = 5V 10%, TA = 0°C to +70°C unless otherwise specified) Symbol Parameter Min (ns) Clock TCY Tr Tf CPW Clock Cycle Time Clock Rise Time Clock Fall Time Clock Pulse Width 50 /DS Setup Time from CLOCK Fall /DS Hold Time from CLOCK Rise EA Setup Time to /DS Fall EA Hold Time from /DS Rise Data Read Setup Time to /DS Rise Data Read Hold Time from /DS Rise Data Write Setup Time to /DS Rise Data Write Hold Time from /DS Rise 0 4 12 4 14 6 Interrupt INTSET INTWIDTH Interrupt Setup Time to CLOCK Fall Interrupt Low Pulse Width 7 1 TCY Codec Interface SSET FSSET TXSET RXSET RXHOLD SCLK Setup Time from Clock Rise FSYNC Setup Time from SCLK Rise TXD Setup Time from SCLK Rise RXD Setup Time to SCLK Fall RXD Hold Time from SCLK Fall Reset RRISE RSET RWIDTH Reset Rise Time Reset Setup Time to CLOCK Rise Interrupt Low Pulse Width Max (ns) 2 2 23 I/O DSSET DSHOLD EASET EAHOLD RDSET RDHOLD WRSET WRHOLD 15 15 18 5 15 6 7 7 0 1000 15 2 TCY External Program Memory PASET PA Setup Time from CLOCK Rise PDSET PD Setup Time to CLOCK Rise PDHOLD PD Hold Time from CLOCK Rise 5 10 10 Wait State WSET WHOLD WAIT Setup Time to CLOCK Rise WAIT Hold Time from CLOCK Rise 23 1 Halt Setup Time to CLOCK Rise Halt Hold Time from CLOCK Rise 3 10 Halt HSET HHOLD DC 9030-00 5 Z89390 CPS DC-9030-01 P R E L I M I N A R Y ZILOG AC TIMING DIAGRAM TCY Tr Tf CLOCK CPW DSHOLD DSSET /DS EASET EA(2:0) EAHOLD Valid Address Out RD//WR RDHOLD RDSET EXT(15:0) Data In Read Timing Diagram TCY CLOCK WHOLD WSET WAIT /DS EA(2:0) Valid Address Out RD//WR EXT(15:0) Data In Read Timing Diagram Using WAIT Pin 6 DC 9030-00 P R E L I M I N A R Y ZILOG Z89390 CPS DC-9030-01 TCY CLOCK DSHOLD DSSET /DS EASET EA(2:0) EAHOLD Valid Address Out EAHOLD EASET RD//WR WRHOLD WRSET EXT(15:0) Data In Write Timing Diagram TCY CLOCK WHOLD WSET WAIT /DS EA(2:0) Valid Address Out RD//WR EXT(15:0) Data In Write Timing Diagram Using WAIT Pin DC 9030-00 7 Z89390 CPS DC-9030-01 P R E L I M I N A R Y ZILOG AC TIMING (Continued) TCY CLOCK SSET SCLK FSSET FSSET FS0, FS1 TXSET TXD 1 0 1 0 1 RXHOLD RXSET RXD 1 0 1 0 1 Codec Interface Timing Diagram 8 DC 9030-00 Z89390 CPS DC-9030-01 P R E L I M I N A R Y ZILOG AC TIMING (Continued) TCY CLOCK INTSET INT 0,1,2 INTWidth PROGRAM ADDRESS Fetch N –1 EXECUTE Fetch N Fetch N +1 Fetch Int_Addr Fetch I Execute N –1 Execute N CALL Int Routine Execute Int Routine Fetch I +1 Interrupt Timing Diagram TCY CLOCK HHOLD HSET HALT HALT Timing Diagram DC 9030-00 9 Z89390 CPS DC-9030-01 P R E L I M I N A R Y ZILOG AC TIMING (Continued) TCY CLOCK RSET RRISE /RESET RWIDTH INTERNAL RESET EXECUTE Cycle 1 Cycle 0 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Code Execution RD/WR /DS UO0-1 EA0-2 EXT0-15 Tri-Stated PA0-15 Tri-Stated Access Reset Vector RAM/ REGISTERS Intact* * The RAM and hardware registers are left intact during a warm reset. A cold reset will produce random data in these locations. The status register is set to zeroes in both cases. RESET Timing Diagram TCY CLOCK PASET PROGRAM ADDRESS Valid Valid Valid PDSET PDHOLD PROGRAM DATA Valid Valid Valid External Memory Port Timing Diagram 10 DC 9030-00 ZILOG P R E L I M I N A R Y © 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. DC 9030-00 Z89390 CPS DC-9030-01 Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056 Internet: http://www.zilog.com 11