TPD12S521 www.ti.com .................................................................................................................................................... SLVS639B – OCTOBER 2007 – REVISED APRIL 2009 SINGLE-CHIP HDMI TRANSMITTER PORT PROTECTION AND INTERFACE DEVICE FEATURES 1 • • • • • • • • • • Single-Chip ESD Solution for High-Definition Multimedia Interface (HDMI) Driver Supports HDMI 1.3 Data Rate (–3 dB Frequency > 3 GHz) 0.8-pF Capacitance for High-Speed Transition Minimized Differential Signaling (TMDS) Lines 0.05-pF Matching Capacitance Between the Differential Signal Pair Integrated Level Shifting for the Control Lines ±8-kV Contact ESD Protection on External Lines 38-Pin Thin Shrink Small-Outline Package (TSSOP) Provides Seamless Layout Option With HDMI Connector Backdrive Protection Lead-Free Package On-Chip Current Regulator With 55-mA Current Output DBT PACKAGE (TOP VIEW) 5V_SUPPLY LV_SUPPLY GND TMDS_D2+ TMDS_GND TMDS_D2– TMDS_D1+ TMDS_GND TMDS_D1– TMDS_D0+ TMDS_GND TMDS_D0– TMDS_CK+ TMDS_GND TMDS_CK– CE_REMOTE_IN DDC_CLK_IN DDC_DAT_IN HOTPLUG_DET_IN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 5V_OUT ESD_BYP GND TMDS_D2+ TMDS_GND TMDS_D2– TMDS_D1+ TMDS_GND TMDS_D1– TMDS_D0+ TMDS_GND TMDS_D0– TMDS_CK+ TMDS_GND TMDS_CK– CE_REMOTE_OUT DDC_CLK_OUT DDC_DAT_OUT HOTPLUG_DET_OUT APPLICATIONS • • • • PCs Consumer Electronics Set-Top Boxes DVDRW Players DESCRIPTION/ORDERING INFORMATION The TPD12S521 is a single-chip ESD solution for the high-definition multimedia interface (HDMI) transmitter port. In many cases, the core ICs, such as the scalar chipset, may not have robust ESD cells to sustain system-level ESD strikes. In these cases, the TPD12S521 provides the desired system-level ESD protection, such as the the IEC61000-4-2 (Level 4) ESD, by absorbing the energy associated with the ESD strike. While providing the ESD protection, the TPD12S521 adds little or no additional glitch in the high-speed differential signals (see Figure 5 and Figure 6). The high-speed transition minimized differential signaling (TMDS) lines add only 0.9-pF capacitance to the lines. In addition, the monolithic integrated circuit technology ensures that there is excellent matching between the two-signal pair of the differential line. This is a direct advantage over discrete ESD clamp solutions where variations between two different ESD clamps may significantly degrade the differential signal quality. The low-speed control lines offer voltage-level shifting to eliminate the need for an external voltage level-shifter IC. The control line ESD clamps add 3.5-pF capacitance to the control lines. The 38-pin DBT package offers seamless layout routing option to eliminate the routing glitch for the differential signal pair. The TPD12S521 provides an on-chip regulator with current output ratings of 55 mA at pin 38. This current enables HDMI receiver detection even when the receiver device is powered off. DBT package pitch (0.5 mm) matches with HDMI connector pitch. In addition, pin mapping follows the same order as the HDMI connector pin mapping. This HDMI receiver port protection and interface device is specifically designed for next-generation HDMI transmitter protection. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2009, Texas Instruments Incorporated TPD12S521 SLVS639B – OCTOBER 2007 – REVISED APRIL 2009 .................................................................................................................................................... www.ti.com ORDERING INFORMATION TA PACKAGE –40°C to 85°C (1) (2) (3) (1) (2) ORDERABLE PART NUMBER (3) TSSOP-38 – DBT TPD12S521DBTR TOP-SIDE MARKING PN521 Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Parts are shipped in tape-and-reel form, unless otherwise specified. ELECTRICAL SCHEMATIC ESD_BYP 5V_SUPPLY TMDS_D2+ TMDS_D1+ TMDS_D0+ TMDS_CK+ TMDS_GND TMDS_GND TMDS_GND TMDS_GND TMDS_D2– TMDS_D1– TMDS_D0– TMDS_CK– LV Supply LV Supply CE_REMOTE_IN CE_REMOTE_OUT LV Supply LV Supply DDC_CLK_IN DDC_CLK_OUT 5V_SUPPLY 2 DDC_DAT_OUT DDC_DAT_IN HOTPLUG_DET_OUT HOTPLUG_DET_IN 55-mA Overcurrent Switch Submit Documentation Feedback 5V_OUT Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TPD12S521 TPD12S521 www.ti.com .................................................................................................................................................... SLVS639B – OCTOBER 2007 – REVISED APRIL 2009 38 1 D2+ GND D2– D1+ GND D1– D0+ GND D0– CLK+ GND CLK– CE_R NC D_CK D_DT GND 5OUT HTDT TPD12S521 HDMI Core Chip 20 19 A. HDMI Connector High-speed lines Board Traces GND VIA Connected to 5V Plane Control lines VIA Connected to LV Plane 5 V out VIA Connected to GND Plane External bypass capacitors and resistor components not included Figure 1. Board Layout for HDMI Transmitter Using TPD12S521DBTR VLV VLV 100 kW VLV VLV 47 kW VLV 47 kW 5V VLV 5V 1.7 kW 10 kW 47 kW 5V_SUPPLY 5V_OUT LV_SUPPLY ESD_BYP 0.1 uF 0.1 uF 5V 3.3 V 1.7 kW 27 kW 0.1 uF D0+ 0.1 uF GND D0– D1+ GND D1– HDMI Transmitter Chip D2+ GND D2– D3+ GND CEC_IN DCLK_IN DDAT_IN HPD_IN D3– CE_R NC D_CLK D_DAT GND 5V HTP_D CEC_OUT DCLK_OUT DDAT_OUT HPD_OUT 10 kW A. VLV = supply voltage of the core scalar chip Figure 2. Application Schematic Showing Pins Requiring External Components: HDMI Transmitter Side Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TPD12S521 3 TPD12S521 SLVS639B – OCTOBER 2007 – REVISED APRIL 2009 .................................................................................................................................................... www.ti.com PIN DESCRIPTION NAME ESD LEVEL (1) DESCRIPTION 5V_SUPPLY 1 2 kV LV_SUPPLY 2 2 kV (1) GND, TMDS_GND 3, 5, 8, 11,14, 25, 28, 31, 34, 36 NA TMDS_D2+ 4, 35 8 kV (3) TMDS 0.8-pF ESD protection (4) 6, 33 8 kV (3) TMDS 0.8-pF ESD protection (4) (3) TMDS 0.8-pF ESD protection (4) TMDS_D2– Current source for 5V_OUT Bias for CE/DDC/HOTPLUG level shifters TMDS ESD and parasitic GND return (2) TMDS_D1+ 7, 32 8 kV TMDS_D1– 9, 30 8 kV (3) TMDS 0.8-pF ESD protection (4) 8 kV (3) TMDS 0.8-pF ESD protection (4) (3) TMDS 0.8-pF ESD protection (4) TMDS_D0+ 10, 29 TMDS_D0– 12, 27 8 kV TMDS_CK+ 13, 26 8 kV (3) TMDS 0.8-pF ESD protection (4) 15, 24 8 kV (3) TMDS 0.8-pF ESD protection (4) (1) LV_SUPPLY referenced logic level into ASIC TMDS_CK– CE_REMOTE_IN 16 2 kV DDC_CLK_IN 17 2 kV (1) LV_SUPPLY referenced logic level into ASIC (1) LV_SUPPLY referenced logic level into ASIC DDC_DAT_IN 18 2 kV HOTPLUG_DET_IN 19 2 kV (1) LV_SUPPLY referenced logic level into ASIC HOTPLUG_DET_OUT 20 8 kV (3) 5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD (5) to connector DDC_DAT_OUT 21 8 kV (3) 5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD to connector DDC_CLK_OUT 22 8 kV (3) 5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD to connector CE_REMOTE_OUT 23 8 kV (3) 5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD to connector ESD_BYP 37 2 kV (1) ESD bypass. This pin must be connected to a 0.1-µF ceramic capacitor. 38 (1) 5V_OUT (1) (2) (3) (4) (5) 4 PIN NO. 2 kV 5-V regulator output Human-Body Model (HBM) per MIL-STD-833, Method 3015, CDISCHARGE = 100 pF, RDISCHARGE = 1.5 kΩ, 5V_SUPPLY and LV_SUPPLY within recommended operating conitions, GND = 0 V, and ESD_BYP (pin 37) and HOTPLUG_DET_OUT (pin 20) each bypassed with a 0.1-µF ceramic capacitor connnected to GND. These pins should be routed directly to the associated GND pins on the HDMI connector, with single-point ground vias at the connector. Standard IEC 61000-4-2, CDISCHARGE = 150 pF, RDISCHARGE = 330 Ω, 5V_SUPPLY and LV_SUPPLY within recommended operating conditions, GND = 0 V, and ESD_BYP (pin 37) and HOTPLUG_DET_OUT (pin 20) each bypassed with a 0.1-µF ceramic capacitor connected to GND. These two pins must be connected together inline on the PCB. This output can be connected to an external 0.1-µF ceramic capacitor, resulting in an increased ESD withstand voltage rating. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TPD12S521 TPD12S521 www.ti.com .................................................................................................................................................... SLVS639B – OCTOBER 2007 – REVISED APRIL 2009 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN V5V_SUPPLY VLV_SUPPLY Supply voltage VI/O DC voltage at any channel input Tstg Storage temperature range (1) MAX 6 UNIT V GND – 0.5 6 V –65 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Operating supply voltage 5V_SUPPLY Bias supply voltage LV_SUPPLY Operating temperature MIN NOM MAX 5 5.5 1 3.3 5.5 V 85 °C –40 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TPD12S521 UNIT V 5 TPD12S521 SLVS639B – OCTOBER 2007 – REVISED APRIL 2009 .................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS ICC5 Operating supply current 5V_SUPPLY = 5 V ICC3 Bias supply current LV_SUPPLY = 3.3 V VDROP 5V_OUT overcurrent output drop 5V_SUPPLY = 5 V, IOUT = 55 mA ISC 5V_OUT short-circuit current limit 5V_SUPPLY= 5 V, 5V_OUT = GND IOFF OFF-state leakage current, level-shifting NFET LV_SUPPLY = 0 V MIN 90 TMDS_D[2:0]+/–, TMDS_CK+/–, CE_REMOTE_OUT, DDC_DAT_OUT, DDC_CLK_OUT, HOTPLUG_DET_OUT, 5V_OUT TYP MAX UNIT 110 130 µA 1 5 µA 150 200 mV 135 175 mA 0.1 5 µA 0.1 5 µA 95 140 mV IBACKDRIVE Current conducted from output pins to V_SUPPLY rails when powered down VON Voltage drop across level-shifting NFET LV_SUPPLY = 2.5 V, VS = GND, IDS = 3 mA when ON VF Diode forward voltage VESD ESD withstand voltage VCL Channel clamp voltage at ±8-kV HBM ESD TA = 25°C (1) (3) RDYN Dynamic resistance I = 1 A, TA = 25°C (4) ILEAK TMDS channel leakage current TA = 25°C (1) 0.01 1 µA CIN, TMDS TMDS channel input capacitance 5V_SUPPLY= 5 V, Measured at 1 MHz, VBIAS = 2.5 V (1) 0.8 1.0 pF ΔCIN, TMDS TMDS channel input capacitance matching 5V_SUPPLY= 5 V, Measured at 1 MHz, VBIAS = 2.5 V (1) (5) 0.05 pF CMUTUAL Mutual capacitance between signal pin and adjacent signal pin 5V_SUPPLY= 0 V, Measured at 1 MHz, VBIAS = 2.5 V (1) 0.07 pF CIN Level-shifting input capacitance, capacitance to GND 5V_SUPPLY= 0 V, Measured at 100 KHz, VBIAS = 2.5 V (1) (1) (2) (3) (4) (5) 6 5V_SUPPLY < VCH_OUT IF = 8 mA, TA = 25°C (1) 75 Top diode 0.85 Bottom diode 0.85 Pins 4, 7, 10, 13, 20–24, 27, 30, 33 (1) (2) IEC ±8 Pins 1, 2, 16–19, 37, 38 (1) (3) HBM ±2 kV Positive transients 9 Negative transients –9 Positive transients V V 3 Negative transients Ω 1.5 DDC 3.5 4 CEC 3.5 4 HP 3.5 4 pF This parameter is specified by design and verified by device characterization. Standard IEC 61000-4-2, CDISCHARGE = 150 pF, RDISCHARGE = 330 Ω Human-Body Model (HBM) per MIL-STD-883, Method 3015, CDISCHARGE = 100 pF, RDISCHARGE = 1.5 kΩ These measurements performed with no external capacitor on ESD_BYP. Intrapair matching, each TMDS pair (i.e., D+, D–) Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TPD12S521 TPD12S521 www.ti.com .................................................................................................................................................... SLVS639B – OCTOBER 2007 – REVISED APRIL 2009 TYPICAL PERFORMANCE 1 –1 Insertion Loss (dB) –3 DC Bias = 0 V –5 –7 –9 –11 –13 DC Bias = 3.0 V –15 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10 Frequency (Hz) Figure 3. Insertion Loss Performance Across Frequency Figure 4. Test Board to Measure Eye Diagram for the TPD12S521 (Refer to Eye Diagram Plot) Figure 5. HDMI 1.65Gbps Eye Diagram With TPD12S521 on a Test Board Figure 6. HDMI 1.65Gbps Eye Diagram Without TPD12S521 in the Socket in the Test Board Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TPD12S521 7 PACKAGE OPTION ADDENDUM www.ti.com 5-Jan-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPD12S521DBTR ACTIVE TSSOP DBT 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPD12S521DBTRG4 ACTIVE TSSOP DBT 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Jan-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPD12S521DBTR Package Package Pins Type Drawing TSSOP DBT 38 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.9 10.2 1.8 12.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Jan-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPD12S521DBTR TSSOP DBT 38 2000 346.0 346.0 33.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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