TI TAS5631BPHD

TAS5631B
www.ti.com
SLES263 – NOVEMBER 2010
300-W STEREO / 600-W MONO PurePath™ HD DIGITAL-INPUT POWER STAGE
Check for Samples: TAS5631B
FEATURES
APPLICATIONS
•
•
•
•
•
1
23
•
•
•
•
•
•
PurePath™ HD Enabled Integrated Feedback
Provides:
– Signal Bandwidth up to 80 kHz for
High-Frequency Content From HD Sources
– Ultralow 0.03% THD at 1 W Into 4 Ω
– Flat THD at All Frequencies for Natural
Sound
– 80-dB PSRR (BTL, No Input Signal)
– >100-dB (A-weighted) SNR
– Click- and Pop-Free Start-Up
Multiple Configurations Possible on the Same
PCB With Stuffing Options:
– Mono Parallel Bridge-Tied Load (PBTL)
– Stereo Bridge-Tied Load (BTL)
– 2.1 Single-Ended Stereo Pair and
Bridge-Tied Load Subwoofer
– Quad Single-Ended Outputs
Total Output Power at 10% THD+N
– 600 W in Mono PBTL Configuration
– 300 W per Channel in Stereo BTL
Configuration
– 145 W per Channel in Quad Single-Ended
Configuration
High-Efficiency Power Stage (>88%) With
60-mΩ Output MOSFETs
Two Thermally Enhanced Package Options:
– PHD (64-Pin QFP)
– DKD (44-Pin PSOP3)
Self-Protection Design (Including
Undervoltage, Overtemperature, Clipping, and
Short-Circuit Protection) With Error Reporting
EMI Compliant When Used With
Recommended System Design
Mini Combo System
AV Receivers
DVD Receivers
Active Speakers
DESCRIPTION
The TAS5631B is a high-performance PWM input
class-D amplifier with integrated closed-loop
feedback technology (known as PurePath HD
technology) with the ability to drive up to 300 W (1)
stereo into 4-Ω to 8-Ω speakers from a single 50-V
supply.
PurePath HD technology enables traditional
AB-amplifier performance (<0.03% THD) levels while
providing the power efficiency of traditional class-D
amplifiers.
Unlike traditional class-D amplifiers, the distortion
curve does not increase until the output levels move
into clipping. PurePath HD™
PurePath HD technology enables lower idle losses,
making the device even more efficient.
Note 1. Achievable output power levels are
dependent on the thermal configuration of the target
application. A high-performance thermal interface
material between the package exposed heat slug
and the heat sink should be used to achieve high
output-power levels.
♫♪
DIGITAL
AUDIO
INPUT
TAS5518C
Digital PWM
Processor
TM
PurePath HD
TAS5630
TAS5631B
♫♪
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PurePath HD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
TAS5631B
SLES263 – NOVEMBER 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DEVICE INFORMATION
Terminal Assignment
Both package types contains a heat slug that is located on the top side of the device for convenient thermal
coupling to the heat sink.
DKD PACKAGE
(TOP VIEW)
64-pins QFP package
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GND_A
GND_B
GND_B
OUT_B
OUT_B
PVDD_B
PVDD_B
BST_B
BST_C
PVDD_C
PVDD_C
OUT_C
OUT_C
GND_C
GND_C
_
GND_D
OTW2
CLIP
READY
M1
M2
M3
GND
GND
GVDD_C
GVDD_D
BST_D
OUT_D
OUT_D
PVDD_D
PVDD_D
GND_D
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PSU_REF
VDD
OC_ADJ
RESET
C_STARTUP
INPUT_A
INPUT_B
VI_CM
GND
AGND
VREG
INPUT_C
INPUT_D
TEST
NC
NC
SD
OTW
READY
M1
M2
M3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 pins PACKAGE
(TOP VIEW)
OC_ADJ
RESET
C_STARTUP
INPUT_A
INPUT_B
VI_CM
GND
AGND
VREG
INPUT_C
INPUT_D
TEST
NC
NC
SD
OTW1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VDD
PSU_REF
NC
NC
NC
NC
GND
GND
GVDD_B
GVDD_A
BST_A
OUT_A
OUT_A
PVDD_A
PVDD_A
GND_A
PHD PACKAGE
(TOP VIEW)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
GVDD_AB
BST_A
PVDD_A
PVDD_A
OUT_A
OUT_A
GND_A
GND_B
OUT_B
PVDD_B
BST_B
BST_C
PVDD_C
OUT_C
GND_C
GND_D
OUT_D
OUT_D
PVDD_D
PVDD_D
BST_D
GVDD_CD
PIN ONE LOCATION PHD PACKAGE
Electrical Pin 1
Pin 1 Marker
White Dot
2
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SLES263 – NOVEMBER 2010
MODE SELECTION PINS
MODE PINS
PWM INPUT (1)
OUTPUT
CONFIGURATION
2N
2 × BTL
AD mode
—
—
Reserved
2N
2 × BTL
BD mode
1N
1 × BTL +2 × SE
AD mode
0
1N
4 × SE
AD mode
1
2N
1N
M3
M2
M1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
1
(1)
(2)
0
1
1
0
1
1
1
1 × PBTL
DESCRIPTION
INPUT_C (2)
INPUT_D (2)
0
0
AD mode
1
0
BD mode
Reserved
The 1N and 2N naming convention is used to indicate the number of PWM lines to the power stage per channel in a specific mode.
INPUT_C and INPUT_D are used to select between a subset of AD and BD mode operations in PBTL mode.
PACKAGE HEAT DISSIPATION RATINGS (1)
PARAMETER
TAS5631BPHD
RqJC (°C/W) – 2 BTL or 4 SE channels
2.63
1.4
RqJC (°C/W) – 1 BTL or 2 SE channel(s)
4.13
2.04
RqJC (°C/W) – 1 SE channel
6.45
Pad area
(1)
(2)
TAS5631BDKD
(2)
3.45
2
64 mm
80 mm2
RqJC is junction-to-case; RqCH is case-to-heatsink.
RqCH is an important consideration. Assume a 2-mil (0.051-mm) thickness of thermal grease with a thermal conductivity of 2.5 W/mK
between the pad area and the heat sink and both channels active. The RqCH with this condition is 1.1°C/W for the PHD package and
0.44°C/W for the DKD package.
Table 1. ORDERING INFORMATION (1)
(1)
TA
PACKAGE
DESCRIPTION
0°C–70°C
TAS5631BPHD
64-pin HTQFP
0°C–70°C
TAS5631BDKD
44-pin PSOP3
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
TAS5631B
UNIT
VDD to AGND
–0.3 to 13.2
V
GVDD to AGND
–0.3 to 13.2
V
PVDD_X to GND_X (2)
–0.3 to 69
V
OUT_X to GND_X (2)
–0.3 to 69
V
BST_X to GND_X (2)
–0.3 to 82.2
V
BST_X to GVDD_X
(2)
–0.3 to 69
V
VREG to AGND
–0.3 to 4.2
V
GND_X to GND
–0.3 to 0.3
V
GND_X to AGND
–0.3 to 0.3
V
GND to AGND
–0.3 to 0.3
V
OC_ADJ, M1, M2, M3, OSC_IO+, OSC_IO–, FREQ_ADJ, VI_CM, C_STARTUP,
PSU_REF to GND
–0.3 to 4.2
V
INPUT_X, RESET, SD, OTW1, OTW2, CLIP, READY to GND
Maximum continuous sink current (SD, OTW1, OTW2, CLIP, READY)
Maximum operating junction temperature range, TJ
Storage temperature, Tstg
Human-body model (3) (all pins)
Electrostatic discharge
(1)
(2)
(3)
Charged-device model (3) (all pins)
–0.3 to 7
V
9
mA
0 to 150
°C
–40 to 150
°C
±2
kV
±500
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
These voltages represents the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.
Failure to follow good anti-static ESD handling during manufacture and rework contributes to device malfunction. Make sure the
operators handling the device are adequately grounded through the use of ground straps or alternative ESD protection.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MAX
UNIT
PVDD_x
Half-bridge supply
DC supply voltage
MIN NOM
25
50
52.5
V
GVDD_x
Supply for logic regulators and gate-drive
circuitry
DC supply voltage
10.8
12
13.2
V
VDD
Digital regulator supply voltage
DC supply voltage
10.8
12
13.2
V
3.5
4
Load impedance
Output filter according to schematics in
the application information section.
1.8
2
1.6
2
7
10
7
15
7
10
352
384
RL(BTL)
RL(SE)
RL(PBTL)
LOUTPUT(BTL)
LOUTPUT(SE)
Output filter inductance
Minimum output inductance at IOC
LOUTPUT(PBTL)
fPWM
PWM frame rate
TJ
Junction temperature
0
Ω
mH
500
kHz
125
°C
TERMINAL FUNCTIONS
TERMINAL
NAME
Function (1)
DESCRIPTION
10
P
Analog ground
43
P
HS bootstrap supply (BST); external 0.033-mF capacitor to OUT_A required
41
34
P
HS bootstrap supply (BST); external 0.033-mF capacitor to OUT_B required
40
33
P
HS bootstrap supply (BST); external 0.033-mF capacitor to OUT_C required
PHD NO.
DKD NO.
AGND
8
BST_A
54
BST_B
BST_C
(1)
4
I = Input, O = Output, P = Power
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SLES263 – NOVEMBER 2010
TERMINAL FUNCTIONS (continued)
TERMINAL
Function (1)
DESCRIPTION
NAME
PHD NO.
DKD NO.
BST_D
27
24
P
HS bootstrap supply (BST); external 0.033-mF capacitor to OUT_D required
CLIP
18
—
O
Clipping warning; open drain; active-low
C_STARTUP
3
5
O
Start-up ramp requires a charging capacitor of 4.7 nF to AGND.
TEST
12
14
I
Connect to VREG node
GND
7, 23, 24, 57, 58
9
P
Ground
GND_A
48, 49
38
P
Power ground for half-bridge A
GND_B
46, 47
37
P
Power ground for half-bridge B
GND_C
34, 35
30
P
Power ground for half-bridge C
GND_D
32, 33
29
P
Power ground for half-bridge D
GVDD_A
55
—
P
Gate drive voltage supply requires 0.1-mF capacitor to AGND.
GVDD_B
56
—
P
Gate drive voltage supply requires 0.1-mF capacitor to AGND.
GVDD_C
25
—
P
Gate drive voltage supply requires 0.1-mF capacitor to AGND.
GVDD_D
26
—
P
Gate drive voltage supply requires 0.1-mF capacitor to AGND.
GVDD_AB
—
44
P
Gate drive voltage supply requires 0.22-mF capacitor to AGND.
GVDD_CD
—
23
P
Gate drive voltage supply requires 0.22-mF capacitor to AGND.
INPUT_A
4
6
I
Input signal for half-bridge A
INPUT_B
5
7
I
Input signal for half-bridge B
INPUT_C
10
12
I
Input signal for half-bridge C
INPUT_D
11
13
I
Input signal for half-bridge D
M1
20
20
I
Mode selection
M2
21
21
I
Mode selection
M3
22
22
I
Mode selection
NC
59–62
–
—
No connect; pins may be grounded.
NC
13, 14
15, 16
—
No connect; pins may be grounded.
OC_ADJ
1
3
O
Analog overcurrent programming pin requires resistor to ground.
OTW
—
18
O
Overtemperature warning signal, open-drain, active-low
OTW1
16
—
O
Overtemperature warning signal, open-drain, active-low
OTW2
17
—
O
Overtemperature warning signal, open-drain, active-low
OUT_A
52, 53
39, 40
O
Output, half-bridge A
OUT_B
44, 45
36
O
Output, half-bridge B
OUT_C
36, 37
31
O
Output, half-bridge C
OUT_D
28, 29
27, 28
O
Output, half-bridge D
63
1
P
PSU reference requires close decoupling of 4.7 mF to AGND.
PVDD_A
50, 51
41, 42
P
Power-supply input for half-bridge A requires close decoupling of 0.01-mF capacitor in
parallel with 1-mF capacitor to GND_A.
PVDD_B
42, 43
35
P
Power-supply input for half-bridge B requires close decoupling of 0.01-mF capacitor in
parallel with 1-mF capacitor to GND_B.
PVDD_C
38, 39
32
P
Power-supply input for half-bridge C requires close decoupling of 0.01-mF capacitor in
parallel with 1-mF capacitor to GND_C.
PVDD_D
30, 31
25, 26
P
Power-supply input for half-bridge D requires close decoupling of 0.01-mF capacitor in
parallel with 1-mF capacitor to GND_D.
READY
19
19
O
Normal operation; open-drain; active-high
RESET
2
4
I
Device reset input; active-low
SD
15
17
O
Shutdown signal; open-drain, active-low
VDD
64
2
P
Power supply for digital voltage regulator requires a 47-mF capacitor in parallel with a
0.1-mF capacitor to GND for decoupling.
VI_CM
6
8
O
Analog comparator reference node requires close decoupling of 4.7 mF to AGND.
VREG
9
11
P
Digital regulator supply filter pin requires 0.1-mF capacitor to AGND.
PSU_REF
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TYPICAL SYSTEM BLOCK DIAGRAM
Caps for
External
Filtering
and
Startup/Stop
System
microcontroller
(2)
AMP RESET
LeftChannel
Output
PWM_A
C_STARTUP
VI_CM
PSU_REF
RESET
VALID
/CLIP
*NOTE1
READY
/SD
TAS5518/
TAS5508/
TAS5086
/OTW1, /OTW2, /OTW
I2C
BST_A
BST_B
OUT_A
INPUT_A
PWM_B
Input
H-Bridge 1
INPUT_B
Output
H-Bridge 1
2
OUT_B
2
Bootstrap
Caps
2nd Order
L-C Output
Filter for
each
H-Bridge
2-CHANNEL
H-BRIDGE
BTL MODE
PWM_C
INPUT_C
PWM_D
OUT_C
Input
H-Bridge 2
INPUT_D
Output
H-Bridge 2
2
OUT_D
8
50V
PVDD
12V
PVDD
Power Supply
Decoupling
SYSTEM
Power
Supplies
GND
8
BST_D
OC_ADJ
TEST
VREG
AGND
M3
2nd Order
L-C Output
Filter for
each
H-Bridge
BST_C
VDD
M2
GND
M1
GND_A, B, C, D
Hardwire
Mode
Control
GVDD_A, B, C, D
2
PVDD_A, B, C, D
RightChannel
Output
Bootstrap
Caps
4
GVDD, VDD,
and VREG
Power Supply
Decoupling
Hardwire
OverCurrent
Limit
GND
GVDD (12V)/VDD (12V)
VAC
(1)
6
Logic AND is inside or outside the microcontroller.
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SLES263 – NOVEMBER 2010
FUNCTIONAL BLOCK DIAGRAM
CLIP
READY
OTW1
OTW2
SD
PROTECTION & I/O LOGIC
M1
M2
M3
RESET
STARTUP
CONTROL
C_STARTUP
VDD
POWER-UP
RESET
UVP
VREG
VREG
AGND
TEMP
SENSE
GVDD_A
GVDD_C
GVDD_B
OVER-LOAD
PROTECTION
PPSC
CURRENT
SENSE
CB3C
4
4
4
GND
GVDD_D
OC_ADJ
PVDD_X
OUT_X
GND_X
GVDD_A
PWM
ACTIVITY
DETECTOR
BST_A
PVDD_A
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
OUT_A
GND_A
PSU_REF
GVDD_B
VI_CM
-
ANALOG
LOOP FILTER
PVDD_X
GND
INPUT_C
INPUT_D
ANALOG
LOOP FILTER
ANALOG
LOOP FILTER
ANALOG INPUT MUX
4
AGC
PVDD_B
PWM
RECEIVER
+
ANALOG
LOOP FILTER
INPUT_B
BST_B
+
+
ANALOG COMPARATOR MUX
INPUT_A
CONTROL
TIMING
CONTROL
GATE-DRIVE
OUT_B
GND_B
GVDD_C
BST_C
PVDD_C
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
+
OUT_C
GND_C
-
GVDD_D
BST_D
PVDD_D
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
OUT_D
GND_D
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AUDIO CHARACTERISTICS (BTL)
Audio performance is recorded as a chipset consisting of a TAS5518 PWM processor (modulation index limited to 97.7%)
and a TAS5631B power stage. PCB and system configurations are in accordance with recommended guidelines. Audio
frequency = 1 kHz, PVDD_X = 50 V, GVDD_X = 12 V, RL = 4 Ω, fS = 384 kHz, ROC = 22 kΩ, TC = 75°C;
output filter: LDEM = 7 mH, CDEM = 680 nF, MODE = 000, unless otherwise noted.
PARAMETER
PO
Power output per channel
TEST CONDITIONS
MIN
TYP MAX UNIT
RL = 4 Ω, 10% THD+N, clipped input signal
300
RL = 6 Ω, 10% THD+N, clipped input signal
210
RL = 8 Ω, 10% THD+N, clipped input signal
160
RL = 4 Ω, 1% THD+N, unclipped input signal
240
RL = 6 Ω, 1% THD+N, unclipped input signal
160
RL = 8 Ω, 1% THD+N, unclipped input signal
W
125
THD+N
Total harmonic distortion + noise
1W
Vn
Output integrated noise
A-weighted, TAS5518 modulator
|VOS|
Output offset voltage
No signal
SNR
Signal-to-noise ratio (1)
A-weighted, TAS5518 modulator
103
dB
DNR
Dynamic range
A-weighted, input level –60 dBFS using TAS5518
modulator
103
dB
Pidle
Power dissipation due to idle losses
(IPVDD_X)
PO = 0, four channels switching (2)
3.9
W
(1)
(2)
0.03%
180
20
mV
50
mV
SNR is calculated relative to 1% THD-N output level.
Actual system idle losses also are affected by core losses of output inductors.
AUDIO SPECIFICATION (Single-Ended Output)
Audio performance is recorded as a chipset consisting of a TAS5086 PWM processor (modulation index limited to 97.7%)
and a TAS5631B power stage. PCB and system configurations are in accordance with recommended guidelines. Audio
frequency = 1 kHz, PVDD_X = 50 V, GVDD_X = 12 V, RL = 2 Ω, fS = 384 kHz, ROC = 22 kΩ, TC = 75°C;
output filter: LDEM = 7 mH, CDEM = 470 nF, MODE = 100, unless otherwise noted.
PARAMETER
PO
TEST CONDITIONS
Power output per channel
MIN
TYP MAX
RL = 2 Ω, 10%, THD+N, clipped input signal
145
RL = 3 Ω, 10%, THD+N, clipped input signal
100
RL = 4 Ω, 10%, THD+N, clipped input signal
75
RL = 2 Ω, 1% THD+N, unclipped input signal
110
RL = 3 Ω, 1% THD+N, unclipped input signal
75
RL = 4 Ω, 1% THD+N, unclipped input signal
UNIT
W
55
THD+N
Total harmonic distortion + noise
1W
Vn
Output integrated noise
A-weighted, TAS5086 modulator
140
mV
SNR
Signal-to-noise ratio (1)
A-weighted, TAS5086 modulator
100
dB
DNR
Dynamic range
A-weighted, input level –60 dBFS using TAS5086
modulator
100
dB
Pidle
Power dissipation due to idle losses (IPVDD_X)
PO = 0, 4 channels switching (2)
3
W
(1)
(2)
8
0.04%
SNR is calculated relative to 1% THD-N output level.
Actual system idle losses are affected by core losses of output inductors.
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AUDIO SPECIFICATION (PBTL)
Audio performance is recorded as a chipset consisting of a TAS5518 PWM processor (modulation index limited to 97.7%)
and a TAS5631B power stage. PCB and system configurations are in accordance with recommended guidelines. Audio
frequency = 1 kHz, PVDD_X = 50 V, GVDD_X = 12 V, RL = 2 Ω, fS = 384 kHz, ROC = 22 kΩ, TC = 75°C;
output filter: LDEM = 7 mH, CDEM = 1 mF, MODE = 101-00, unless otherwise noted.
PARAMETER
PO
TEST CONDITIONS
Power output per channel
MIN
TYP MAX
RL = 2 Ω, 10%, THD+N, clipped input signal
600
RL = 3 Ω, 10%, THD+N, clipped input signal
400
RL = 4 Ω, 10%, THD+N, unclipped input signal
300
RL = 2 Ω, 1% THD+N, unclipped input signal
480
RL = 3 Ω, 1% THD+N, unclipped input signal
310
RL = 4 Ω, 1% THD+N, unclipped input signal
UNIT
W
230
THD+N
Total harmonic distortion + noise
1W
Vn
Output integrated noise
A-weighted, TAS5518 modulator
170
mV
SNR
Signal-to-noise ratio (1)
A-weighted, TAS5518 modulator
103
dB
DNR
Dynamic range
A-weighted, input level –60 dBFS using
TAS5518 modulator
103
dB
Pidle
Power dissipation due to idle losses (IPVDD_X)
PO = 0, 4 channels switching (2)
3.7
W
(1)
(2)
0.03%
SNR is calculated relative to 1% THD-N output level.
Actual system idle losses are affected by core losses of output inductors.
ELECTRICAL CHARACTERISTICS
PVDD_X = 50V, GVDD_X = 12 V, VDD = 12V, TC (case temperature) = 75°C, fS = 384 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
VREG
Voltage regulator, only used as reference
node, VREG
VI_CM
Analog comparator reference node, VI_CM
IVDD
VDD supply current
IGVDD_x
Gate-supply current per half-bridge
IPVDD_x
Half-bridge idle current
VDD = 12 V
3
3.3
3.6
V
1.5
1.75
1.9
V
Operating, 50% duty cycle
22.5
Idle, reset mode
22.5
50% duty cycle
12.5
Reset mode
mA
mA
1.5
50% duty cycle without output filter or
load
19.5
mA
Reset mode, no switching
750
mA
OUTPUT-STAGE MOSFETs
Drain-to-source resistance, low side (LS)
RDS(on)
Drain-to-source resistance, high side (HS)
TJ = 25°C, excludes metallization
resistance,
GVDD = 12 V
60
100
mΩ
60
100
mΩ
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ELECTRICAL CHARACTERISTICS (continued)
PVDD_X = 50V, GVDD_X = 12 V, VDD = 12V, TC (case temperature) = 75°C, fS = 384 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
I/O PROTECTION
Vuvp,G
Undervoltage protection limit, GVDD_X
Vuvp,hyst
10
(1)
V
0.6
V
OTW1 (1)
Overtemperature warning 1
95
100
105
°C
OTW2 (1)
Overtemperature warning 2
115
125
135
°C
OTWhyst
(1)
Temperature drop needed below OTW
temperature for OTW to be inactive after
OTW event
25
Overtemperature error
OTE (1)
145
155
°C
165
°C
OTE-OTW differential
30
°C
A reset must occur for SD to be released
following an OTE event
25
°C
fPWM = 384 kHz
2.6
ms
Resistor – programmable, nominal peak
current in 1-Ω load,
64-pin QFP package (PHD)
ROCP = 22 kΩ
19
A
Resistor – programmable, nominal peak
current in 1-Ω load,
44-pin PSOP3 package (DKD)
ROCP = 24 kΩ
19
A
Overcurrent response time, latched
Resistor – programmable, nominal peak
current in 1-Ω load,
ROCP = 47 kΩ
19
A
IOCT
Overcurrent response time
Time from application of short condition to
Hi-Z of affected half-bridge
150
ns
IPD
Internal pulldown resistor at output of each
half-bridge
Connected when RESET is active to
provide bootstrap charge. Not used in SE
mode.
3
mA
OTEHYST
OLPC
(1)
Overload protection counter
Overcurrent limit response
IOC
STATIC DIGITAL SPECIFICATIONS
VIH
High-level input voltage
VIL
Low-level input voltage
Ilkg
Input leakage current
INPUT_X, M1, M2, M3, RESET
1.9
V
1.45
V
100
mA
kΩ
OTW/SHUTDOWN (SD)
RINT_PU
Internal pullup resistance, OTW1 to VREG,
OTW2 to VREG, SD to VREG
VOH
High-level output voltage
VOL
Low-level output voltage
IO = 4 mA
FANOUT
Device fanout OTW1, OTW2, SD, CLIP,
READY
No external pullup
(1)
10
Internal pullup resistor
External pullup of 4.7 kΩ to 5 V
20
26
33
3
3.3
3.6
4.5
5
200
30
500
V
mV
devices
Specified by design
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SLES263 – NOVEMBER 2010
TYPICAL CHARACTERISTICS, BTL CONFIGURATION
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
OUTPUT POWER
vs
SUPPLY VOLTAGE
320
THD+N - Total Harmonic Distortion + Noise - %
10
5
TC = 75°C
300
280
260
PO - Output Power - W
2
1
0.5
0.2
0.1
4W
6W
0.05
0.005
20m
8W
100m200m
1 2
5 10 20 50 100
PO - Output Power - W
400
120
100
80
30
35
40
45
PVDD - Supply Voltage - V
UNCLIPPED OUTPUT POWER
vs
SUPPLY VOLTAGE
SYSTEM EFFICIENCY
vs
OUTPUT POWER
TC = 75°C
4W
200
180
Efficiency - %
PO - Output Power - W
8W
140
Figure 2.
220
6W
160
140
8W
100
80
60
40
20
0
25
6W
Figure 1.
240
120
4W
20
0
25
280
260
240
220
200
180
160
60
40
0.02
0.01
TC = 75°C
THD+N at 10%
30
35
40
45
50
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
8W
6W
50
4W
TC = 25°C
THD+N at 10%
0
Figure 3.
100
400
200
300
500
2 Channel Output Power - W
600 650
Figure 4.
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
OUTPUT POWER
vs
CASE TEMPERATURE
TC = 25°C
THD+N at 10%
PO - Output Power - W
Power Loss - W
SYSTEMS POWER LOSS
vs
OUTPUT POWER
4W
6W
8W
0
100
200
300
400
500
2 Channel Output Power - W
600 650
360
340
320
300
280
260
240
220
200
180
160
140
120
100
80
60
40
20
0
10
4W
6W
8W
THD+N at 10%
20
30
40 50 60 70 80 90 100 110 120
TC - Case Temperature - °C
Figure 5.
Figure 6.
NOISE AMPLITUDE
vs
FREQUENCY
+0
-10
-20
Noise Amplitude - dB
-30
-40
-50
TC = 75°C,
VREF = 31.7 V,
Sample Rate = 48 kHz,
FFT Size = 16384
-60
-70
-80
-90
-100
-110
-120
4W
-130
-140
-150
-160
0k
12
2k
4k
6k
8k 10k 12k 14k 16k 18k 20k 22k
f - Frequency - Hz
Figure 7.
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SLES263 – NOVEMBER 2010
TYPICAL CHARACTERISTICS, SE CONFIGURATION
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
OUTPUT POWER
vs
SUPPLY VOLTAGE
5
160
TC = 75°C
150
140
130
4W
2
1
PO - Output Power - W
THD+N - Total Harmonic Distortion + Noise - %
10
3W
0.5
2W
0.2
0.1
0.05
2W
120
110
100
3W
90
80
70
4W
60
50
40
30
20
0.02
0.01
0.005
20m
TC = 75°C
THD+N at 10%
200m
1 2
10 20
PO - Output Power - W
100 200
10
0
25
30
35
40
45
PVDD - Supply Voltage - V
Figure 8.
50
Figure 9.
OUTPUT POWER
vs
CASE TEMPERATURE
PO - Output Power - W
170
160
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
10
3W
2W
4W
THD+N at 10%
20
30
40 50 60 70 80 90 100 110 120
TC - Case Temperature - °C
Figure 10.
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TYPICAL CHARACTERISTICS, PBTL CONFIGURATION
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
5
650
T
TC = 75°C
2 W (TC = 50 C)
1
550
3W
2
2 W (TC = 50oC)
500
4W
0.5
6W
0.2
TC = 75°C
THD+N at 10%
600
o
PO - Output Power - W
THD+N - Total Harmonic Distortion + Noise - %
10
OUTPUT POWER
vs
SUPPLY VOLTAGE
8W
0.1
0.05
3W
450
400
4W
350
6W
300
8W
250
200
150
0.02
100
0.01
0.005
20m
50
100m 200m 1 2
5 10 20 50 100 200 700
PO - Output Power - W
0
25
30
35
40
45
PVDD - Supply Voltage - V
Figure 11.
50
Figure 12.
OUTPUT POWER
vs
CASE TEMPERATURE
700
2W
650
THD+N at 10%
600
PO - Output Power - W
550
500
3W
450
400
4W
350
300
6W
250
8W
200
150
100
50
0
10
14
20
30
40 50 60 70 80 90 100 110 120
TC - Case Temperature - °C
Figure 13.
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TAS5631B
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SLES263 – NOVEMBER 2010
APPLICATION INFORMATION
PCB MATERIAL RECOMMENDATION
FR-4 2-oz. (70 mm) glass epoxy material is recommended for use with the TAS5631B. The use of this material
can provide for higher power output, improved thermal performance, and better EMI margin (due to lower PCB
trace resistance).
PVDD CAPACITOR RECOMMENDATION
The large capacitors used in conjunction with each full bridge are referred to as the PVDD capacitors. These
capacitors should be selected for proper voltage margin and adequate capacitance to support the power
requirements. In practice, with a well-designed system power supply, 1000 mF, 63 V support more applications.
The PVDD capacitors should be the low-ESR type because they are used in a circuit associated with high-speed
switching.
DECOUPLING CAPACITOR RECOMMENDATION
To design an amplifier that has robust performance, passes regulatory requirements, and exhibits good audio
performance, good-quality decoupling capacitors should be used. In practice, X7R should be used in this
application.
The voltage of the decoupling capacitors should be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the
selection of the 0.1-mF capacitor that is placed on the power supply to each half-bridge. It must withstand the
voltage overshoot of the PWM switching, the heat generated by the amplifier during high power output, and the
ripple current created by high power output. A minimum voltage rating of 63 V is required for use with a 50-V
power supply.
SYSTEM DESIGN RECOMMENDATIONS
The following schematics and PCB layouts illustrate best practices in the use of the TAS5631B.
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15
R_RIGHT_N
IN_RIGHT_P
IN_LEFT_N
IN_LEFT_P
/RESET
100R
R13
100R
R12
100R
R11
100R
R10
100R
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GND
READY
/CLIP
/OTW2
/OTW1
/SD
C18
100pF
GND
R19
47k
GND
GND
GND
GND
100nF
C22
VREG
GND
VREG
4.7uF
C21
4.7nF
22.0k
C20
R20
4.7uF
/OTW1
/SD
NC
NC
TEST
INPUT_D
INPUT_C
VREG
AGND
GND
VI_CM
INPUT_B
INPUT_A
C_STARTUP
/RESET
OC_ADJ
PSU_REF
/CLIP
R18
VREG
GND
NC
READY
GND
NC
M1
U10
TAS5631PHD
VREG
NC
M2
VDD
/OTW2
GND
GND
GND
C33
100nF
GND
GND
NC
M3
C31
100nF
GND
GND
C30
100nF
GVDD_B
C32
100nF
GND GND
GVDD_C
3.3R
GVDD_A
GVDD_D
C26
100nF
3.3R
3.3R
R33
R32
C43
33nF
BST_A
BST_D
C23
C25
10uF
OUT_A
OUT_D
C40
33nF
OUT_A
OUT_D
R31
C63
2.2uF
GND_D
GND_C
GND_C
OUT_C
OUT_C
PVDD_C
PVDD_C
BST_C
BST_B
PVDD_B
PVDD_B
OUT_B
OUT_B
GND_B
GND_B
GND_A
GND
C60
2.2uF
PVDD_A
PVDD_D
3.3R
GND_A
PVDD_A
PVDD_D
16
GND_D
R30
GND
C62
2.2uF
C61
2.2uF
GND
L13
7uH
7uH
L12
C42
33nF
C41
33nF
L11
7uH
L10
7uH
1000uF
C65
C53
680nF
C52
680nF
GND
C51
680nF
C50
680nF
C72
1nF
GND
C73
1nF
GND
1000uF
C66
C71
1nF
GND
C70
1nF
R73
3.3R
C77
10nF
C76
10nF
R72
3.3R
GND
GND
GND
C68
47uF
63V
R71
3.3R
C75
10nF
C74
10nF
R70
3.3R
C67
1000uF
GND
GND
C69
2.2uF
GND
C64
1000uF
GND
GND
PVDD
GVDD/VDD (+12V)
PVDD
OUT_RIGHT_R
-
+
GND
OUT_RIGHT_P
C78
10nF
R74
3.3R
OUT_LEFT_M
-
+
OUT_LEFT_P
PVDD
GVDD/VDD (+12V)
TAS5631B
SLES263 – NOVEMBER 2010
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Figure 14. Typical Differential (2N) BTL Application With BD Modulation Filters
Copyright © 2010, Texas Instruments Incorporated
READY
/CLIP
/OTW2
/OTW1
/SD
IN_N
IN_P
/RESET
100R
100R
100R
GND
100pF
GND
VREG
47k
GND
GND
GND
GND
100nF
4.7uF
4.7nF
22.0k
VREG
VREG
GND
GND
1
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
/OTW1
/SD
NC
NC
TEST
INPUT_D
INPUT_C
VREG
AGND
GND
VI_CM
INPUT_B
INPUT_A
C_STARTUP
/RESET
OC_ADJ
4.7uF
GND GND
100nF
GND
100nF
GND
GND GND
58
VREG
100nF
64
VDD
/OTW2
17
63
PSU_REF
/CLIP
18
10uF
NC
READY
19
62
20
57
GND
GND
100nF
GND GND
100nF
TAS5631PHD
VREG
33nF
3.3R
3.3R
3.3R
3.3R
33nF
GND
24
54
GVDD_C
25
61
NC
M1
56
GVDD_B
GVDD_D
26
53
BST_A
BST_D
27
60
NC
M2
55
GVDD_A
OUT_A
OUT_D
28
52
OUT_A
OUT_D
29
51
PVDD_A
PVDD_D
30
50
PVDD_A
PVDD_D
31
59
NC
M3
22
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21
GND
GND
49
GND_A
GND_D
32
VDD (+12V)
2.2uF
GND_D
GND_C
GND_C
OUT_C
OUT_C
PVDD_C
PVDD_C
BST_C
BST_B
PVDD_B
PVDD_B
OUT_B
OUT_B
GND_B
GND_B
GND_A
GND
2.2uF
48
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
GND
2.2uF
2.2uF
GND
33nF
33nF
7uH
7uH
7uH
7uH
1uF
1000uF
1000uF
GND
1uF
1000uF
1000uF
GND
GND
1nF
1nF
GND
GND
47uF
GND
3.3R
10nF
10nF
3.3R
GND
+
-
GVDD (+12V)
PVDD
OUT_LEFT_M
GND
OUT_LEFT_P
10nF
3.3R
GND
2.2uF
PVDD
GVDD (+12V)
TAS5631B
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SLES263 – NOVEMBER 2010
Figure 15. Typical (2N) PBTL Application With AD Modulation Filters
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READY
/CLIP
/OTW2
/OTW1
/SD
IN_D
IN_C
IN_B
IN_A
/RESET
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150 kOhm
169 kOhm
191 kOhm
191 kOhm
196 kOhm
50 V
49 V
48 V
47 V
<47 V
R_COMP
PVDD
100R
100R
100R
100R
GND
100pF
PVDD
PVDD
C
A
47k
10k
470uF
R_COMP
10k
10k
10k
GND
GND
R_COMP
100nF
4.7uF
10nF
470uF
470uF
470uF
GND
GND
GND
GND
22.0k
VREG
10k
10k
VREG
GND
GND
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
470nF
470nF
/OTW1
/SD
NC
NC
TEST
INPUT_D
INPUT_C
VREG
AGND
GND
VI_CM
INPUT_B
INPUT_A
100nF
100nF
100nF
100nF
C_STARTUP
/RESET
OC_ADJ
4.7uF
62
NC
100R
61
100nF
NC
GND GND
100nF
GND
GND
10nF
10nF
3.3R
3.3R
10nF
10nF
3.3R
3.3R
GND
60
NC
GND
GND GND
100nF
54
GND
GND
OUT_C_M
-
+
OUT_C_P
GND
GND
OUT_A_M
-
+
OUT_A_P
100nF
VREG
GND
PVDD
PVDD
D
B
GND GND
100nF
TAS5631PHD
33nF
52
3.3R
3.3R
53
470uF
470uF
470uF
470uF
3.3R
3.3R
33nF
50
PVDD_A
VREG
10uF
64
VDD
/OTW2
17
63
PSU_REF
/CLIP
18
59
NC
M3
22
READY
19
58
GND
GND
23
M1
20
57
GND
GND
24
M2
21
56
GVDD_B
GVDD_C
25
51
GND
GND
49
GND_A
GND_D
55
GVDD_A
GVDD_D
26
BST_A
BST_D
27
OUT_A
OUT_D
28
OUT_A
OUT_D
29
PVDD_A
PVDD_D
30
PVDD_D
10k
10k
R_COMP
10k
10k
R_COMP
31
18
32
VDD (+12V)
2.2uF
GND_D
GND_C
GND_C
10k
10k
OUT_C
OUT_C
PVDD_C
PVDD_C
BST_C
BST_B
PVDD_B
PVDD_B
OUT_B
OUT_B
GND_B
GND_B
GND_A
GND
2.2uF
48
47
33
34
35
36
37
38
39
40
41
42
43
44
45
46
470nF
470nF
GND
100nF
100nF
100nF
100nF
GND
2.2uF
2.2uF
33nF
33nF
GND
GND
10nF
47uF
10nF
3.3R
3.3R
10nF
10nF
3.3R
3.3R
7uH
7uH
7uH
7uH
GND
GND
OUT_D_M
-
+
OUT_D_P
GND
GND
OUT_B_M
-
+
OUT_B_P
GND
GND
2.2uF
GND
10nF
3.3R
GVDD (+12V)
D
PVDD
C
PVDD
B
PVDD
A
GVDD (+12V)
TAS5631B
SLES263 – NOVEMBER 2010
www.ti.com
Figure 16. Typical SE Application
Copyright © 2010, Texas Instruments Incorporated
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TAS5631B
READY
/CLIP
/OTW2
/OTW1
/SD
IN_RIGHT
IN_LEFT
IN_CENTER
/RESET
100R
100R
100R
100R
GND
100pF
47k
VREG
GND
GND
GND
GND
100nF VREG
4.7uF
10nF
22.0k
GND
1
191 kOhm
191 kOhm
196 kOhm
47 V
<47 V
169 kOhm
49 V
48 V
R_COMP
150 kOhm
/OTW1
/SD
NC
NC
TEST
INPUT_D
INPUT_C
VREG
AGND
GND
VI_CM
INPUT_B
INPUT_A
C_STARTUP
/RESET
OC_ADJ
PVDD
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
4.7uF
GND GND
100nF
50 V
VREG
VREG
GND
10uF
64
VDD
/OTW2
17
63
PSU_REF
/CLIP
18
62
19
61
100nF
NC
READY
60
NC
VREG
100nF
GND
GND GND
59
GND
100nF
GND
3.3R
33nF
GND GND
100nF
TAS5631PHD
NC
M3
22
M1
20
58
GND
GND
23
NC
57
GND
GND
24
3.3R
3.3R
3.3R
33nF
GVDD_D
26
54
BST_A
BST_D
53
28
27
VDD (+12V)
25
M2
21
55
GVDD_A
OUT_A
OUT_D
52
OUT_A
OUT_D
29
51
PVDD_A
PVDD_D
30
50
PVDD_A
PVDD_D
31
56
GVDD_B
GVDD_C
49
GND_A
GND_D
32
2.2uF
GND_D
GND_C
GND_C
OUT_C
OUT_C
PVDD_C
PVDD_C
BST_C
BST_B
PVDD_B
PVDD_B
OUT_B
OUT_B
GND_B
GND_B
GND_A
GND
2.2uF
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
GND
2.2uF
2.2uF
GND
7uH
PVDD
7uH
PVDD
33nF
33nF
470uF
470uF
470uF
470uF
1000uF
GND
GND
10k
10k
R_COMP
GND
10k
10k
R_COMP
GND
47uF
GND
10k
10k
10nF
3.3R
GND
2.2uF
7uH
680nF
GND
680nF
7uH
GND
470nF
GND
GND
470nF
GND
10nF
100nF
100nF
10nF
10nF
100nF
100nF
10nF
1nF
1nF
1000uF
3.3R
GND
3.3R
3.3R
GND
3.3R
3.3R
10nF
10nF
3.3R
GND
+
-
www.ti.com
GVDD (+12V)
PVDD
OUT_RIGHT_M
-
+
OUT_RIGHT_P
OUT_LEFT_M
-
+
OUT_LEFT_P
PVDD
OUT_CENTER_M
GND
OUT_CENTER_P
PVDD
GVDD (+12V)
TAS5631B
SLES263 – NOVEMBER 2010
Figure 17. Typical 2.1 System (2N) Input BTL and (1N) Input SE Application
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19
20
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READY
/OTW
/SD
IN_RIGHT_N
IN_RIGHT_P
IN_LEFT_N
IN_LEFT_P
/RESET
VDD (+12V)
100R
100R
100R
100R
100R
GND
100pF
VREG
47k
GND
GND
GND
GND
GND
100nF
4.7uF
4.7nF
24k
4.7uF
VREG
10uF
GND
GND
GND
VREG
VREG
GND
100nF
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
M3
M2
M1
READY
/OTW
/SD
NC
NC
TEST
INPUT_D
INPUT_C
VREG
AGND
GND
VI_CM
INPUT_B
INPUT_A
TAS5631DKD
C_STARTUP
/RESET
OC_ADJ
VDD
PSU_REF
GVDD_CD
BST_D
PVDD_D
PVDD_D
OUT_D
OUT_D
GND_D
GND_C
OUT_C
PVDD_C
BST_C
BST_B
PVDD_B
OUT_B
GND_B
GND_A
OUT_A
OUT_A
PVDD_A
PVDD_A
BST_A
GVDD_AB
100nF
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
GND
100nF
33nF
1.5R
33nF
GND
100nF
GND
33nF
GND
33nF
100nF
1.5R
2.2uF
2.2uF
2.2uF
2.2uF
GND
7uH
680nF
GND
GND
1000uF
680nF
7uH
GND
1000uF
7uH
680nF
GND
680nF
7uH
1nF
1nF
GND
1000uF
47uF
1nF
1nF
1000uF
GND
3.3R
10nF
10nF
3.3R
GND
GND
+
-
OUT_RIGHT_M
GND
OUT_RIGHT_P
10nF
3.3R
OUT_LEFT_M
-
+
OUT_LEFT_P
GND
2.2uF
3.3R
10nF
10nF
3.3R
GND
GVDD (+12V)
PVDD
PVDD
PVDD
GVDD (+12V)
TAS5631B
SLES263 – NOVEMBER 2010
www.ti.com
Figure 18. Typical Differential Input BTL Application With BD Modulation Filters, DKD Package
Copyright © 2010, Texas Instruments Incorporated
TAS5631B
www.ti.com
SLES263 – NOVEMBER 2010
THEORY OF OPERATION
POWER SUPPLIES
To facilitate system design, the TAS5631B needs only a 12-V supply in addition to the (typical) 50-V power-stage
supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog
circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is
accommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge.
To provide outstanding electrical and acoustical characteristics, the PWM signal path, including gate drive and
output stage, is designed as identical, independent half-bridges. For this reason, each half-bridge has separate
gate-drive supply pins (GVDD_X), bootstrap pins (BST_X), and power-stage supply pins (PVDD_X).
Furthermore, an additional pin (VDD) is provided as a supply for all common circuits. Although supplied from the
same 12-V source, it is highly recommended to separate GVDD_A, GVDD_B, GVDD_C, GVDD_D, and VDD on
the printed-circuit board (PCB) by RC filters (see application diagram for details). These RC filters provide the
recommended high-frequency isolation. Special attention should be paid to placing all decoupling capacitors as
close to their associated pins as possible. In general, inductance between the power supply pins and decoupling
capacitors must be avoided. (See reference board documentation for additional information.)
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the
bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM
switching frequencies in the range from 300 kHz to 4000 kHz, it is recommended to use 33-nF ceramic
capacitors, size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage,
even during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during
the remaining part of the PWM cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin is
decoupled with a 2.2-mF ceramic capacitor placed as close as possible to each supply pin. It is recommended to
follow the PCB layout of the TAS5631B reference design. For additional information on recommended power
supply and required components, see the application diagrams in this data sheet.
The 12-V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 50-V
power-stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not
critical as facilitated by the internal power-on-reset circuit. Moreover, the TAS5631B is fully protected against
erroneous power-stage turnon due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are
non-critical within the specified range (see the Recommended Operating Conditions table of this data sheet).
SYSTEM POWER-UP/POWER-DOWN SEQUENCE
Powering Up
The TAS5631B does not require a power-up sequence. The outputs of the H-bridges remain in a
high-impedance state until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage
protection (UVP) voltage threshold (see the Electrical Characteristics table of this data sheet). Although not
specifically required, it is recommended to hold RESET in a low state while powering up the device. This allows
an internal circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge
output.
Powering Down
The TAS5631B does not require a power-down sequence. The device remains fully operational as long as the
gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage
threshold (see the Electrical Characteristics table of this data sheet). Although not specifically required, it is a
good practice to hold RESET low during power down, thus preventing audible artifacts including pops or clicks.
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TAS5631B
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ERROR REPORTING
The SD, OTW, OTW1, and OTW2 pins are active-low, open-drain outputs. Their function is for protection-mode
signaling to a PWM controller or other system-control device.
Any fault resulting in device shutdown is signaled by the SD pin going low. Likewise, OTW and OTW2 go low
when the device junction temperature exceeds 125°C and OTW1 goes low when the junction temperature
exceeds 100°C (see the following table).
SD
OTW1
OTW2,
OTW
0
0
0
Overtemperature (OTE) or overload (OLP) or undervoltage (UVP)
0
0
1
Overload (OLP) or undervoltage (UVP). Junction temperature higher than 100°C (overtemperature
warning)
0
1
1
Overload (OLP) or undervoltage (UVP)
1
0
0
Junction temperature higher than 125°C (overtemperature warning)
1
0
1
Junction temperature higher than 100°C (overtemperature warning)
1
1
1
Junction temperature lower than 100°C and no OLP or UVP faults (normal operation)
DESCRIPTION
Note that asserting RESET low forces the SD signal high, independent of faults being present. TI recommends
monitoring the OTW signal using the system microcontroller and responding to an overtemperature warning
signal by, e.g., turning down the volume to prevent further heating of the device resulting in device shutdown
(OTE).
To reduce external component count, an internal pullup resistor to 3.3 V is provided on both SD and OTW
outputs. Level compliance for 5-V logic can be obtained by adding external pullup resistors to 5 V (see the
Electrical Characteristics table of this data sheet for further specifications).
DEVICE PROTECTION SYSTEM
The TAS5631B contains advanced protection circuitry carefully designed to facilitate system integration and ease
of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as
short circuits, overload, overtemperature, and undervoltage. The TAS5631B responds to a fault by immediately
setting the power stage in a high-impedance (Hi-Z) state and asserting the SD pin low. In situations other than
overload and overtemperature error (OTE), the device automatically recovers when the fault condition has been
removed, i.e., the supply voltage has increased.
The device functions on errors, as shown in the following table.
BTL Mode
Local Error In
A
B
C
D
PBTL Mode
Turns Off
A+B
C+D
Local Error In
SE Mode
Turns Off
A
B
C
Local Error In
A
A+B+C+D
D
B
C
D
Turns Off
A+B
C+D
Bootstrap UVP does not shut down according to the table; it shuts down the respective half-bridge.
PIN-TO-PIN SHORT-CIRCUIT PROTECTION (PPSC)
The PPSC detection system protects the device from permanent damage if a power output pin (OUT_X) is
shorted to GND_X or PVDD_X. For comparison, the OC protection system detects an overcurrent after the
demodulation filter, whereas PPSC detects shorts directly at the pin before the filter. PPSC detection is
performed at startup, i.e., when VDD is supplied; consequently, a short to either GND_X or PVDD_X after
system startup does not activate the PPSC detection system. When PPSC detection is activated by a short on
the output, all half-bridges are kept in a Hi-Z state until the short is removed; the device then continues the
start-up sequence and starts switching. The detection is controlled globally by a two-step sequence. The first
step ensures that there are no shorts from OUT_X to GND_X; the second step tests that there are no shorts
from OUT_X to PVDD_X. The total duration of this process is roughly proportional to the capacitance of the
22
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TAS5631B
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SLES263 – NOVEMBER 2010
output LC filter. The typical duration is <15 ms/mF. While the PPSC detection is in progress, SD is kept low, and
the device does not react to changes applied to the RESET pin. If no shorts are present, the PPSC detection
passes, and SD is released. A device reset does not start a new PPSC detection. PPSC detection is enabled in
BTL and PBTL output configurations; the detection is not performed in SE mode. To make sure not to trip the
PPSC detection system, it is recommended not to insert resistive load between OUT_X and GND_X or PVDD_X.
OVERTEMPERATURE PROTECTION
The two different package options have individual overtemperature protection schemes.
PHD Package
The TAS5631B PHD package option has a three-level temperature-protection system that asserts an active-low
warning signal (OTW1) when the device junction temperature exceeds 100°C (typical), (OTW2) when the device
junction temperature exceeds 125°C (typical) and, if the device junction temperature exceeds 155°C (typical), the
device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z)
state and SD being asserted low. OTE is latched in this case. To clear the OTE latch, RESET must be asserted.
Thereafter, the device resumes normal operation.
DKD Package
The TAS5631B DKD package option has a two-level temperature-protection system that asserts an active-low
warning signal (OTW) when the device junction temperature exceeds 125°C (typical) and, if the device junction
temperature exceeds 155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs
being set in the high-impedance (Hi-Z) state and SD being asserted low. OTE is latched in this case. To clear the
OTE latch, RESET must be asserted. Thereafter, the device resumes normal operation.
UNDERVOLTAGE PROTECTION (UVP) AND POWER-ON RESET (POR)
The UVP and POR circuits of the TAS5631B fully protect the device in any power-up/down and brownout
situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are
fully operational when the GVDD_X and VDD supply voltages reach values stated in the Electrical
Characteristics table. Although GVDD_X and VDD are independently monitored, a supply-voltage drop below the
UVP threshold on any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the
high-impedance (Hi-Z) state and SD being asserted low. The device automatically resumes operation when all
supply voltages have increased above the UVP threshold.
DEVICE RESET
When RESET is asserted low, all power-stage FETs in the four half-bridges are forced into a high-impedance
(Hi-Z) state.
In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables
weak pulldown of the half-bridge outputs. In the SE mode, the output is forced into a high-impedance state when
asserting the reset input low. Asserting the reset input low removes any fault information to be signaled on the
SD output, i.e., SD is forced high. A rising-edge transition on the reset input allows the device to resume
operation after an overload fault. To ensure thermal reliability, the rising edge of reset must occur no sooner than
4 ms after the falling edge of SD.
SYSTEM DESIGN CONSIDERATIONS
A rising-edge transition on the reset input allows the device to execute the startup sequence and start switching.
Apply only audio when the state of READY is high; that starts and stops the amplifier without having audible
artifacts that are heard in the output transducers. If an overcurrent protection event is introduced, the READY
signal goes low; hence, filtering is needed if the signal is intended for audio muting in non-microcontroller
systems.
The CLIP signal indicates that the output is approaching clipping. The signal can be used either to activate a
volume decrease or to signal an intelligent power supply to increase the rail voltage from low to high for optimum
efficiency..
The device inverts the audio signal from input to output.
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23
TAS5631B
SLES263 – NOVEMBER 2010
www.ti.com
The VREG pin is not recommended to be used as a voltage source for external circuitry.
PRINTED CIRCUIT BOARD RECOMMENDATION
Use an unbroken ground plane to have good low-impedance and -inductance return path to the power supply for
power and audio signals. PCB layout, audio performance and EMI are linked closely together. The circuit
contains high, fast-switching currents; therefore, care must be taken to prevent damaging voltage spikes. Routing
for the audio input should be kept short and together with the accompanying audio source ground. It is important
to keep a solid local ground area underneath the device to minimize ground bounce. It is always good practice fo
follow the EVM layout as a guideline,
Netlist for this printed circuit board is generated from the schematic in Figure 14.
Note T1: PVDD decoupling bulk capacitors C60–C64 should be as close as possible to the PVDD and GND_X pins;
the heat sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and
without going through vias. No vias or traces should be blocking the current path.
Note T2: Close decoupling of PVDD with low-impedance X7R ceramic capacitors is placed under the heat sink and
close to the pins. This is valid for C60, C61, C62, and C63.
Note T3: Heat sink must have a good connection to PCB ground.
Note T4: Output filter capacitors must be linear in the applied voltage range, and preferably metal film types.
Figure 19. Printed Circuit Board – Top Layer
24
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TAS5631B
www.ti.com
SLES263 – NOVEMBER 2010
Note B1: It is important to have a direct, low-impedance return path for high current back to the power supply. Keep
impedance low from top to bottom side of PCB through a lot of ground vias.
Note B2: Bootstrap low-impedance X7R ceramic capacitors placed on bottom side provide a short low-inductance
current loop.
Note B3: Return currents from bulk capacitors and output filter capacitors
Figure 20. Printed Circuit Board – Bottom Layer
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Product Folder Link(s): TAS5631B
25
PACKAGE OPTION ADDENDUM
www.ti.com
23-Apr-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
TAS5631BDKD
PREVIEW
HSSOP
DKD
44
29
TBD
Call TI
Call TI
TAS5631BDKDR
PREVIEW
HSSOP
DKD
44
500
TBD
Call TI
Call TI
TAS5631BPHD
ACTIVE
HTQFP
PHD
64
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-4-260C-72 HR
TAS5631BPHDR
ACTIVE
HTQFP
PHD
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-4-260C-72 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Apr-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TAS5631BPHDR
Package Package Pins
Type Drawing
HTQFP
PHD
64
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
24.4
Pack Materials-Page 1
17.0
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
17.0
1.5
20.0
24.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Apr-2011
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TAS5631BPHDR
HTQFP
PHD
64
1000
346.0
346.0
41.0
Pack Materials-Page 2
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amplifier.ti.com
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www.ti.com/computers
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dataconverter.ti.com
Consumer Electronics
www.ti.com/consumer-apps
DLP® Products
www.dlp.com
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DSP
dsp.ti.com
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www.ti.com/industrial
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interface.ti.com
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logic.ti.com
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Power Mgmt
power.ti.com
Transportation and
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www.ti.com/automotive
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
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www.ti-rfid.com
Wireless
www.ti.com/wireless-apps
RF/IF and ZigBee® Solutions
www.ti.com/lprf
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