74ACT11377
OCTAL D-TYPE FLIP-FLOP
WITH CLOCK ENABLE
SCAS129 – D3450, MARCH 1990 – REVISED APRIL 1993
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•
•
•
•
•
•
•
•
DB, DW OR NT PACKAGE
(TOP VIEW)
Inputs Are TTL-Voltage Compatible
Contains Eight D-Type Flip-Flops
Clock Enable Latched to Avoid False
Clocking
Applications Include:
Buffer/Storage Registers
Shift Registers
Pattern Generators
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1-mm Process
500-mA Typical Latch-Up Immunity
at 125°C
Package Options Include Plastic
Small-Outline Packages, Plastic Shrink
Small-Outline Packages and Standard
Plastic 300-mil DIPs
1Q
2Q
3Q
4Q
GND
GND
GND
GND
5Q
6Q
7Q
8Q
t
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
CLKEN
1D
2D
3D
4D
VCC
VCC
5D
6D
7D
8D
CLK
description
These circuits are positive-edge-triggered D-type flip-flops with a clock enable input.
Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the
positive-going edge of the clock pulse if CLKEN is low. Clock triggering occurs at a particular voltage level and
is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high
or low level, the D input signal has no effect at the output. The circuits are designed to prevent false clocking
by transitions at the CLKEN input.
The 74ACT11377 is characterized for operation from – 40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
CLKEN
CLK
D
OUTPUT
Q
H
X
X
Q0
L
↑
H
H
L
↑
L
L
X
L
X
Q0
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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2–1
74ACT11377
OCTAL D-TYPE FLIP-FLOP
WITH CLOCK ENABLE
SCAS129 – D3450, MARCH 1990 – REVISED APRIL 1993
logic symbol†
CLKEN
CLK
1D
2D
3D
4D
5D
6D
7D
8D
24
logic diagram (positive logic)
13
23
CLK
G1
1C2
2D
1
22
2
21
3
20
4
17
9
16
10
15
11
14
12
CLKEN
1Q
2Q
1D
13
24
23
1
1D
3Q
1Q
C1
4Q
5Q
Six Identical
Stages
Not Shown
6Q
7Q
8Q
8D
14
12
1D
8Q
C1
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
} Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
recommended operating conditions
MIN
MAX
4.5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
High-level input voltage
2
UNIT
V
V
0.8
V
VCC
VCC
V
High-level output current
– 24
mA
IOL
Dt /Dv
Low-level output current
24
mA
0
10
ns / V
TA
Operating free-air temperature
– 40
85
°C
2–2
Input transition rise or fall rate
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• DALLAS, TEXAS 75265
V
74ACT11377
OCTAL D-TYPE FLIP-FLOP
WITH CLOCK ENABLE
SCAS129 – D3450, MARCH 1990 – REVISED APRIL 1993
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
4.5 V
IOH = – 50 mA
VOH
IOH = – 24 mA
IOH = – 75 mA{
VOL
IOL = 24 mA
IOL = 75 mA{
VI = VCC or GND
II
ICC
DICC}
TA = 25°C
TYP
MAX
MIN
4.4
4.4
5.5 V
5.4
5.4
4.5 V
3.94
3.8
5.5 V
4.94
MAX
UNIT
V
4.8
5.5 V
IOL = 50 mA
VOL
MIN
3.85
4.5 V
0.1
5.5 V
0.1
0.1
0.1
4.5 V
0.36
0.44
5.5 V
0.36
0.44
5.5 V
V
1.65
V
5.5 V
± 0.1
±1
mA
VI = VCC or GND,
IO = 0
5.5 V
8
80
mA
One input at 3.4 V,
Other inputs at GND or VCC
5.5 V
0.9
1
mA
Ci
VI = VCC or GND
5V
4
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
pF
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
fclock
Clock frequency
tw
Pulse duration
0
Setup time before CLK↑
↑
tsu
Hold time after CLK↑
↑
th
100
MIN
MAX
UNIT
0
100
MHz
CLK high
5
5
CLK low
5
5
Data
4
4
CLKEN high
4
4
CLKEN low
5
5
CLKEN high or low
0
0
Data high
1
1
Data low
0
0
ns
ns
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
MIN
TA = 25°C
TYP
MAX
100
CLK
Any Q
MIN
MAX
100
UNIT
MHz
4.5
9.1
12.2
4.5
13.8
4.8
9.6
12.7
4.8
14.2
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
CL = 50 pF,
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f = 1 MHz
TYP
UNIT
68
pF
2–3
74ACT11377
OCTAL D-TYPE FLIP-FLOP
WITH CLOCK ENABLE
SCAS129 – D3450, MARCH 1990 – REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
tw
CL = 50 pF
(see Note A)
3V
500 Ω
Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
LOAD CIRCUIT
3V
Input
(see Note B)
3V
Timing Input
(see Note B)
0V
tsu
Data Input
1.5 V
0V
tPHL
tPLH
1.5 V
th
1.5 V
In-Phase
Output
50% VCC
3V
1.5 V
tPLH
tPHL
1.5 V
0V
Out-of-Phase
Output
VOH
50% VCC
VOL
50% VCC
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
2–4
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