DRV201 SLVSB25 – AUGUST 2011 www.ti.com VOICE COIL MOTOR DRIVER FOR CAMERA AUTO FOCUS Check for Samples: DRV201 FEATURES • • • • 1 • • • • • • Configurable for Linear or PWM Mode VCM Current Generation High Efficiency PWM Current Control for VCM Advanced Ringing Compensation Integrated 10-bit D/A Converter for VCM Current Control Protection – Open and Short-Circuit Detection on VCM Pins – Undervoltage Lockout (UVLO) – Thermal Shutdown – Open and Short Circuit Protection on VCM Output – Internal Current Limit for VCM Driver I2C Interface Operating Temperature Range: -40ºC to 85ºC 6-Ball WCSP Package With 0.4-mm Pitch Max Die Size: 0.8 mm x 1.48 mm Package Height: 0.15 mm APPLICATIONS • • • • • • Cell Phone Auto Focus Digital Still Camera Auto Focus Iris/Exposure Control Security Cameras Web and PC Cameras Actuator Controls DESCRIPTION The DRV201 is an advanced voice coil motor driver for camera auto focus. It has an integrated D/A converter for setting the VCM current. VCM current is controlled with a fixed frequency PWM controller or a linear mode driver. Current generation can be selected via I2C register. The DRV201 has an integrated sense resistor for current regulation and the current can be controlled through I2C. When changing the current in the VCM, the lens ringing is compensated with an advanced ringing compensation function. Ringing compensation reduces the needed time for auto focus significantly. The device also has VCM short and open protection functions. FUNCTIONAL BLOCK DIAGRAM Cin POR 10-bit DAC DIGITAL GATE CONTROL REFERENCE PWM OSCILLATOR ERROR AMPLIFIER VBAT ISOURCE VCM REGISTERS RINGING COMPENSATION SCL ISINK I2C Rsense SDA GND 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated DRV201 SLVSB25 – AUGUST 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) (1) (2) TA PACKAGE (2) ORDERABLE PART NUMBER -40°C to 85°C YFM DRV201YFMR For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. DEVICE INFORMATION NanoFree PACKAGE (BOTTOM VIEW) SCL I SOURCE VBAT SDA I SINK GND C B A 2 1 TERMINAL FUNCTIONS TERMINAL 2 I/O DESCRIPTION NAME NO. VBAT 2A Power GND 1A Ground I_SOURCE 2B Voice coil positive terminal I_SINK 1B SCL 2C I SDA 1C I/O Voice coil negative terminal I2C serial interface clock input I2C serial interface data input/output (open drain) Copyright © 2011, Texas Instruments Incorporated DRV201 SLVSB25 – AUGUST 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) VBAT, ISOURCE, ISOURCE pin voltage range (1) (2) Voltage range at SDA, SCL VALUE UNIT –0.3 to 5.5 V –0.3 to 3.6 V Continuous total power dissipation θJA Junction-to-ambient thermal resistance (3) TJ TA Tstg 130 °C/W Operating junction temperature -40 to 125 °C Operating ambient temperature -40 to 85 °C Storage temperature -55 to 150 °C ESD rating (1) (2) (3) Internally limited (HBM) Human body model ±4000 (CDM) Charged device model ±500 V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. This thermal data is measured with high-K board (4-layer board). ELECTRICAL CHARACTERISTICS Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature range of 25°C) (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 2.5 3.7 4.8 UNIT INPUT VOLTAGE VBAT Input supply voltage VUVLO Undervoltage lockout threshold VHYS Undervoltage lockout hysteresis VBAT rising VBAT falling 2.2 2 50 V V 100 250 mV INPUT CURRENT ISHUTDOWN Input supply current shutdown, includes switch leakage currents MAX: VBAT = 4.4 V 0.15 1 µA ISTANDBY Input supply current standby, includes switch leakage currents MAX: VBAT = 4.4 V 120 200 µA STARTUP, MODE TRANSITIONS, AND SHUTDOWN t1 Shutdown to standby 100 µs t2 Standby to active 100 µs t3 Active to standby t4 Shutdown time Active or standby to shutdown 0.5 100 µs 1 ms VCM DRIVER STAGE Resolution IRES 10 Relative accuracy Differential nonlinearity 10 -1 1 Zero code error Offset error 0 At code 32 LSB mA 3 mA % of FSR Gain error ±3 Gain error drift 0.3 0.4 %/°C Offset error drift 0.3 0.5 %/°C IMAX Maximum output current ILIMIT Average VCM current limit (1) bits -10 102.3 See (1) 110 160 mA 240 mA During short circuit condition driver current limit comparator will trip and short is detected and driver goes into STANDBY and short flag is set high in the status register. Copyright © 2011, Texas Instruments Incorporated 3 DRV201 SLVSB25 – AUGUST 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature range of 25°C) (unless otherwise noted) PARAMETER IDETCODE Minimum VCM code for OPEN and SHORT detection fSW Switching frequency VDRP Internal dropout LVCM VCM inductance RVCM VCM resistance TEST CONDITIONS See (2) Selectable through CONTROL register See MIN TYP MAX 256 UNIT mA 0.5 4 (3) MHz 0.4 V 30 150 µH 11 22 Ω LENS MOVEMENT CONTROL tset1 Lens settling time ±10% error band tset2 Lens settling time ±10% error band fVCM VCM resonance frequency 2/fVCM ms 1/fVCM ms 50 150 Hz -20 20 % V = 3.6 V, SCL -20 20 V = 3.6 V, SDA -1 1 VCM resonance frequency tolerance LOGIC I/Os (SDA AND SCL) IIN Input leakage current RPullUp I2C pull-up resistors SDA and SCL pins VIH Input high level See (4) VIL Input low level See (5) tTIMEOUT SCL timeout for shutdown detection RPD Pull down resistor at SCL line fSCL I2C clock frequency 4.7 µA kΩ 1.17 3.6 0 0.63 0.5 1 ms 400 kHz 500 V V kΩ INTERNAL OSCILLATOR fOSC Internal oscillator 20°C ≤ TA ≤ 70°C -3 3 % Frequency accuracy -40°C ≤ TA ≤ 85°C -5 5 % THERMAL SHUTDOWN TTRIP (2) (3) (4) (5) 4 Thermal shutdown trip point 140 °C When testing VCM open or short this is the recommended minimum VCM code (in dec) to be used. This is the voltage that is needed for the feedback resistor and high side driver. It should be noted that the maximum VCM resistance is limited by this voltage and supply voltage. E.g. 3-V supply maximum VCM resistance is: RVCM = (VBAT – VDRP)/IVCM = (3 V - 0.4 V)/102.3 mA = 25.4 Ω. During shutdown to standby transition VIH low limit is 1.28 V. During shutdown to standby transition VIL low limit is 0.51 V. Copyright © 2011, Texas Instruments Incorporated DRV201 SLVSB25 – AUGUST 2011 www.ti.com FUNCTIONAL DESCRIPTION The DRV201 is intended for high performance autofocus in camera modules. It is used to control the current in the voice coil motor (VCM). The current in the VCM generates a magnetic field which forces the lens stack connected to a spring to move. The VCM current and thus the lens position can be controlled via the I2C interface and an auto focus function can be implemented. The device connects to a video processor or image sensor through a standard I2C interface which supports up to 400-kbit/s data rate. The digital interface supports IO levels from 1.8 V to 3.3 V. All pins have 4-kV HBM ESD rating. When SCL is low for at least 0.5 ms, the device enters SHUTDOWN mode. If SCL goes from low to high the driver enters STANDBY mode in less than 100 μs and default register values are set as shown in Figure 1. ACTIVE mode is entered when ever the VCM_CURRENT register is set to something else than zero. Vbat ISC/SCL t1 DAC mode t2 SHUTDOWN =0 0 =0 STANDBY t4 t3 ACTIVE STANDBY SHUTDOWN Figure 1. Power Up and Down Sequence VCM current can be controlled via an I2C interface and VCM_CURRENT registers. Lens stack is connected to a spring which causes a dampened ringing in the lens position when current is changed. This mechanical ringing is compensated internally by generating an optimized ramp when ever the current value in the VCM_CURRENT register is changed. This enables a fast autofocus algorithm and pleasant user experience. Current in the VCM can be generated with a linear or PWM control. In linear mode the high side PMOS is configured as a current source and current is set by the VCM_CURRENT control register. In PWM control the VCM is driven with a half bridge driver. With PWM control the VCM current is increased by connecting the VCM between VBAT and GND through the high side PMOS and then released to a ‘freewheeling’ mode through the sense resistor and low side NMOS. PWM mode switching frequency can be selected from 0.5 MHz up to 4 MHz through a CONTROL register. PWM or linear mode can be selected with the PWM/LIN bit in the MODE register. Copyright © 2011, Texas Instruments Incorporated 5 DRV201 SLVSB25 – AUGUST 2011 www.ti.com MODES OF OPERATION SHUTDOWN If the driver detects SCL has a DC level below 0.63 V for duration of at least 0.5 ms, the driver will enter shutdown mode. This is the lowest power mode of operation. The driver will remain in shutdown for as long as SCL pin remain low. STANDBY If SCL goes from low to high the driver enters STANDBY mode and sets the default register values. In this mode registers can be written to through the I2C interface. Device will be in STANDBY mode when VCM_CURRENT register is set to zero. From ACTIVE mode the device will enter STANDBY if the SW_RST bit of the CONTROL register is set. In this case all registers will be reset to default values. STANDBY mode is entered from ACTIVE mode if any of the following faults occur: Over temperature protection fault (OTPF), VCM short (VCMS), or VCM open (VCMO). When STANDBY mode is entered due to a fault condition current register is cleared. ACTIVE The device is in ACTIVE mode whenever the VCM_CURRENT control is set to something else than zero through the I2C interface. In ACTIVE mode VCM driver output stage is enabled all the time resulting in higher power consumption. The device remains in active mode until the SW_RST bit in the CONTROL register is set, SCL is pulled low for duration of 0.5 ms, VCM_CURRENT control is set to zero, or any of the following faults occur: Over temperature protection fault (OTPF), VCM short (VCMS), or VCM open (VCMO). If active mode is entered after fault the status register is automatically cleared. 6 Copyright © 2011, Texas Instruments Incorporated DRV201 SLVSB25 – AUGUST 2011 www.ti.com VCM DRIVER OUTPUT STAGE OPERATION Current in the VCM can be controlled with a linear or PWM mode output stage. Output stage is enabled in ACTIVE mode which can be controlled through VCM_CURRENT control register and the output stage mode is selected from MODE register bit PWM/LIN. In linear mode the output PMOS is configured to a high side current source and current can be controlled from a VCM_CURRENT registers. In PWM control the VCM is driven with a half bridge driver. With PWM control the VCM current is increased by connecting the VCM between VBAT and GND through the high side PMOS and then released to a ‘freewheeling’ mode through the sense resistor and low side NMOS. Current in the VCM is sensed with a 1-Ω sense resistor which is connected into an error amplifier input where the other input is controlled by the 10-bit DAC output. PWM mode switching frequency can be selected from 0.5 MHz up to 4 MHz through a CONTROL register. PWM or linear mode can be selected with the PWM/LIN bit in the MODE register. RINGING COMPENSATION VCM current can be controlled via an I2C interface and VCM_CURRENT registers. Lens stack is connected to a spring which causes a dampened ringing in the lens position when current is changed. This mechanical ringing is compensated internally by generating an optimized ramp when ever the current value in the VCM_CURRENT register is changed. This enables a fast auto focus algorithm and pleasant user experience. Ringing compensation is dependent on the VCM resonance frequency and this can be controlled via VCM_FREQ register from 50 Hz up 152 Hz with 0.4-Hz steps. Ringing compensation is designed in a way that it can tolerate ±20% frequency variation in the VCM resonance frequency so only statistical data from the VCM is needed in production. I2C BUS OPERATION The DRV201 hosts a slave I2C interface that supports data rates up to 400 kbit/s and auto-increment addressing and is compliant to I2C standard 3.0. Slave Address + R/nW Start G3 G2 G1 G0 A2 A1 A0 Sub Address R/nW ACK S7 S6 S5 S4 S3 S2 Data S1 S0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK Stop Figure 2. Subaddress in I2C Transmission Start – Start condition G(3:0) – Group ID: Address fixed at '0001' A(2:0) – Device Address: Address fixed at '110' R/nW – Read/not Write select bit ACK – Acknowledge S(7:0) – Subaddress: Defined per register map D(7:0) – Data: Data to be loaded into the device Stop – Stop condition The I2C Bus is a communications link between a controller and a series of slave terminals. The link is established using a two-wire bus consisting of a serial clock signal (SCL) and a serial data signal (SDA). The serial clock is sourced from the controller in all cases where the serial data line is bi-directional for data communication between the controller and the slave terminals. Each device has an open drain output to transmit data on the serial data line. An external pull-up resistor must be placed on the serial data line to pull the drain output high during data transmission. Copyright © 2011, Texas Instruments Incorporated 7 DRV201 SLVSB25 – AUGUST 2011 www.ti.com Data transmission is initiated with a start bit from the controller as shown in Figure 3. The start condition is recognized when the SDA line transitions from high to low during the high portion of the SCL signal. Upon reception of a start bit, the device will receive serial data on the SDA input and check for valid address and control information. If the appropriate slave address bits are set for the device, then the device will issue an acknowledge pulse and prepare to receive the register address. Depending on the R/nW bit, the next byte received from the master is written to the addressed register (R/nW = 0) or the device responds with 8-bit data from the register (R/nW = 1). Data transmission is completed by either the reception of a stop condition or the reception of the data word sent to the device. A stop condition is recognized as a low to high transition of the SDA input during the high portion of the SCL signal. All other transitions of the SDA line must occur during the low portion of the SCL signal. An acknowledge is issued after the reception of valid address, sub-address and data words. The I2C interfaces will auto-sequence through register addresses, so that multiple data words can be sent for a given I2C transmission. Reference Figure 4. ... SDA SCL 1 2 3 4 5 START CONDITION 6 7 8 ... 9 STOP CONDITION ACKNOWLEDGE 2 Figure 3. I C Start/Stop/Acknowledge Protocol tLOW tr tH(STA) tf SCL tH(STA) tH(DAT) tHIGH tS(DAT) tS(STO) tS(STA) SDA t(BUF) P S S P Figure 4. I2C Data Transmission Protocol 8 Copyright © 2011, Texas Instruments Incorporated DRV201 SLVSB25 – AUGUST 2011 www.ti.com DATA TRANSMISSION TIMING VBAT = 3.6 V ±5%, TA = 25ºC, CL = 100 pF (unless otherwise noted) PARAMETER f(SCL) Serial clock frequency tBUF Bus Free Time Between Stop and Start Condition tSP Tolerable spike width on bus tLOW SCL low time tHIGH SCL high time tS(DAT) SDA → SCL setup time tS(STA) Start condition setup time tS(STO) TEST CONDITIONS Stop condition setup time tH(DAT) SDA → SCL hold time tH(STA) Start condition hold time tr(SCL) Rise time of SCL Signal tf(SCL) Fall time of SCL Signal tr(SDA) Rise time of SDA Signal tf(SDA) Rise time of SDA Signal Copyright © 2011, Texas Instruments Incorporated MIN TYP 100 SCL = 100 KHz 4.7 SCL = 400 KHz 1.3 SCL = 100 KHz MAX 400 SCL = 400 KHz 4.7 SCL = 400 KHz 1.3 KHz µs 50 SCL = 100 KHz UNIT ns µs SCL = 100 KHz 4 µs SCL = 400 KHz 600 ns SCL = 100 KHz 250 SCL = 400 KHz 100 ns µs SCL = 100 KHz 4.7 SCL = 400 KHz 600 ns SCL = 100 KHz 4 µs SCL = 400 KHz 600 SCL = 100 KHz 0 3.45 SCL = 400 KHz 0 0.9 SCL = 100 KHz 4 SCL = 400 KHz 600 ns µs µs ns SCL = 100 KHz 1000 SCL = 400 KHz 300 SCL = 100 KHz 300 SCL = 400 KHz 300 SCL = 100 KHz 1000 SCL = 400 KHz 300 SCL = 100 KHz 300 SCL = 400 KHz 300 ns ns ns ns 9 DRV201 SLVSB25 – AUGUST 2011 www.ti.com REGISTER ADDRESS MAP DEFAULT VALUE REGISTER ADDRESS (HEX) NAME DESCRIPTION 1 01 not used 2 02 CONTROL 0000 0010 Control register 3 03 VCM_CURRENT_MSB 0000 0000 Voice coil motor MSB current control 4 04 VCM_CURRENT_LSB 0000 0000 Voice coil motor LSB current control 5 05 STATUS 0000 0000 Status register 6 06 MODE 0000 0000 Mode register 7 07 VCM_FREQ 1000 0011 VCM resonance frequency CONTROL REGISTER (CONTROL) Address – 0x02h DATA BIT D7 D6 D5 D4 D3 D2 D1 D0 FIELD NAME not used not used not used not used not used not used EN_RING RESET READ/WRITE R R R R R R R/W R/W RESET VALUE 0 0 0 0 0 0 1 0 FIELD NAME BIT DEFINITION Forced software reset (reset all registers to default values) and device goes into STANDBY. RESET bit is automatically cleared when written high. RESET 0 – inactive 1 – device goes to STANDBY Enables ringing compensation. EN_RING 0 – disabled 1 – enabled VCM MSB CURRENT CONTROL REGISTER (VCM_CURRENT_MSB) Address – 0x03h DATA BIT D7 D6 D5 D4 D3 D2 FIELD NAME not used not used not used not used not used not used READ/WRITE R R R R R R RESET VALUE 0 0 0 0 0 0 FIELD NAME D1 D0 VCM_CURRENT[9:0] R/W 0 0 BIT DEFINITION VCM current control 00 0000 0000b – 0 mA 00 0000 0001b – 0.1 mA VCM_CURRENT[9:0] 00 0000 0010b – 0.2 mA … 11 1111 1110b – 102.2 mA 11 1111 1111b – 102.3 mA 10 Copyright © 2011, Texas Instruments Incorporated DRV201 SLVSB25 – AUGUST 2011 www.ti.com VCM LSB CURRENT CONTROL REGISTER (VCM_CURRENT_LSB) Address – 0x04h DATA BIT D7 D6 D5 FIELD NAME D4 D3 D2 D1 D0 0 0 0 VCM_CURRENT[7:0] READ/WRITE R/W RESET VALUE 0 0 0 0 FIELD NAME 0 BIT DEFINITION VCM current control 00 0000 0000b – 0 mA 00 0000 0001b – 0.1 mA VCM_CURRENT[7:0] 00 0000 0010b – 0.2 mA … 11 1111 1110b – 102.2 mA 11 1111 1111b – 102.3 mA STATUS REGISTER (STATUS) (1) Address – 0x05h (1) DATA BIT D7 D6 D5 D4 D3 D2 D1 D0 FIELD NAME not used not used not used TSD VCMS VCMO UVLO OVC READ/WRITE R R/WR R R R R R R RESET VALUE 0 0 0 0 0 0 0 0 Status bits are cleared when device changes it’s state from standby to active. If TSD was tripped the device goes into Standby and will not allow the transition into Active until the device cools down and TSD is cleared. FIELD NAME BIT DEFINITION OVC Over current detection UVLO Undervoltage Lockout VCMO Voice coil motor open detected VCMS Voice coil motor short detected TSD Thermal shutdown detected Copyright © 2011, Texas Instruments Incorporated 11 DRV201 SLVSB25 – AUGUST 2011 www.ti.com MODE REGISTER (MODE) Address – 0x06h DATA BIT D7 D6 D5 D4 D3 D2 PWM_FREQ[2:0] D1 D0 PWM/LIN RING_MOD E FIELD NAME not used not used not used READ/WRITE R R R R/W R/W R/W R/W R/W RESET VALUE 0 0 0 0 0 0 0 0 D2 D1 D0 0 1 1 FIELD NAME BIT DEFINITION Ringing compensation settling time RING_MODE 0 – 2x(1/fVCM) 1 – 1x(1/fVCM) Driver output stage in linear or PWM mode PWM/LIN 0 – PWM mode 1 – Linear mode Output stage PWM switching frequency 000 – 0.5 MHz 001 – 1 MHz 010 – N/A PWM_FREQ[2:0] 011 – 2 MHz 100 – N/A 101 – N/A 110 – N/A 111 – 4 MHz VCM RESONANCE FREQUENCY REGISTER (VCM_FREQ) Address – 0x07h DATA BIT D7 D6 D5 D4 FIELD NAME READ/WRITE RESET VALUE D3 VCM_FREQ[7:0] R/W 1 0 0 FIELD NAME 0 0 BIT DEFINITION VCM mechanical ringing frequency for the ringing compensation can be selected with the below formula. The formula gives the VCM_FREQ[7:0] register value in decimal which should be rounded to the nearest integer. VCM_FREQ[7:0] VCM _ FREQ = 383 - 19200 Fres (1) Default VCM mechanical ringing frequency is 76.4 Hz. VCM _ FREQ = 383 - 12 19200 = 131.69 Þ 132 Þ '1000 0011' 76.4 (2) Copyright © 2011, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 9-Sep-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) DRV201YFMR ACTIVE DSLGA YFM 6 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM DRV201YFMT ACTIVE DSLGA YFM 6 250 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Sep-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DRV201YFMR DSLGA YFM 6 3000 180.0 8.4 0.85 1.52 0.19 4.0 8.0 Q1 DRV201YFMT DSLGA YFM 6 250 180.0 8.4 0.85 1.52 0.19 4.0 8.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Sep-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV201YFMR DSLGA YFM 6 3000 210.0 185.0 35.0 DRV201YFMT DSLGA YFM 6 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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